1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-01 16:33:37 +01:00
Commit Graph

217 Commits

Author SHA1 Message Date
Daniel Dunbar
f254edca8d MC/Mach-O: Add another zerofill test to improve coverage.
llvm-svn: 103691
2010-05-13 01:10:28 +00:00
Chris Lattner
ca57d80f83 fix rdar://7965971 and a fixme: use ParseIdentifier in
ParseDirectiveDarwinZerofill instead of hard coding the
check for identifier. This allows quoted symbol names to
be used.

llvm-svn: 103682
2010-05-13 00:10:34 +00:00
Chris Lattner
887e8f9f53 reapply r103668 with a fix. Never make "minor syntax changes"
after testing before committing.

llvm-svn: 103681
2010-05-13 00:02:47 +00:00
Chris Lattner
361c115f23 revert r103668 for now, it is apparently breaking things.
llvm-svn: 103677
2010-05-12 23:40:59 +00:00
Chris Lattner
91a836a9c7 moffset forms of moves are x86-32 only, make the parser
lower them to the correct x86-64 instructions since we 
don't have a clean way to handle this in td files yet.
rdar://7947184

llvm-svn: 103668
2010-05-12 23:13:36 +00:00
Chris Lattner
1960255123 fix the encoding of the obscure "moffset" forms of moves, i386
part first.  rdar://7947184

llvm-svn: 103660
2010-05-12 22:48:24 +00:00
Daniel Dunbar
469dddef0e MC/X86: Extend suffix matching hack to match 'q' suffix.
llvm-svn: 103535
2010-05-12 00:54:20 +00:00
Daniel Dunbar
e5a79692cf MC/Mach-O/x86_64: Add a new hook for checking whether a particular section can
be diced into atoms, and adjust getAtom() to take this into account.
 - This fixes relocations to symbols in fixed size literal sections, for
   example.

llvm-svn: 103532
2010-05-12 00:38:17 +00:00
Daniel Dunbar
a033860d55 MC/Mach-O/x86_64: Fix PCrel adjustment for x86_64, which was using the fixup
offset instead of the fixup address as intended.

llvm-svn: 103527
2010-05-11 23:53:11 +00:00
Daniel Dunbar
7670f69e42 MC/Mach-O x86_64: Switch to using fragment atom symbol.
- This eliminates getAtomForAddress() (which was a linear search) and
   simplifies getAtom().
 - This also fixes some correctness problems where local labels at the same
   address as non-local labels could be assigned to the wrong atom.

llvm-svn: 103480
2010-05-11 17:22:50 +00:00
Daniel Dunbar
d2c14ce38d MC/Mach-O: Fix another mismatch with .weak_definition, we shouldn't use a
scattered relocation entry with a .weak_definition.

llvm-svn: 103443
2010-05-10 23:15:20 +00:00
Kevin Enderby
3807a4746a Fix i386 relocations to Weak Definitions. The relocation entries should be
external and the item to be relocated should not have the address of the
symbol added in.

llvm-svn: 103302
2010-05-07 21:44:23 +00:00
Daniel Dunbar
45589cd853 MC/X86: X86AbsMemAsmOperand is subclass of X86NoSegMemAsmOperand.
- This fixes "leal 0, %eax", for example.

llvm-svn: 103205
2010-05-06 22:39:14 +00:00
Chris Lattner
c788971da7 fix rdar://7947167 - llvm-mc doesn't match movsq
llvm-svn: 103199
2010-05-06 21:48:14 +00:00
Sean Callanan
4331428e24 Eliminated the classification of control registers into %ecr_
and %rcr_, leaving just %cr_ which is what people expect.
Updated the disassembler to support this unified register set.
Added a testcase to verify that the registers continue to be
decoded correctly.

llvm-svn: 103196
2010-05-06 20:59:00 +00:00
Daniel Dunbar
a3731b17c0 Revert r103137, fix for $ in labels. It looks like we can't actually handle this
at the token level. Consider the following horrible test case:

  a = 1
  .globl $a
  movl ($a), %eax
  movl $a, %eax
  movl $$a, %eax

llvm-svn: 103178
2010-05-06 14:46:38 +00:00
Chris Lattner
ca80f41a4d fix rdar://7946934 - in some limited cases, the assembler should
allow $ at the start of a symbol name.

llvm-svn: 103137
2010-05-05 23:51:28 +00:00
Daniel Dunbar
9a3d46162f MC/Mach-O: Mark absolute variable's appropriately, and add Mach-O support for
writing them.
 - <rdar://problem/7885351> integrated assembler broken for i386 objc code

llvm-svn: 103112
2010-05-05 19:01:05 +00:00
Daniel Dunbar
f5dc70a7d1 MC/Mach-O/x86_64: Relocations in debug sections should use local relocations
when possible.
 - <rdar://problem/7934873>

llvm-svn: 103092
2010-05-05 17:22:39 +00:00
Daniel Dunbar
e335a71a56 MC/X86: Chris pointed that 'as' isn't consistent in accepting the long form of
instructions which have no direct register usage.

Darwin 'as' accepts:
  add $0, (%rax)
but rejects
  mov $0, (%rax)
for example.

Given that, only accept suffix matches which match exactly one form. We still
need to emit nice diagnostics for failures...

llvm-svn: 103015
2010-05-04 17:31:02 +00:00
Daniel Dunbar
648d1ae783 MC/X86: Add "support" for matching ATT style mnemonic prefixes.
- The idea is that when a match fails, we just try to match each of +'b', +'w',
   +'l'. If exactly one matches, we assume this is a mnemonic prefix and accept
   it. If all match, we assume it is width generic, and take the 'l' form.

 - This would be a horrible hack, if it weren't so simple. Therefore it is an
   elegant solution! Chris gets the credit for this particular elegant
   solution. :)

 - Next step to making this more robust is to have the X86 matcher generate the
   mnemonic prefix information. Ideally we would also compute up-front exactly
   which mnemonic to attempt to match, but this may require more custom code in
   the matcher than is really worth it.

llvm-svn: 103012
2010-05-04 16:12:42 +00:00
Kevin Enderby
ce7a24a57f Changed llvm-mc to use the same suffixes with floating point compare
instructions as the Mac OS X darwin assembler.  Some of which like 'fcoml'
assembled to different opcodes.  While some of the suffixes were just different.

llvm-svn: 102958
2010-05-03 21:31:40 +00:00
Kevin Enderby
be2804f752 Fixed the encoding of two of the X86 movq instuctions. The Move quadword from
mm to mm/m64 and the Move quadword from xmm2/mem64 to xmm1 had the incorrect
encodings.

llvm-svn: 102952
2010-05-03 21:03:31 +00:00
Kevin Enderby
c1eeb061e7 Fixed the encoding of the x86 push instructions. Using a 32-bit immediate value
caused the a pushl instruction to be incorrectly encoding using only two bytes
of immediate, causing the following 2 instruction bytes to be part of the 32-bit
immediate value.  Also fixed the one byte form of push to be used when the
immediate would fit in a signed extended byte.  Lastly changed the names to not
include the 32 of PUSH32 since they actually push the size of the stack pointer.

llvm-svn: 102951
2010-05-03 20:45:05 +00:00
Kevin Enderby
58bed5a913 Fixed the word sized Bit Scan Forward/Reverse instructions, they needed the
Operand size override prefix to be part of their records.

llvm-svn: 102556
2010-04-28 23:20:40 +00:00
Johnny Chen
6e4b1607ee Thumb instructions which have reglist operands at the end and predicate operands
before reglist were not properly handled with respect to IT Block.  Fix that by
creating a new method ARMBasicMCBuilder::DoPredicateOperands() used by those
instructions for disassembly.  Add a test case.

llvm-svn: 101974
2010-04-21 01:01:19 +00:00
Johnny Chen
9998480f92 When doing Thumb disassembly, there's no need to consider t2ADDrSPi12/t2SUBrSPi12,
as their generic counterparts t2ADDri12/t2SUBri12 should suffice.

llvm-svn: 101929
2010-04-20 18:45:24 +00:00
Johnny Chen
bd5bf58029 For t2LDRT, t2LDRBT, t2LDRHT, t2LDRSBT, and t2LDRSHT, if Rn(Inst{19-16})=='1111',
transform the Opcode to the corresponding t2LDR*pci counterpart.

Ref: A8.6.86 LDRT, A8.6.65 LDRBT, A8.6.77 LDRHT, A8.6.81 LDRSBT, A8.6.85 LDRSHT
llvm-svn: 101915
2010-04-20 17:28:50 +00:00
Johnny Chen
fe24cdbba8 According to A8.6.16 B (Encoding T3) and A8.3 Conditional execution -- A8.3.1
Pseudocode details of conditional, Condition bits '111x' indicate the
instruction is always executed.  That is, '1111' is a leagl condition field
value, which is now mapped to ARMCC::AL.

Also add a test case for condition field '1111'.

llvm-svn: 101817
2010-04-19 21:19:52 +00:00
Johnny Chen
091c01cb2f ARM disassembler did not react to recent changes to the NEON instruction table.
VLD1q*_UPD and VST1q*_UPD have the ${dst:dregpair} operand now.

llvm-svn: 101784
2010-04-19 16:20:34 +00:00
Chris Lattner
65d1e40895 teach the x86 asm parser how to handle segment prefixes
in memory operands.  rdar://7874844

llvm-svn: 101661
2010-04-17 18:56:34 +00:00
Chris Lattner
80a22bfcdb testcase for r101538, patch by Nico Schmidt!
llvm-svn: 101642
2010-04-17 17:22:06 +00:00
Chris Lattner
42337931b2 a bunch of ssse3 instructions are misencoded to think they have an
i8 field when they really do not.  This fixes rdar://7840289

llvm-svn: 101629
2010-04-17 07:38:24 +00:00
Johnny Chen
1b78f89844 Minor change to make the test case comply with Vd<0> == '0' when Q == '1'.
llvm-svn: 101559
2010-04-16 22:48:31 +00:00
Johnny Chen
44087236da Fixed a bug in DisassembleN1RegModImmFrm() where a break stmt was missing for a
case.  Also, the 0xFF hex literal involved in the shift for ESize64 should be
suffixed "ul" to preserve the shift result.

Implemented printHex*ImmOperand() by copying from ARMAsmPrinter.cpp and added a
test case for DisassembleN1RegModImmFrm()/printHex64ImmOperand().

llvm-svn: 101557
2010-04-16 22:40:20 +00:00
Johnny Chen
7ac96eac03 In the same spirit of r101524, which removed the assert() from printAddrMode2OffsetOperand(),
this patch removes the assert() from printAddrMode3OffsetOperand() and adds a test case.

llvm-svn: 101529
2010-04-16 19:57:21 +00:00
Johnny Chen
3cc0200f74 Multiclass LdStCop was using pre-UAL syntax LDC<c>L for the L fragment. Changed
to the UAL syntax of LDCL<c>, instead.

Add a test case for this change which also tests the removal of assert() from
printAddrMode2OffsetOperand().

llvm-svn: 101527
2010-04-16 19:33:23 +00:00
Johnny Chen
0017916a36 Added another test case for am3offset operand, testing Rn, #+/-imm8.
Previous checkin tested Rn, #+/-Rm.

llvm-svn: 101418
2010-04-15 23:23:40 +00:00
Johnny Chen
53225c4582 Fixed a bug in ARM disassembly where LDRSBT should have am3offset operand, not
am2offset.  Modified the instruction table entry and added a new test case.

llvm-svn: 101415
2010-04-15 23:12:47 +00:00
Daniel Dunbar
cc40ce33de tests: MC/Disassembler tests depend on ARM support being compiler in.
llvm-svn: 101337
2010-04-15 03:47:20 +00:00
Chris Lattner
124dc743bc implement mc asmparser support for '.', which gets the
current PC.  rdar://7834775

We now produce an identical .o file compared to the cctools
assembler for something like this:

_f0:
L0:
        jmp L1
        .long . - L0
L1:
        jmp A
        .long . - L1

        .zerofill __DATA,_bss,A,0

llvm-svn: 101227
2010-04-14 04:40:28 +00:00
Johnny Chen
7a729daf31 Fixed a crasher in arm disassembler within ARMInstPrinter.cpp after calling
ARM_AM::getSoImmVal(V) with a legitimate so_imm value: #245 rotate right by 2.
Introduce ARM_AM::getSOImmValOneOrNoRotate(unsigned Arg) which is called from
ARMInstPrinter.cpp's printSOImm() function, replacing ARM_AM::getSOImmVal(V).

[12:44:43] johnny:/Volumes/data/llvm/git/trunk (local-trunk) $ gdb Debug/bin/llvm-mc
GNU gdb 6.3.50-20050815 (Apple version gdb-1346) (Fri Sep 18 20:40:51 UTC 2009)
Copyright 2004 Free Software Foundation, Inc.
GDB is free software, covered by the GNU General Public License, and you are
welcome to change it and/or distribute copies of it under certain conditions.
Type "show copying" to see the conditions.
There is absolutely no warranty for GDB.  Type "show warranty" for details.
This GDB was configured as "x86_64-apple-darwin"...Reading symbols for shared libraries ... done

(gdb) set args  -triple=arm-apple-darwin9 -debug-only=arm-disassembler --disassemble
(gdb) r
Starting program: /Volumes/data/llvm/git/trunk/Debug/bin/llvm-mc -triple=arm-apple-darwin9 -debug-only=arm-disassembler --disassemble
Reading symbols for shared libraries ++. done
0xf5 0x71 0xf0 0x53
Opcode=201 Name=MVNi Format=ARM_FORMAT_DPFRM(4)
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
-------------------------------------------------------------------------------------------------
| 0: 1: 0: 1| 0: 0: 1: 1| 1: 1: 1: 1| 0: 0: 0: 0| 0: 1: 1: 1| 0: 0: 0: 1| 1: 1: 1: 1| 0: 1: 0: 1|
-------------------------------------------------------------------------------------------------

	mvnpls	r7, Assertion failed: (V != -1 && "Not a valid so_imm value!"), function printSOImm, file ARMInstPrinter.cpp, line 229.

Program received signal SIGABRT, Aborted.
0x00007fff88c65886 in __kill ()
(gdb) bt
#0  0x00007fff88c65886 in __kill ()
#1  0x00007fff88d05eae in abort ()
#2  0x00007fff88cf2ef0 in __assert_rtn ()
#3  0x000000010020e422 in printSOImm (O=@0x1010bdf80, V=-1, VerboseAsm=false, MAI=0x1020106d0) at ARMInstPrinter.cpp:229
#4  0x000000010020e5fe in llvm::ARMInstPrinter::printSOImmOperand (this=0x1020107e0, MI=0x7fff5fbfee70, OpNum=1, O=@0x1010bdf80) at ARMInstPrinter.cpp:254
#5  0x00000001001ffbc0 in llvm::ARMInstPrinter::printInstruction (this=0x1020107e0, MI=0x7fff5fbfee70, O=@0x1010bdf80) at ARMGenAsmWriter.inc:3236
#6  0x000000010020c27c in llvm::ARMInstPrinter::printInst (this=0x1020107e0, MI=0x7fff5fbfee70, O=@0x1010bdf80) at ARMInstPrinter.cpp:182
#7  0x000000010003cbff in PrintInsts (DisAsm=@0x10200f4e0, Printer=@0x1020107e0, Bytes=@0x7fff5fbff060, SM=@0x7fff5fbff078) at Disassembler.cpp:65
#8  0x000000010003c8b4 in llvm::Disassembler::disassemble (T=@0x1010c13c0, Triple=@0x1010b6798, Buffer=@0x102010690) at Disassembler.cpp:153
#9  0x000000010004095c in DisassembleInput (ProgName=0x7fff5fbff3f0 "/Volumes/data/llvm/git/trunk/Debug/bin/llvm-mc") at llvm-mc.cpp:347
#10 0x000000010003eefb in main (argc=4, argv=0x7fff5fbff298) at llvm-mc.cpp:374
(gdb) q
The program is running.  Exit anyway? (y or n) y
[13:36:26] johnny:/Volumes/data/llvm/git/trunk (local-trunk) $ 

llvm-svn: 101053
2010-04-12 18:46:53 +00:00
Benjamin Kramer
0230783438 unXFAIL, arm disassembler was reenabled.
llvm-svn: 100692
2010-04-07 21:19:41 +00:00
Evan Cheng
dbf0c22d5b Reverting 100265 to try to get buildbots green again. Lots of self-hosting buildbots started complaining since this commit. Also xfail ARM disassembly tests.
llvm-svn: 100378
2010-04-05 01:04:27 +00:00
Johnny Chen
6d9cbe7270 Second try of initial ARM/Thumb disassembler check-in. It consists of a tablgen
backend (ARMDecoderEmitter) which emits the decoder functions for ARM and Thumb,
and the disassembler core which invokes the decoder function and builds up the
MCInst based on the decoded Opcode.

Reviewed by Chris Latter and Bob Wilson.

llvm-svn: 100233
2010-04-02 22:27:38 +00:00
Daniel Dunbar
f2c7999cd8 MC/Mach-O/x86_64: Support @GOTPCREL on symbols, even for non-PCrel relocations!
llvm-svn: 99853
2010-03-29 23:56:40 +00:00
Bob Wilson
04e9ff15cb Reapply Kevin's change 94440, now that Chris has fixed the limitation on
opcode values fitting in one byte (svn r99494).

llvm-svn: 99514
2010-03-25 16:36:14 +00:00
Daniel Dunbar
cfa1820a7e MC: Fix refacto in MCExpr evaluation, I mistakenly replaced a fragment address with a symbol address.
- This fixes the integrated-as nightly test regressions.

llvm-svn: 99466
2010-03-25 01:03:17 +00:00
Bob Wilson
d5673d9f1f Speculatively revert this to see if it fixes buildbot failures.
--- Reverse-merging r99440 into '.':
U    test/MC/AsmParser/X86/x86_32-bit_cat.s
U    test/MC/AsmParser/X86/x86_32-encoding.s
U    include/llvm/IntrinsicsX86.td
U    include/llvm/CodeGen/SelectionDAGNodes.h
U    lib/Target/X86/X86InstrSSE.td
U    lib/Target/X86/X86ISelLowering.h

llvm-svn: 99450
2010-03-24 23:26:29 +00:00
Kevin Enderby
9cab7fdb12 Added the Advanced Encryption Standard (AES) Instructions.
llvm-svn: 99440
2010-03-24 22:33:33 +00:00