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2494 Commits

Author SHA1 Message Date
Chad Rosier
fa78ec1a3e Fixed regression due to commit 131709, which disables vararg tail call optimizations on Win64 
llvm-svn: 131740
 2011-05-20 17:49:39 +00:00
Benjamin Kramer
83096d1db1 Rename the "sandybridge" subtarget to "corei7-avx", for GCC compatibility. 
llvm-svn: 131730
 2011-05-20 15:11:26 +00:00
Cameron Zwarich
a487989a73 Fix PR9960 by teaching SimpleRegisterCoalescing::AdjustCopiesBackFrom() to preserve 
the phikill flag.

llvm-svn: 131717
 2011-05-20 03:54:04 +00:00
Chad Rosier
a5f0bb3719 Don't attempt to tail call optimize for Win64. 
llvm-svn: 131709
 2011-05-20 00:59:28 +00:00
Evan Cheng
a3f5204c82 Revert r131664 and fix it in instcombine instead. rdar://9467055 
llvm-svn: 131708
 2011-05-20 00:54:37 +00:00
Eli Friedman
ecdbb58b95 Add fast-isel support for zeroext and signext ret instructions on x86. 
llvm-svn: 131689
 2011-05-19 22:16:13 +00:00
Eric Christopher
74a9e350d2 Oddly people want to use the 'r' constraint for fp constants on x86. 
Fixes rdar://9218925
Fixes PR9601

llvm-svn: 131682
 2011-05-19 21:33:47 +00:00
Eli Friedman
97fda21a43 Fix up this test to use explicit triples (Win64 passes a different number of arguments in registers). 
llvm-svn: 131676
 2011-05-19 21:13:08 +00:00
Evan Cheng
efcc06b08f crc32 with 64-bit output zeros upper 32-bits. rdar://9467055 
llvm-svn: 131664
 2011-05-19 18:57:12 +00:00
Stuart Hastings
b524e73afc Move test to Transforms/InstCombine. 
llvm-svn: 131634
 2011-05-19 05:53:22 +00:00
Chad Rosier
be943c5d9a Enables vararg functions that pass all arguments via registers to be optimized into tail-calls when possible. 
llvm-svn: 131560
 2011-05-18 19:59:50 +00:00
Stuart Hastings
c77046f8d7 An imminent fix to the x86_64 byval logic will expose a flaw in the 
x86_64 sibcall logic.  I've filed PR9943 for the sibcall problem, and
this patch alters the testcase to work around the flaw.  When PR9943
is fixed, this patch should be reverted.

llvm-svn: 131557
 2011-05-18 19:19:17 +00:00
Eli Friedman
0703b8a293 Force a triple on a couple of tests; we don't support fast-isel of ret on Win64. 
llvm-svn: 131540
 2011-05-18 17:16:37 +00:00
Stuart Hastings
03a1927217 Merge pmovzx test case into existing file. 
llvm-svn: 131539
 2011-05-18 17:02:04 +00:00
Eli Friedman
97233814a0 Make some of the fast-isel tests actually test fast-isel (and fix test failures). 
llvm-svn: 131510
 2011-05-18 00:00:10 +00:00
Stuart Hastings
719cee1aa8 X86 pmovsx/pmovzx ignore the upper half of their inputs. 
rdar://problem/6945110

llvm-svn: 131493
 2011-05-17 22:13:31 +00:00
Galina Kistanova
96a3ce9a6f Move test for appropriate directory. 
llvm-svn: 131477
 2011-05-17 19:06:43 +00:00
Eli Friedman
ba315a4fcc Add x86 fast-isel for calls returning first-class aggregates. rdar://9435872. 
This is r131438 with a couple small fixes.

llvm-svn: 131474
 2011-05-17 18:29:03 +00:00
Eli Friedman
3aa2fe389f Back out r131444 and r131438; they're breaking nightly tests. I'll look into 
it more tomorrow.

llvm-svn: 131451
 2011-05-17 02:36:59 +00:00
Eli Friedman
410094a937 Fix test. 
llvm-svn: 131444
 2011-05-17 00:39:14 +00:00
Evan Cheng
24322e6f0a Add target triple so test doesn't fail on Windows machines. 
llvm-svn: 131439
 2011-05-17 00:15:58 +00:00
Eli Friedman
8c4de16d2b Add x86 fast-isel for calls returning first-class aggregates. rdar://9435872. 
llvm-svn: 131438
 2011-05-17 00:13:47 +00:00
Jakob Stoklund Olesen
16f11212fc Teach LiveInterval::isZeroLength about null SlotIndexes. 
When instructions are deleted, they leave tombstone SlotIndex entries.
The isZeroLength method should ignore these null indexes.

This causes RABasic to sometimes spill a callee-saved register in the
abi-isel.ll test, so don't run that test with -regalloc=basic.  Prioritizing
register allocation according to spill weight can cause more registers to be
used.

llvm-svn: 131436
 2011-05-16 23:50:05 +00:00
Eli Friedman
23e7691f59 Remove dead code. Fix associated test to use FileCheck. 
llvm-svn: 131424
 2011-05-16 21:28:22 +00:00
Eli Friedman
cb60e2293f Make fast-isel work correctly s/uadd.with.overflow intrinsics. 
llvm-svn: 131420
 2011-05-16 21:06:17 +00:00
Eli Friedman
5f1b7e4153 Basic fast-isel of extractvalue. Not too helpful on its own, given the IR clang generates for cases like this, but it should become more useful soon. 
llvm-svn: 131417
 2011-05-16 20:27:46 +00:00
Rafael Espindola
98372d430c Don't produce a vmovntdq if we don't have AVX support. 
llvm-svn: 131330
 2011-05-14 00:30:01 +00:00
Evan Cheng
f3eb9e3262 Re-enable branchfolding common code hoisting optimization. Fixed a liveness test bug and also taught it to update liveins. 
llvm-svn: 131241
 2011-05-12 20:30:01 +00:00
Devang Patel
344808fbe5 Identify end of prologue (and beginning of function body) using DW_LNS_set_prologue_end line table opcode. 
llvm-svn: 131194
 2011-05-11 19:22:19 +00:00
Nadav Rotem
57dd315a3b Fixes a bug in the DAGCombiner. LoadSDNodes have two values (data, chain). 
If there is a store after the load node, then there is a chain, which means
that there is another user. Thus, asking hasOneUser would fail. Instead we
ask hasNUsesOfValue on the 'data' value.

llvm-svn: 131183
 2011-05-11 14:40:50 +00:00
Nadav Rotem
2a654a69ed Add custom lowering of X86 vector SRA/SRL/SHL when the shift amount is a splat vector. 
llvm-svn: 131179
 2011-05-11 08:12:09 +00:00
Rafael Espindola
dfc30289f1 Revert 131172 as it is causing clang to miscompile itself. I will try 
to provide a reduced testcase.

llvm-svn: 131176
 2011-05-11 03:27:17 +00:00
Evan Cheng
271e0ebf0a Add a late optimization to BranchFolding that hoist common instruction sequences 
at the start of basic blocks to their common predecessor. It's actually quite
common (e.g. about 50 times in JM/lencod) and has shown to be a nice code size
benefit. e.g.

        pushq   %rax
        testl   %edi, %edi
        jne     LBB0_2
## BB#1:
        xorb    %al, %al
        popq    %rdx
        ret
LBB0_2:
        xorb    %al, %al
        callq   _foo
        popq    %rdx
        ret

=>

        pushq   %rax
        xorb    %al, %al
        testl   %edi, %edi
        je      LBB0_2
## BB#1:
        callq   _foo
LBB0_2:
        popq    %rdx
        ret

rdar://9145558

llvm-svn: 131172
 2011-05-11 01:03:01 +00:00
Benjamin Kramer
ba7c9948e8 X86: Add a bunch of peeps for add and sub of SETB. 
"b + ((a < b) ? 1 : 0)" compiles into
	cmpl	%esi, %edi
	adcl	$0, %esi
instead of
	cmpl	%esi, %edi
	sbbl	%eax, %eax
	andl	$1, %eax
	addl	%esi, %eax

This saves a register, a false dependency on %eax
(Intel's CPUs still don't ignore it) and it's shorter.

llvm-svn: 131070
 2011-05-08 18:36:07 +00:00
Jakob Stoklund Olesen
bb09bbccb8 Emit a proper error message when register allocators run out of registers. 
This can't be just an assertion, users can always write impossible inline
assembly. Such an assembly statement should be included in the error message.

llvm-svn: 131024
 2011-05-06 21:58:30 +00:00
Eli Friedman
f7b4d848ae Re-revert r130877; it's apparently causing a regression on 197.parser, 
possibly related to cbnz formation.

llvm-svn: 130977
 2011-05-06 05:23:07 +00:00
Rafael Espindola
ab39b8319b Don't produce a __debug_frame. 
I tested both gdb on a bootstrapped clang and and the gdb testsuite on OS X (snow leopard)
and both are happy using __eh_frame.

llvm-svn: 130937
 2011-05-05 18:43:39 +00:00
Eli Friedman
09ec41fcde Avoid extra vreg copies for arguments passed in registers. Specifically, this can make MachineCSE more effective in some cases (especially in small functions). PR8361 / part of rdar://problem/8259436 . 
llvm-svn: 130928
 2011-05-05 16:53:34 +00:00
Jakob Stoklund Olesen
f27731bf40 Prepare remaining tests for -join-physreg going away. 
llvm-svn: 130893
 2011-05-04 23:54:59 +00:00
Jakob Stoklund Olesen
e964058440 Fix a batch of x86 tests to be coalescer independent. 
Most of these tests require a single mov instruction that can come either before
or after a 2-addr instruction. -join-physregs changes the behavior, but the
results are equivalent.

llvm-svn: 130891
 2011-05-04 23:54:51 +00:00
Eli Friedman
5b78092546 Re-commit r130862 with a minor change to avoid an iterator running off the edge in some cases. 
Original message:

Teach MachineCSE how to do simple cross-block CSE involving physregs.  This allows, for example, eliminating duplicate cmpl's on x86. Part of rdar://problem/8259436 .

llvm-svn: 130877
 2011-05-04 22:10:36 +00:00
Eli Friedman
cc74616be6 Back out r130862; it appears to be breaking bootstrap. 
llvm-svn: 130867
 2011-05-04 20:48:42 +00:00
Eli Friedman
e086e00208 Teach MachineCSE how to do simple cross-block CSE involving physregs. This allows, for example, eliminating duplicate cmpl's on x86. Part of rdar://problem/8259436 . 
llvm-svn: 130862
 2011-05-04 19:54:24 +00:00
Jakob Stoklund Olesen
4d020cd8e5 Don't depend on the physreg coalescing order. 
llvm-svn: 130818
 2011-05-04 01:01:47 +00:00
Bill Wendling
67f5e8f0a7 Replace the "movnt" intrinsics with a native store + nontemporal metadata bit. 
<rdar://problem/8460511>

llvm-svn: 130791
 2011-05-03 21:11:17 +00:00
Rafael Espindola
d49e7769a7 Add r130623 back now that ELF has been fixed to work with -fno-dwarf2-cfi-asm. 
llvm-svn: 130658
 2011-05-01 15:44:13 +00:00
Rafael Espindola
eb5d0cb4f4 GCC uses a different encoding of pointers in the FDE when using 
-fno-dwarf2-cfi-asm. Implement the same behavior.

llvm-svn: 130637
 2011-05-01 04:49:54 +00:00
Rafael Espindola
886aa563be Revert the previous patch while I figure out how to make llvm-gcc 
less agressive about disabling cfi on linux :-(

llvm-svn: 130626
 2011-04-30 23:03:44 +00:00
Rafael Espindola
9455887b10 Enable CFI on OS X. 
Currently the output should be almost identical to the one produced by CodeGen
to make the transition easier.

The only two differences I know of are:

* Some files get an extra advance loc of size 0. This will be fixed when
relaxations are enabled.
* The optimization of declaring an EH symbol as an external variable is not
implemented. This is a subset of adding the nounwind attribute, so we if really
this at -O0 we should probably do it at the IL level.

llvm-svn: 130623
 2011-04-30 22:29:54 +00:00
Jakob Stoklund Olesen
c140b5ac84 Allow folded spills in test. 
llvm-svn: 130599
 2011-04-30 08:00:50 +00:00