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Commit Graph

133303 Commits

Author SHA1 Message Date
Craig Topper
fb3bf38856 [X86] Pre-allocate some of the shuffle mask SmallVectors in the auto upgrade code instead of calling push_back in a loop. This removes the need to check if the vector needs to grow on each iteration.
llvm-svn: 272501
2016-06-12 04:48:00 +00:00
Craig Topper
b01b227720 [AVX512] Remove the masked palignr intrinsics that I forgot to remove when I added auto-upgrade code to turn them into shufflevectors and selects.
llvm-svn: 272497
2016-06-12 04:14:13 +00:00
Craig Topper
9c5cbc87df [X86] Greatly simplify the llvm.x86.avx.vpermil.* auto-upgrade code. We can fully derive everything using types of the intrinsic arguments rather than writing separate loops for each intrinsic. NFC
llvm-svn: 272496
2016-06-12 03:10:47 +00:00
Eli Friedman
97af9f3308 [MergedLoadStoreMotion] Use correct helper for load hoist safety.
It isn't legal to hoist a load past a call which might not return;
even if it doesn't throw, it could, for example, call exit().

Fixes http://llvm.org/PR27953.

llvm-svn: 272495
2016-06-12 02:11:20 +00:00
Craig Topper
aee1d0d19d [X86] Move tests for llvm.x86.avx.vpermil.* intrinsics to a -upgrade test since they are autoupgraded to shufflevector.
llvm-svn: 272494
2016-06-12 01:41:06 +00:00
Craig Topper
3ff68142de [X86,IR] Make use of the CreateShuffleVector form that takes an ArrayRef<uint32_t> to avoid the need to manually create a bunch of Constants and a ConstantVector. NFC
llvm-svn: 272493
2016-06-12 01:05:59 +00:00
Craig Topper
14d655be9c [IR] Require ArrayRef of 'uint32_t' instead of 'int' for the mask argument for one of the signatures of CreateShuffleVector. This better emphasises that you can't use it for the -1 as undef behavior.
llvm-svn: 272491
2016-06-12 00:41:19 +00:00
Eli Friedman
a67cf70e74 [LICM] Make isGuaranteedToExecute more accurate.
Summary:
Make isGuaranteedToExecute use the
isGuaranteedToTransferExecutionToSuccessor helper, and make that helper
a bit more accurate.

There's a potential performance impact here from assuming that arbitrary
calls might not return. This probably has little impact on loads and
stores to a pointer because most things alias analysis can reason about
are dereferenceable anyway. The other impacts, like less aggressive
hoisting of sdiv by a variable and less aggressive hoisting around
volatile memory operations, are unlikely to matter for real code.

This also impacts SCEV, which uses the same helper.  It's a minor
improvement there because we can tell that, for example, memcpy always
returns normally. Strictly speaking, it's also introducing
a bug, but it's not any worse than everywhere else we assume readonly
functions terminate.

Fixes http://llvm.org/PR27857.

Reviewers: hfinkel, reames, chandlerc, sanjoy

Subscribers: broune, llvm-commits

Differential Revision: http://reviews.llvm.org/D21167

llvm-svn: 272489
2016-06-11 21:48:25 +00:00
Simon Pilgrim
08b5ad90a3 [X86] Updated test checks script to generalise LCPI symbol refs
The script now replace '.LCPI888_8' style asm symbols with the {{\.LCPI.*}} re pattern - this helps stop hardcoded symbols in 32-bit x86 tests changing with every edit of the file

Refreshed some tests to demonstrate the new check

llvm-svn: 272488
2016-06-11 20:39:21 +00:00
Simon Pilgrim
2b98b76820 [CostModel][X86][SSE] Updated costs for vector BITREVERSE ops on SSSE3+ targets
To account for the fast PSHUFB implementation now available

llvm-svn: 272484
2016-06-11 19:23:02 +00:00
Xinliang David Li
37b3e3fa49 [MBP] Code cleanup /NFC
This is one of the patches to clean up the code so that
it is in a better form to make future enhancements easier.

In htis patch, the logic to collect viable successors are
extrated as a helper to unclutter the caller which gets very
large recenty. Also cleaned up BP adjustment code.
 

llvm-svn: 272482
2016-06-11 18:35:40 +00:00
Vassil Vassilev
1872258b31 [CMake] Allow LLVM to be embedded and built in a subfolder as part of another project.
Patch by Bertrand Bellenot!

Reviewed by Chris Bieneman and me.

llvm-svn: 272481
2016-06-11 17:20:53 +00:00
Vikram TV
b4ecab0885 Delay dominator updation while cloning loop.
Summary:
Dominator updation fails for a loop inserted with a new basicblock.

A block required by DT to set the IDom might not have been cloned yet. This is because there is no predefined ordering of loop blocks (except for the header block which should be the first block in the list).

The patch first creates DT nodes for the cloned blocks and then separately updates the DT in a follow-on loop.

Reviewers: anemet, dberlin

Subscribers: dberlin, llvm-commits

Differential Revision: http://reviews.llvm.org/D20899

llvm-svn: 272479
2016-06-11 16:41:10 +00:00
Simon Pilgrim
b7726309b9 [X86][SSSE3] Added PSHUFB LUT implementation of BITREVERSE
PSHUFB can speed up BITREVERSE of byte vectors by performing LUT on the low/high nibbles separately and ORing the results. Wider integer vector types are already BSWAP'd beforehand so also make use of this approach.

llvm-svn: 272477
2016-06-11 15:44:13 +00:00
Simon Pilgrim
5b4791fb00 Strip trailing whitespace. NFCI.
llvm-svn: 272476
2016-06-11 14:34:10 +00:00
Craig Topper
fb75f9757d [AVX512] Re-generate v8i64 shuffle test now that we use pshufd for some cases.
llvm-svn: 272474
2016-06-11 13:57:08 +00:00
Craig Topper
78932cddbe [AVX512] Lower v8i64 and v16i32 to pshufd when possible.
llvm-svn: 272473
2016-06-11 13:43:21 +00:00
Craig Topper
24d1cbdf99 [X86] Remove GCC builtin name from some intrinsics that are no longer used by clang. A future commit can remove the intrinsics entirely.
Some of these have been unused for a long time.

llvm-svn: 272472
2016-06-11 13:43:18 +00:00
Simon Pilgrim
c0eeddf671 [X86][SSE] Added PSLLDQ/PSRLDQ as a target shuffle type
Ensure that PALIGNR/PSLLDQ/PSRLDQ are byte vectors so that they can be correctly decoded for target shuffle combining

llvm-svn: 272471
2016-06-11 13:38:28 +00:00
Simon Pilgrim
f29552f8ec [X86][AVX2] Added PSLLDQ/PSRLDQ shuffle combining tests
llvm-svn: 272469
2016-06-11 13:18:21 +00:00
Simon Pilgrim
53b27def76 [X86][SSE] Use vXi8 return type for PSLLDQ/PSRLDQ instructions
These are byte shift instructions and it will make shuffle combining a lot more straightforward if we can assume a vXi8 vector of bytes so decoded shuffle masks match the return type's number of elements

llvm-svn: 272468
2016-06-11 12:54:37 +00:00
Simon Pilgrim
7f1a8ecbfa [X86][AVX512] Tidied up VSHUFF32x4/VSHUFF64x2/VSHUFI32x4/VSHUFI64x2 comment generation
Now matches other shuffles

llvm-svn: 272464
2016-06-11 11:18:38 +00:00
Chandler Carruth
1b236505ea Try a bit harder to remove the signed and unsigned comparison warning.
Hopefully this time it actually works and stays away.

llvm-svn: 272463
2016-06-11 09:13:00 +00:00
Chandler Carruth
3c87e69ef7 Use a two-level cast through an intptr_t, and make them C-style casts.
This shouldn't have any functional difference, but it appears to be the
pattern used for other methods on DynamicLibrary, and it should avoid
the -Wpedantic warning on one of the build bots about the direct
reinterpret_cast.

llvm-svn: 272461
2016-06-11 08:19:59 +00:00
Chandler Carruth
d641f0d19d Add a using declaration so that the overrides don't hide some of the
base class methods.

This was caught by GCC's -Woverloaded-virtual, not sure why it wasn't
caught by Clang's. =/

llvm-svn: 272460
2016-06-11 08:12:17 +00:00
Chandler Carruth
c5dd6b188a Compare to an unsigned literal to avoid a -Wsign-compare warning.
llvm-svn: 272459
2016-06-11 08:02:01 +00:00
Chandler Carruth
cf33f93aeb Use const_cast to cast away constness. This silences a warning.
llvm-svn: 272458
2016-06-11 08:01:57 +00:00
NAKAMURA Takumi
62479a2a36 DebugInfoPDBTests:MappedBlockStreamTest.TestWriteThenRead: Avoid assigning temporary object to ArrayRef.
llvm-svn: 272457
2016-06-11 06:37:28 +00:00
Lang Hames
a4ac14ea38 [MCJIT] Update MCJIT and get the fibonacci example working again.
MCJIT will now set the DataLayout on a module when it is added to the JIT,
rather than waiting until it is codegen'd, and the runFunction method will
finalize the module containing the function to be run before running it.

The fibonacci example has been updated to include and link against MCJIT.

llvm-svn: 272455
2016-06-11 05:47:04 +00:00
Craig Topper
9a64a1c8f7 [AVX512] Add support for lowering v32i16 shuffles with repeated lanes. This allows us to create 512-bit PSHUFLW/PSHUFHW.
llvm-svn: 272450
2016-06-11 03:27:42 +00:00
Craig Topper
ead4a97985 [AVX512] No need to check for BWI being enabled before lowering v32i16 and v64i8 shuffles. If we get this far the types are already legal which means BWI must be enabled.
llvm-svn: 272449
2016-06-11 03:27:37 +00:00
Matthias Braun
fe41256f69 LiveIntervalAnalysis: findLastUseBefore() must ignore undef uses.
undef uses are no real uses of a register and must be ignored by
findLastUseBefore() so that handleMove() does not produce invalid live
intervals in some cases.

This fixed http://llvm.org/PR28083

llvm-svn: 272446
2016-06-11 00:31:28 +00:00
Qin Zhao
e53140dc9d [esan|cfrag] Handle complex GEP instr in the cfrag tool
Summary:
Iterates all (except the first and the last) operands within each GEP
instruction for instrumentation.

Adds test struct_field_gep.ll.

Reviewers: aizatsky

Subscribers: vitalybuka, zhaoqin, kcc, eugenis, bruening, llvm-commits

Differential Revision: http://reviews.llvm.org/D21242

llvm-svn: 272442
2016-06-10 22:28:55 +00:00
Zachary Turner
3ce2291b08 Try again to fix this endianness issue.
llvm-svn: 272440
2016-06-10 22:12:18 +00:00
Michael Zolotukhin
116f2abb18 Don't try to rotate a loop more than once - we never do this anyway.
Summary:
I can't find a case where we can rotate a loop more than once, and it looks
like we never do this. To rotate a loop following conditions should be met:
1) its header should be exiting
2) its latch shouldn't be exiting

But after the first rotation the header becomes the new latch, so this
condition can never be true any longer.

Tested on with an assert on LNT testsuite and make check.

Reviewers: hfinkel, sanjoy

Subscribers: sebpop, sanjoy, llvm-commits, mzolotukhin

Differential Revision: http://reviews.llvm.org/D20181

llvm-svn: 272439
2016-06-10 22:03:56 +00:00
Zachary Turner
d2ab2f7431 [pdb] Fix issues with pdb writing.
This fixes an alignment issue by forcing all cached allocations
to be 8 byte aligned, and also fixes an issue arising on big
endian systems by writing ulittle32_t's instead of uint32_t's
in the test.

llvm-svn: 272437
2016-06-10 21:47:26 +00:00
Sebastian Pop
b4051eb864 MemorySSA: fix memory access local dominance function for live on entry
A memory access defined on function entry cannot be locally dominated by another memory access.
The patch was split from http://reviews.llvm.org/D19338 which exposes the problem.

Differential Revision: http://reviews.llvm.org/D21039

llvm-svn: 272436
2016-06-10 21:36:41 +00:00
Sanjoy Das
858bed9b6b [STLExtras] Introduce and use llvm::count_if; NFC
(This is split out from was D21115)

llvm-svn: 272435
2016-06-10 21:18:39 +00:00
Quentin Colombet
cd7dd65c54 [IRTranslator] Support the translation of or.
Now or instructions get translated into G_OR.

llvm-svn: 272433
2016-06-10 20:50:35 +00:00
Quentin Colombet
c115d30d00 [IRTranslator] Rework the comments for the methods to translate.
NFC.

llvm-svn: 272432
2016-06-10 20:50:33 +00:00
Quentin Colombet
b2b5df0dde [IRTranslator] Refactor to expose a translateBinaryOp method.
This method will be used for every binary operation.

NFC.

llvm-svn: 272431
2016-06-10 20:50:18 +00:00
Chad Rosier
bfe945ef74 [AArch64] Move comments closer to relevant check. NFC.
llvm-svn: 272430
2016-06-10 20:49:18 +00:00
Chad Rosier
35d6f25123 [AArch64] Refactor a check earlier. NFC.
llvm-svn: 272429
2016-06-10 20:47:14 +00:00
Sanjay Patel
c800b6d013 [x86] enable bitcasted fabs/fneg transforms
The vector cases don't change because we already have folds in X86ISelLowering
to look through and remove bitcasts.

llvm-svn: 272427
2016-06-10 20:33:50 +00:00
Etienne Bergeron
5f9149275d [CodeGen] Fix PrologEpilogInserter to avoid duplicate allocation of SEH structs
Summary:
When stack-protection is activated and WinEH exceptions is used, 
the EHRegNode (exception handling registration) is allocated twice on the stack.

This was not breaking anything except loosing space on the stack.

```
D:\src\llvm\examples>llc exc2.ll  -debug-only=pei
alloc FI(0) at SP[-24]
alloc FI(1) at SP[-48]   <<-- Allocated
alloc FI(1) at SP[-72]   <<-- Allocated twice!?
alloc FI(2) at SP[-76]
alloc FI(4) at SP[-80]
alloc FI(3) at SP[-84]
```

Reviewers: rnk, majnemer

Subscribers: chrisha, llvm-commits

Differential Revision: http://reviews.llvm.org/D21188

llvm-svn: 272426
2016-06-10 20:24:38 +00:00
Nico Weber
cedbf019a4 Remove a few gendered pronouns.
llvm-svn: 272422
2016-06-10 20:06:03 +00:00
Evgeniy Stepanov
3a69e668e5 Disable MSan-hostile loop unswitching.
Loop unswitching may cause MSan false positive when the unswitch
condition is not guaranteed to execute.

This is very similar to ASan and TSan special case in
llvm::isSafeToSpeculativelyExecute (they don't like speculative loads
and stores), but for branch instructions.

This is a workaround for PR28054.

llvm-svn: 272421
2016-06-10 20:03:20 +00:00
Evgeniy Stepanov
212faec920 Move isGuaranteedToExecute out of LICM.
Also rename LICMSafetyInfo to LoopSafetyInfo.
Both will be used in LoopUnswitch in a separate change.

llvm-svn: 272420
2016-06-10 20:03:17 +00:00
Zhan Jun Liau
4faf864f2c [SystemZ] Support Compare and Traps
Support and generate Compare and Traps like CRT, CIT, etc.

Support Trap as legal DAG opcodes and generate "j .+2" for them by default.
Add support for Conditional Traps and use the If Converter to convert them into
the corresponding compare and trap opcodes.

Differential Revision: http://reviews.llvm.org/D21155

llvm-svn: 272419
2016-06-10 19:58:10 +00:00
Tom Stellard
b52bf01ef4 AMDGPU/SI: Don't use fixup_si_rodata for scratch rsrc relocations
Summary:
We need to set the fixup type to FK_Data_4 for the
SCRATCH_RSRC_DWORD[01] symbols, since these require absolute
relocations, and fixup_si_rodata is for relative relocations.

Reviewers: arsenm, kzhuravl

Subscribers: arsenm, kzhuravl, llvm-commits

Differential Revision: http://reviews.llvm.org/D21153

llvm-svn: 272417
2016-06-10 19:26:38 +00:00