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Commit Graph

146193 Commits

Author SHA1 Message Date
Volkan Keles
f603fe7e92 GlobalISel: Translate ConstantDataVector
Reviewers: qcolombet, aditya_nandakumar, dsanders, t.p.northover, javed.absar, ab

Reviewed By: qcolombet, dsanders, ab

Subscribers: dberris, rovka, llvm-commits, kristof.beyls

Differential Revision: https://reviews.llvm.org/D30216

llvm-svn: 297670
2017-03-13 21:36:19 +00:00
Juergen Ributzka
036b9677ed [Support] Test directory iterators and recursive directory iterators with broken symlinks.
This commit adds a unit test to the file system tests to verify the behavior of
the directory iterator and recursive directory iterator with broken symlinks.

This test is Unix only.

llvm-svn: 297669
2017-03-13 21:34:07 +00:00
Tim Northover
70406195b7 Revert "GlobalISel: move vector extract/insert inside generic opcode region."
I was writing against an earlier branch and Volkan had already fixed this.

llvm-svn: 297668
2017-03-13 21:25:10 +00:00
Simon Pilgrim
57d2266552 [X86][MMX] Fix folding of shift value loads to cover whole 64-bits
rL230225 made the assumption that only the lower 32-bits of an MMX register load is used as a shift value, when in fact the whole 64-bits are reloaded and treated as a i64 to determine the shift value.

This patch reverts rL230225 to ensure that the whole 64-bits of memory are folded and ensures that the upper 32-bit are zero'd for cases where the shift value has come from a scalar source.

Found during fuzz testing.

Differential Revision: https://reviews.llvm.org/D30833

llvm-svn: 297667
2017-03-13 21:23:29 +00:00
Tim Northover
96a7930f52 GlobalISel: move vector extract/insert inside generic opcode region.
Otherwise they won't be legalized or selected, causing instruction selection to
fail horribly.

llvm-svn: 297666
2017-03-13 21:18:59 +00:00
Andrew Kaylor
5b14a90ddd Revert r295004 (Add MXCSR) due to errors reported by MachineVerifier
I am leaving the code in clang which filters mxcsr from the clobber list because that is still technically correct and will be useful again when the MXCSR register is reintroduced.

llvm-svn: 297664
2017-03-13 20:35:10 +00:00
Volkan Keles
55c5038c53 [GlobalISel] Update PRE_ISEL_GENERIC_OPCODE_END marker
llvm-svn: 297663
2017-03-13 20:31:45 +00:00
Matt Arsenault
7b61ea7700 AMDGPU: Re-use TM.getNullPointerValue
llvm-svn: 297662
2017-03-13 20:18:14 +00:00
Rafael Espindola
4358d27b64 Bring back r297624.
The issues was just a missing REQUIRES in the test.

llvm-svn: 297661
2017-03-13 20:00:25 +00:00
Sanjay Patel
f688b567a8 [SimplifyCFG] move tests for PR31028 from CGP
Hopefully, this will make sense with a forthcoming patch. If not, we can move these back.

llvm-svn: 297660
2017-03-13 19:59:14 +00:00
Matt Arsenault
78e7d66a36 AMDGPU: Treat 0 as private null pointer in addrspacecast lowering
llvm-svn: 297658
2017-03-13 19:47:31 +00:00
Rafael Espindola
b89a1dbe86 Revert "Fix crash when multiple raw_fd_ostreams to stdout are created."
This reverts commit r297624.
It was failing on the bots.

llvm-svn: 297657
2017-03-13 19:38:32 +00:00
Daniel Berlin
58f8a88d1e Fix some indenting and line-wrapping issues identified in ProgrammersManual. Make description of debugCounters a little clearer
llvm-svn: 297656
2017-03-13 19:09:23 +00:00
Jessica Paquette
ad5647725b [Outliner] Add tail call support
This commit adds tail call support to the MachineOutliner pass. This allows
the outliner to insert jumps rather than calls in areas where tail calling is
possible. Outlined tail calls include the return or terminator of the basic
block being outlined from.

Tail call support allows the outliner to take returns and terminators into
consideration while finding candidates to outline. It also allows the outliner
to save more instructions. For example, in the X86-64 outliner, a tail called
outlined function saves one instruction since no return has to be inserted.

llvm-svn: 297653
2017-03-13 18:39:33 +00:00
Craig Topper
c2088276f3 [X86] Lower AVX2 gather intrinsics similar to AVX-512. Apply the same input source optimizations to break execution dependencies.
For AVX-512 we force the input to zero if the input is undef or the mask is all ones to break an execution dependency. This patch brings the same behavior to AVX2.

llvm-svn: 297652
2017-03-13 18:34:46 +00:00
Craig Topper
3cb591fd44 [AVX-512] If gather mask is all ones, force the input to a zero vector.
We were already forcing undef inputs to become a zero vector, this now catches an all ones mask too.

Ideally we'd use undef and let execution dep fix handle picking the best register/clearance for the undef, but I don't think it can handle the early clobber today.

llvm-svn: 297651
2017-03-13 18:17:46 +00:00
Matt Arsenault
9763d98635 AMDGPU: Fold icmp/fcmp into icmp intrinsic
The typical use is a library vote function which
compares to 0. Fold the user condition into the intrinsic.

llvm-svn: 297650
2017-03-13 18:14:02 +00:00
Jonas Devlieghere
9840ae61ae [Linker] Provide callback for internalization
Differential Revision: https://reviews.llvm.org/D30738

llvm-svn: 297649
2017-03-13 18:08:11 +00:00
Craig Topper
d35723bd11 [SelectionDAG] Enhance SDTCisSameNumEltsAs to work with scalar types and use it on extend/trunc/round operations.
Currently we don't enforce that ISD::ANY_EXTEND, ZERO_EXTEND, SIGN_EXTEND, TRUNC, FP_ROUND, FP_EXTEND have the same number of elements(including scalar) between their input and output. Though we have them documented as such. Up until a few months ago x86 created nodes that violated this rule. That's all been fixed now, and we should enforce the rule going forward.

In order to do this we need to allow SDTCisSameNumEltsAs to support scalar types and not enforce being a vector. If one type is scalar we will force the other type to also be scalar.

Differential Revision: https://reviews.llvm.org/D30878

llvm-svn: 297648
2017-03-13 17:37:14 +00:00
Zachary Turner
53b5566696 Add missing include on <limits>.
llvm-svn: 297646
2017-03-13 17:25:47 +00:00
Adrian Prantl
3abadd0c86 API gardening: Rename FindAllocaDbgValue to findDbgValue (NFC)
and use have it use SmallVectorImpl.

There is nothing specific about allocas in this function.

llvm-svn: 297643
2017-03-13 17:20:47 +00:00
Zachary Turner
3f1f055e62 Use numeric_limits<size_t>::max() instead of size_t(-1).
llvm-svn: 297641
2017-03-13 17:12:37 +00:00
Zachary Turner
2810a164dd Fix a warning due to signed/unsigned comparison.
llvm-svn: 297639
2017-03-13 16:41:49 +00:00
Zachary Turner
84ce56f415 Use the new member accessors of llvm::enumerate.
The value_type is no longer a struct, it's a class whose
members you have to access via a method.

llvm-svn: 297635
2017-03-13 16:32:08 +00:00
Zachary Turner
bb6c1699b6 [ADT] Improve the genericity of llvm::enumerate().
There were some issues in the implementation of enumerate()
preventing it from being used in various contexts.  These were
all related to the fact that it did not supporter llvm's
iterator_facade_base class.  So this patch adds support for that
and additionally exposes a new helper method to_vector() that
will evaluate an entire range and store the results in a
vector.

Differential Revision: https://reviews.llvm.org/D30853

llvm-svn: 297633
2017-03-13 16:24:10 +00:00
Zachary Turner
ff074a8ea9 Remove an unused variable.
llvm-svn: 297632
2017-03-13 16:18:08 +00:00
Sanjay Patel
439a24aa49 [CGP] add tests for PR31028; NFC
llvm-svn: 297629
2017-03-13 15:45:37 +00:00
Zachary Turner
7513c7f0d9 [llvm-pdbdump] Add support for dumping symbols from Yaml -> PDB.
Previously we could round-trip type records from PDB -> Yaml ->
PDB, but for symbols we could only go from PDB -> Yaml.  This
completes the round-tripping for symbols as well.

llvm-svn: 297625
2017-03-13 14:57:45 +00:00
Rafael Espindola
644c5436f5 Fix crash when multiple raw_fd_ostreams to stdout are created.
If raw_fd_ostream is constructed with the path of "-", it claims
ownership of the stdout file descriptor. This means that it closes
stdout when it is destroyed. If there are multiple users of
raw_fd_ostream wrapped around stdout, then a crash can occur because
of operations on a closed stream.

An example of this would be running something like "clang -S -o - -MD
-MF - test.cpp". Alternatively, using outs() (which creates a local
version of raw_fd_stream to stdout) anywhere combined with such a
stream usage would cause the crash.

The fix duplicates the stdout file descriptor when used within
raw_fd_ostream, so that only that particular descriptor is closed when
the stream is destroyed.

Patch by James Henderson!

llvm-svn: 297624
2017-03-13 14:45:06 +00:00
Diana Picus
48656d6f1e [ARM] GlobalISel: Support SP in regbankselect
We used to hit an unreachable in getRegBankFromRegClass when dealing with the
stack pointer. This commit adds support for the GPRsp reg class.

llvm-svn: 297621
2017-03-13 14:28:34 +00:00
Aaron Ballman
310244c642 Reverting r297617 because it broke some bots:
http://bb.pgr.jp/builders/cmake-llvm-x86_64-linux/builds/49970

llvm-svn: 297618
2017-03-13 12:24:51 +00:00
Aaron Ballman
6055e8d677 Add support for getting file system permissions and implement sys::fs::permissions to set them.
Patch by James Henderson.

llvm-svn: 297617
2017-03-13 12:17:14 +00:00
Balaram Makam
90de8d3f1a [AArch64] Map Sched Read/Write resources for Falkor.
llvm-svn: 297611
2017-03-13 10:42:17 +00:00
Gil Rapaport
52cac734e2 [LV] Set memcheck metadata also for VF==1
This commit is a follow-up on r297580. It fixes the FIXME added temporarily
by that commit to keep the removal of Unroller's specialized version of
scalarizeInstruction() an NFC. See https://reviews.llvm.org/D30715 for details.

llvm-svn: 297610
2017-03-13 10:23:46 +00:00
Sjoerd Meijer
3015e60ce3 ARMDisassembler: loop over ARM decode tables
Loop over the ARM decode tables; this is a clean-up to reduce some code
duplication.

Differential Revision: https://reviews.llvm.org/D30814

llvm-svn: 297608
2017-03-13 09:41:10 +00:00
Konstantin Zhuravlyov
54c08f6036 AMDGPU/RelocVisitor: Handle R_AMDGPU_ABS64
Test is in the separate patch.

Differential Revision: https://reviews.llvm.org/D30027

llvm-svn: 297604
2017-03-13 06:03:11 +00:00
Craig Topper
58a204a9d1 [AVX-512] Add EVEX2VEX test cases for the cvt instructions fixed in r297599 and r297600.
llvm-svn: 297603
2017-03-13 05:47:56 +00:00
Craig Topper
92fcaeffd1 Revert "[AVX-512] EVEX2VEX, don't reject intrinsic instructions when both have a memory operand. We should just continue to check other operands instead."
This reverts r297596.

There were other issues that were making this not work that have been fixed now. Reverting this results in a more accurate table.

llvm-svn: 297602
2017-03-13 05:34:03 +00:00
Craig Topper
a863935515 [AVX-512] Add VEX_WIG to VEX vcvtsd2ss/vcvtss2sd intrinsic instructions so they can be correctly matched by EVEX2VEX table generation.
llvm-svn: 297601
2017-03-13 05:14:47 +00:00
Craig Topper
4cb53e4ee2 [AVX-512] Use sse_loadf32/f64 for vcvtss2sd and vcvtsd2ss intrinsic patterns.
llvm-svn: 297600
2017-03-13 05:14:44 +00:00
Craig Topper
ed42919a04 [AVX-512] Use sse_load_f64/f32 in VCVTSS2SI/VCVTSD2SI patterns.
llvm-svn: 297599
2017-03-13 03:59:06 +00:00
Craig Topper
b9d0343319 [AVX-512] EVEX2VEX, don't reject intrinsic instructions when both have a memory operand. We should just continue to check other operands instead.
This exposed that we have several intrinsic instructions that have identical TSFlags to other instructions. We should merge their patterns and kill of the duplicate. I'll fix that in a follow up patch.

llvm-svn: 297596
2017-03-13 00:36:49 +00:00
Craig Topper
c53a7e90e4 [X86] Minor formatting tweaks in EVEX to VEX tables. NFC
llvm-svn: 297595
2017-03-13 00:36:46 +00:00
Craig Topper
957db85432 [X86] Remove unused SDTypeProfile. NFC
llvm-svn: 297594
2017-03-12 23:05:03 +00:00
Craig Topper
a33be42ddd [X86] Lower SSE/AVX cmpps/pd intrinsics directly to X86ISD::CMPP SDNodes.
This allows us to remove a duplicate set of patterns.

llvm-svn: 297593
2017-03-12 23:05:00 +00:00
Craig Topper
661eeef675 [AVX-512] Fix the valid immediates for the scatter/gather prefetch intrinsics.
The immediate should be 1 or 2, not 0 or 1. This was found while adding bounds checking to clang. In fact the existing clang builtin test failed if we ran it all the way to assembly.

llvm-svn: 297591
2017-03-12 22:29:12 +00:00
Sanjay Patel
e25ded1888 [x86] don't blindly transform SETB into SBB
I noticed unnecessary 'sbb' instructions in D30472 and while looking at 'ptest' codegen recently. 
This happens because we were transforming any 'setb' - even when we only wanted a single-bit result.

This patch moves those transforms under visitAdd/visitSub, so we we're only creating sbb/adc when it
is a win. I don't know why we need a SETCC_CARRY node type, but I'm not proposing to change that
existing behavior in this patch.

Also, I'm skeptical that sbb/adc are a win for all micro-arches, so I added comments to the test files
where this transform still fires.

The test changes here are all cases where we no longer produce sbb/adc. Avoiding partial register
stalls (generating an xor to clear a register) is not handled in some cases, but that's a separate
issue.

Differential Revision: https://reviews.llvm.org/D30611

llvm-svn: 297586
2017-03-12 18:28:48 +00:00
Anna Thomas
8fabbeb54a [LVI] Add Datalayout to the class LazyValueInfo since all its Impls require it. NFC
llvm-svn: 297583
2017-03-12 14:06:41 +00:00
Azharuddin Mohammed
c515dddbb1 Remove CRC32 instructions from AArch64InstrInfo::hasShiftedReg
Summary:
A53 scheduler causes an assertion failure on all CRC instructions:
include/llvm/CodeGen/MachineInstr.h:280: const llvm::MachineOperand
&llvm::MachineInstr::getOperand(unsigned int) const: Assertion `i <
getNumOperands() && "getOperand() out of range!"' failed.

The case statements corresponding to CRC instructions are incorrect and should
be removed.

Also adding a testcase while on this.

Reviewers: t.p.northover, javed.absar, apazos, rengolin

Reviewed By: rengolin

Subscribers: evandro, aemerson, llvm-commits, rengolin

Differential Revision: https://reviews.llvm.org/D30274

llvm-svn: 297582
2017-03-12 14:02:32 +00:00
Igor Breger
a762b2b26e [X86] Add vector zext tests.
llvm-svn: 297581
2017-03-12 13:20:10 +00:00