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llvm-mirror/test/CodeGen/AArch64/fjcvtzs.mir
2020-07-27 09:17:53 -06:00

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# RUN: not llc -o - %s -mtriple=arm64-eabi -mattr=+jsconv -run-pass=legalizer 2>&1 | FileCheck %s
# CHECK: [[@LINE+11]]:49: missing implicit register operand 'implicit-def $nzcv'
...
---
name: test_jcvt
liveins:
- { reg: '$d0' }
body: |
bb.0:
liveins: $d0
renamable $w0 = FJCVTZS killed renamable $d0
RET undef $lr, implicit killed $w0
...