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AsmParser
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[AArch64][v8.5A] Add Memory Tagging instructions
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2018-10-02 10:04:39 +00:00 |
Disassembler
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[AArch64][v8.5A] Add Memory Tagging instructions
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2018-10-02 10:04:39 +00:00 |
InstPrinter
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[AArch64][v8.5A] Add Branch Target Identification instructions
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2018-09-27 14:54:33 +00:00 |
MCTargetDesc
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NFC: use bit_cast more in AArch64AddressingModes
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2018-09-11 04:08:05 +00:00 |
TargetInfo
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Utils
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[AArch64][v8.5A] Add Branch Target Identification instructions
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2018-09-27 14:54:33 +00:00 |
AArch64.h
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Re-commit: [globalisel] Add a combiner helpers for extending loads and use them in a pre-legalize combiner for AArch64
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2018-10-03 02:12:17 +00:00 |
AArch64.td
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[AArch64][v8.5A] Add MTE as an optional AArch64 extension
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2018-10-02 09:36:28 +00:00 |
AArch64A53Fix835769.cpp
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AArch64A57FPLoadBalancing.cpp
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llvm::sort(C.begin(), C.end(), ...) -> llvm::sort(C, ...)
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2018-09-27 02:13:45 +00:00 |
AArch64AdvSIMDScalarPass.cpp
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AArch64AsmPrinter.cpp
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[AArch64] Split zero cycle feature more granularly
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2018-09-28 19:05:09 +00:00 |
AArch64CallingConvention.h
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AArch64CallingConvention.td
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[AArch64] Implement aarch64_vector_pcs codegen support.
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2018-09-12 12:10:22 +00:00 |
AArch64CallLowering.cpp
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[AArch64] Support adding X[8-15,18] registers as CSRs.
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2018-09-22 22:17:50 +00:00 |
AArch64CallLowering.h
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[GlobalISel] Rewrite CallLowering::lowerReturn to accept multiple VRegs per Value
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2018-08-02 08:33:31 +00:00 |
AArch64CleanupLocalDynamicTLSPass.cpp
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AArch64CollectLOH.cpp
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AArch64CondBrTuning.cpp
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AArch64ConditionalCompares.cpp
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AArch64ConditionOptimizer.cpp
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AArch64DeadRegisterDefinitionsPass.cpp
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AArch64ExpandPseudoInsts.cpp
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[AArch64] Add Tiny Code Model for AArch64
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2018-08-22 11:31:39 +00:00 |
AArch64FalkorHWPFFix.cpp
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AArch64FastISel.cpp
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[AArch64] Support adding X[8-15,18] registers as CSRs.
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2018-09-22 22:17:50 +00:00 |
AArch64FrameLowering.cpp
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Revert r343317
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2018-09-28 17:01:50 +00:00 |
AArch64FrameLowering.h
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AArch64GenRegisterBankInfo.def
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AArch64InstrAtomics.td
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AArch64InstrFormats.td
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[AArch64][v8.5A] Add Memory Tagging instructions
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2018-10-02 10:04:39 +00:00 |
AArch64InstrInfo.cpp
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Revert "X86, AArch64, ARM: Do not attach debug location to spill/reload instructions"
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2018-10-02 18:35:44 +00:00 |
AArch64InstrInfo.h
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[MachineOutliner][AArch64] Add support for saving LR to a register
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2018-07-30 17:45:28 +00:00 |
AArch64InstrInfo.td
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[AArch64][v8.5A] Add Memory Tagging instructions
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2018-10-02 10:04:39 +00:00 |
AArch64InstructionSelector.cpp
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[AArch64] Add Tiny Code Model for AArch64
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2018-08-22 11:31:39 +00:00 |
AArch64ISelDAGToDAG.cpp
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[AArch64][v8.5A] Add speculation restriction system registers
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2018-09-27 14:05:46 +00:00 |
AArch64ISelLowering.cpp
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[AArch64] Share search bookkeeping in combines. NFCI.
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2018-09-25 15:30:22 +00:00 |
AArch64ISelLowering.h
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[AtomicExpandPass]: Add a hook for custom cmpxchg expansion in IR
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2018-09-19 14:51:42 +00:00 |
AArch64LegalizerInfo.cpp
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[AArch64][GlobalISel] Make G_BLOCK_ADDR legal.
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2018-07-31 00:08:56 +00:00 |
AArch64LegalizerInfo.h
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AArch64LoadStoreOptimizer.cpp
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[MI] Change the array of MachineMemOperand pointers to be
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2018-08-16 21:30:05 +00:00 |
AArch64MachineFunctionInfo.h
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Remove trailing space
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2018-07-30 19:41:25 +00:00 |
AArch64MacroFusion.cpp
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AArch64: Add FuseCryptoEOR fusion rules
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2018-09-19 20:50:51 +00:00 |
AArch64MacroFusion.h
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AArch64MCInstLower.cpp
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[MinGW] [AArch64] Add stubs for potential automatic dllimported variables
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2018-09-04 20:56:21 +00:00 |
AArch64MCInstLower.h
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AArch64PBQPRegAlloc.cpp
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AArch64PBQPRegAlloc.h
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AArch64PerfectShuffle.h
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AArch64PreLegalizerCombiner.cpp
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Add the missing new files from r343654
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2018-10-03 02:21:30 +00:00 |
AArch64PromoteConstant.cpp
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AArch64RedundantCopyElimination.cpp
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AArch64RegisterBankInfo.cpp
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AArch64RegisterBankInfo.h
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AArch64RegisterBanks.td
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AArch64RegisterInfo.cpp
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[Aarch64] Fix memcpy that was copying 4x too many bytes
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2018-09-23 18:43:28 +00:00 |
AArch64RegisterInfo.h
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[AArch64] Support adding X[8-15,18] registers as CSRs.
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2018-09-22 22:17:50 +00:00 |
AArch64RegisterInfo.td
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[AArch64][SVE] Asm: Add MOVPRFX instructions.
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2018-07-30 15:42:46 +00:00 |
AArch64SchedA53.td
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AArch64SchedA57.td
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AArch64SchedA57WriteRes.td
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AArch64SchedCyclone.td
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AArch64SchedExynosM1.td
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AArch64SchedExynosM3.td
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AArch64SchedFalkor.td
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AArch64SchedFalkorDetails.td
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AArch64SchedKryo.td
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AArch64SchedKryoDetails.td
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AArch64SchedThunderX2T99.td
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AArch64SchedThunderX.td
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AArch64Schedule.td
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AArch64SelectionDAGInfo.cpp
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AArch64SelectionDAGInfo.h
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AArch64SIMDInstrOpt.cpp
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AArch64StorePairSuppress.cpp
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AArch64Subtarget.cpp
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[AArch64] Support adding X[8-15,18] registers as CSRs.
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2018-09-22 22:17:50 +00:00 |
AArch64Subtarget.h
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[AArch64][v8.5A] Add Memory Tagging instructions
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2018-10-02 10:04:39 +00:00 |
AArch64SVEInstrInfo.td
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[AArch64][SVE] Asm: Enable instructions to be prefixed.
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2018-07-30 16:05:45 +00:00 |
AArch64SystemOperands.td
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[AArch64][v8.5A] Add Memory Tagging system registers
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2018-10-02 09:54:35 +00:00 |
AArch64TargetMachine.cpp
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Re-commit: [globalisel] Add a combiner helpers for extending loads and use them in a pre-legalize combiner for AArch64
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2018-10-03 02:12:17 +00:00 |
AArch64TargetMachine.h
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AArch64TargetObjectFile.cpp
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[AArch64] DWARF: do not generate AT_location for thread local
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2018-08-01 23:46:49 +00:00 |
AArch64TargetObjectFile.h
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AArch64TargetTransformInfo.cpp
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Remove trailing space
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2018-07-30 19:41:25 +00:00 |
AArch64TargetTransformInfo.h
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CMakeLists.txt
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Re-commit: [globalisel] Add a combiner helpers for extending loads and use them in a pre-legalize combiner for AArch64
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2018-10-03 02:12:17 +00:00 |
LLVMBuild.txt
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SVEInstrFormats.td
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Remove extra whitespace. NFC. (test commit)
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2018-09-28 08:45:28 +00:00 |