Jan Vesely 4c879ee690 AMDGPU/SI: Fix trunc i16 pattern ... Hit on ASICs that support 16bit instructions. Differential Revision: https://reviews.llvm.org/D30281 llvm-svn: 295990		2017-02-23 16:12:21 +00:00
..
AArch64	[AArch64] Extend AArch64RedundantCopyElimination to do simple copy propagation.	2017-02-22 19:10:45 +00:00
AMDGPU	AMDGPU/SI: Fix trunc i16 pattern	2017-02-23 16:12:21 +00:00
ARM	[ARM] GlobalISel: Lower call returns	2017-02-23 14:18:41 +00:00
AVR	[AVR] Disable integrated assembler for a few tests	2017-02-22 22:41:13 +00:00
BPF
Generic
Hexagon	[Hexagon] Patterns for CTPOP, BSWAP and BITREVERSE	2017-02-23 15:02:09 +00:00
Inputs
Lanai
Mips
MIR	MIRTests: Remove unnecessary 2>&1 redirection	2017-02-22 18:47:41 +00:00
MSP430
NVPTX	[NVPTX] Unify vectorization of load/stores of aggregate arguments and return values.	2017-02-21 22:56:05 +00:00
PowerPC	[DAGCombiner] revert r295336	2017-02-22 16:27:33 +00:00
SPARC
SystemZ
Thumb	[ARM] Fix constant islands pass.	2017-02-22 09:06:21 +00:00
Thumb2
WebAssembly	[WebAssembly] Configure codegen to legalize f16 values.	2017-02-22 16:28:00 +00:00
WinEH
X86	[X86][AVX] Disable VCVTSS2SD & VCVTSD2SS memory folding and fix the register class of their first input when creating node in fast-isel.	2017-02-23 13:15:44 +00:00
XCore