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llvm-mirror/lib/Target/AArch64
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Evandro Menezes 6b61a418d6 [AArch64] Fix Exynos predicates (NFC) 
Fix the logic in the definition of the `ExynosShiftExPred` as a more
specific version of `ExynosShiftPred`.  But, since `ExynosShiftExPred` is
not used yet, this change has NFC.

llvm-svn: 349091
2018-12-13 23:19:46 +00:00
..
AsmParser
[NFC][AArch64] Split out backend features
2018-12-06 15:39:17 +00:00
Disassembler
[AArch64][v8.5A] Add Memory Tagging instructions
2018-10-02 10:04:39 +00:00
InstPrinter
[AArch64][v8.5A] Add Branch Target Identification instructions
2018-09-27 14:54:33 +00:00
MCTargetDesc
[TableGen] Refactor macro names (NFC)
2018-11-27 20:58:27 +00:00
TargetInfo
Add backend name to Target to enable runtime info to be fed back into TableGen
2017-11-15 23:55:44 +00:00
Utils
[AArch64][v8.5A] Add Branch Target Identification instructions
2018-09-27 14:54:33 +00:00
AArch64.h
AArch64: add a pass to compress jump-table entries when possible.
2018-10-24 20:19:09 +00:00
AArch64.td
[AArch64] Refactor the Exynos scheduling predicates
2018-12-10 17:17:26 +00:00
AArch64A53Fix835769.cpp
Rename DEBUG macro to LLVM_DEBUG.
2018-05-14 12:53:11 +00:00
AArch64A57FPLoadBalancing.cpp
llvm::sort(C.begin(), C.end(), ...) -> llvm::sort(C, ...)
2018-09-27 02:13:45 +00:00
AArch64AdvSIMDScalarPass.cpp
Rename DEBUG macro to LLVM_DEBUG.
2018-05-14 12:53:11 +00:00
AArch64AsmPrinter.cpp
[COFF, ARM64] Emit COFF function header
2018-12-11 18:36:14 +00:00
AArch64BranchTargets.cpp
[AArch64][v8.5A] Branch Target Identification code-generation pass
2018-10-08 14:04:24 +00:00
AArch64CallingConvention.h
Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layering
2017-11-08 01:01:31 +00:00
AArch64CallingConvention.td
AArch64: clean up some whitespace in Windows CC (NFC)
2018-12-04 22:19:29 +00:00
AArch64CallLowering.cpp
[AArch64] Support adding X[8-15,18] registers as CSRs.
2018-09-22 22:17:50 +00:00
AArch64CallLowering.h
[GlobalISel] Rewrite CallLowering::lowerReturn to accept multiple VRegs per Value
2018-08-02 08:33:31 +00:00
AArch64CleanupLocalDynamicTLSPass.cpp
MachineFunction: Return reference from getFunction(); NFC
2017-12-15 22:22:58 +00:00
AArch64CollectLOH.cpp
Rename DEBUG macro to LLVM_DEBUG.
2018-05-14 12:53:11 +00:00
AArch64CompressJumpTables.cpp
AArch64: add a pass to compress jump-table entries when possible.
2018-10-24 20:19:09 +00:00
AArch64CondBrTuning.cpp
Rename DEBUG macro to LLVM_DEBUG.
2018-05-14 12:53:11 +00:00
AArch64ConditionalCompares.cpp
Rename DEBUG macro to LLVM_DEBUG.
2018-05-14 12:53:11 +00:00
AArch64ConditionOptimizer.cpp
Rename DEBUG macro to LLVM_DEBUG.
2018-05-14 12:53:11 +00:00
AArch64DeadRegisterDefinitionsPass.cpp
Rename DEBUG macro to LLVM_DEBUG.
2018-05-14 12:53:11 +00:00
AArch64ExpandPseudoInsts.cpp
[AArch64] Add Tiny Code Model for AArch64
2018-08-22 11:31:39 +00:00
AArch64FalkorHWPFFix.cpp
Rename DEBUG macro to LLVM_DEBUG.
2018-05-14 12:53:11 +00:00
AArch64FastISel.cpp
[COFF, ARM64] Implement Intrinsic.sponentry for AArch64
2018-11-01 23:22:25 +00:00
AArch64FrameLowering.cpp
[ARM64][Windows] Fix local stack size for funclets
2018-12-04 00:54:52 +00:00
AArch64FrameLowering.h
[ARM64] [Windows] Handle funclets
2018-11-09 23:33:30 +00:00
AArch64GenRegisterBankInfo.def
[AArch64][RegisterBankInfo] Teach instruction mapping about gpr32 -> fpr16 cross copies
2017-11-18 04:28:56 +00:00
AArch64InstrAtomics.td
[AArch64] Improve v8.1-A code-gen for atomic load-and
2018-02-12 17:03:11 +00:00
AArch64InstrFormats.td
[NFC][AArch64] Split out backend features
2018-12-06 15:39:17 +00:00
AArch64InstrInfo.cpp
[AArch64] Refactor the Exynos scheduling predicates
2018-12-10 17:17:26 +00:00
AArch64InstrInfo.h
[AArch64] Refactor the Exynos scheduling predicates
2018-12-10 17:17:26 +00:00
AArch64InstrInfo.td
[NFC][AArch64] Split out backend features
2018-12-06 15:39:17 +00:00
AArch64InstructionSelector.cpp
[GISel]: Refactor MachineIRBuilder to allow passing additional parameters to build Instrs
2018-12-11 00:48:50 +00:00
AArch64ISelDAGToDAG.cpp
[AArch64][v8.5A] Add speculation restriction system registers
2018-09-27 14:05:46 +00:00
AArch64ISelLowering.cpp
[AArch64] Catch some more CMN opportunities.
2018-12-13 10:31:32 +00:00
AArch64ISelLowering.h
[ARM64] [Windows] Handle funclets
2018-11-09 23:33:30 +00:00
AArch64LegalizerInfo.cpp
[GlobalISel] Restrict G_MERGE_VALUES capability and replace with new opcodes.
2018-12-10 18:44:58 +00:00
AArch64LegalizerInfo.h
[GISel]: Provide standard interface to observe changes in GISel passes
2018-12-05 20:14:52 +00:00
AArch64LoadStoreOptimizer.cpp
[MI] Change the array of MachineMemOperand pointers to be
2018-08-16 21:30:05 +00:00
AArch64MachineFunctionInfo.h
[COFF, ARM64] Make sure to forward arguments from vararg to musttail vararg
2018-10-30 20:46:10 +00:00
AArch64MacroFusion.cpp
[PATCH] [NFC][AArch64] Fix refactoring of macro fusion
2018-10-16 17:41:45 +00:00
AArch64MacroFusion.h
…
AArch64MCInstLower.cpp
[ARM64] [Windows] Handle funclets
2018-11-09 23:33:30 +00:00
AArch64MCInstLower.h
…
AArch64PBQPRegAlloc.cpp
Rename DEBUG macro to LLVM_DEBUG.
2018-05-14 12:53:11 +00:00
AArch64PBQPRegAlloc.h
…
AArch64PerfectShuffle.h
…
AArch64PfmCounters.td
[llvm-exegesis][NFC] Add a way to declare the default counter binding for unbound CPUs for a target.
2018-11-09 13:15:32 +00:00
AArch64PreLegalizerCombiner.cpp
[GISel]: Provide standard interface to observe changes in GISel passes
2018-12-05 20:14:52 +00:00
AArch64PromoteConstant.cpp
Rename DEBUG macro to LLVM_DEBUG.
2018-05-14 12:53:11 +00:00
AArch64RedundantCopyElimination.cpp
[CodeGen][AArch64] Use RegUnits to track register aliases. (NFC)
2018-05-23 17:49:38 +00:00
AArch64RegisterBankInfo.cpp
[AArch64] Map G_LOAD on FPR when the definition goes to a copy to FPR
2017-11-18 04:28:59 +00:00
AArch64RegisterBankInfo.h
[AArch64][RegisterBankInfo] Add mapping for G_FPEXT.
2017-11-02 23:38:19 +00:00
AArch64RegisterBanks.td
[aarch64][globalisel] Register banks and classes should have distinct names.
2017-10-18 00:12:43 +00:00
AArch64RegisterInfo.cpp
[ARM64] [Windows] Handle funclets
2018-11-09 23:33:30 +00:00
AArch64RegisterInfo.h
[ARM64] [Windows] Handle funclets
2018-11-09 23:33:30 +00:00
AArch64RegisterInfo.td
[AArch64][v8.5A] Restrict indirect tail calls to use x16/17 only when using BTI
2018-10-08 14:09:15 +00:00
AArch64SchedA53.td
[AArch64] Clean-up a few over-eager regexps in models.
2018-03-23 11:00:42 +00:00
AArch64SchedA57.td
[AArch64][SVE] Asm: Set SVE as unsupported feature for existing scheduler models.
2017-11-07 15:03:11 +00:00
AArch64SchedA57WriteRes.td
…
AArch64SchedCyclone.td
[AArch64][SVE] Asm: Set SVE as unsupported feature for existing scheduler models.
2017-11-07 15:03:11 +00:00
AArch64SchedExynosM1.td
[AArch64] Refactor the Exynos scheduling predicates
2018-12-10 17:17:26 +00:00
AArch64SchedExynosM3.td
[AArch64] Refactor the Exynos scheduling predicates
2018-12-10 17:17:26 +00:00
AArch64SchedFalkor.td
[TableGen] When trying to reuse a scheduler class for instructions from an InstRW, make sure we haven't already seen another InstRW containing this instruction on this CPU.
2018-03-18 19:56:15 +00:00
AArch64SchedFalkorDetails.td
[AArch64][Falkor] Correct load/store increment scheduling details
2018-03-20 13:46:35 +00:00
AArch64SchedKryo.td
[TableGen] When trying to reuse a scheduler class for instructions from an InstRW, make sure we haven't already seen another InstRW containing this instruction on this CPU.
2018-03-18 19:56:15 +00:00
AArch64SchedKryoDetails.td
…
AArch64SchedPredExynos.td
[AArch64] Fix Exynos predicates (NFC)
2018-12-13 23:19:46 +00:00
AArch64SchedPredicates.td
[AArch64] Refactor the scheduling predicates
2018-12-10 16:24:30 +00:00
AArch64SchedThunderX2T99.td
[TableGen] Emit a fatal error on inconsistencies in resource units vs cycles.
2018-06-13 09:41:49 +00:00
AArch64SchedThunderX.td
[TableGen] When trying to reuse a scheduler class for instructions from an InstRW, make sure we haven't already seen another InstRW containing this instruction on this CPU.
2018-03-18 19:56:15 +00:00
AArch64Schedule.td
[AArch64] Refactor the scheduling predicates (3/3) (NFC)
2018-11-26 21:47:46 +00:00
AArch64SelectionDAGInfo.cpp
AArch64/X86: Factor out common bzero logic; NFC
2017-12-18 23:14:28 +00:00
AArch64SelectionDAGInfo.h
…
AArch64SIMDInstrOpt.cpp
[TargetSchedule] shrink interface for init(); NFCI
2018-04-08 19:56:04 +00:00
AArch64StorePairSuppress.cpp
[CodeGen][NFC] Make TII::getMemOpBaseImmOfs return a base operand
2018-11-28 12:00:20 +00:00
AArch64Subtarget.cpp
[AArch64] Refactor the scheduling predicates (1/3) (NFC)
2018-11-26 21:47:28 +00:00
AArch64Subtarget.h
[NFC][AArch64] Split out backend features
2018-12-06 15:39:17 +00:00
AArch64SVEInstrInfo.td
[AArch64][SVE] Asm: Enable instructions to be prefixed.
2018-07-30 16:05:45 +00:00
AArch64SystemOperands.td
[NFC][AArch64] Split out backend features
2018-12-06 15:39:17 +00:00
AArch64TargetMachine.cpp
[Targets] Add errors for tiny and kernel codemodel on targets that don't support them
2018-12-07 12:10:23 +00:00
AArch64TargetMachine.h
(Re-landing) Expose a TargetMachine::getTargetTransformInfo function
2017-12-22 18:21:59 +00:00
AArch64TargetObjectFile.cpp
[AArch64] DWARF: do not generate AT_location for thread local
2018-08-01 23:46:49 +00:00
AArch64TargetObjectFile.h
Move TargetLoweringObjectFile from CodeGen to Target to fix layering
2018-03-23 23:58:19 +00:00
AArch64TargetTransformInfo.cpp
[LV] Support vectorization of interleave-groups that require an epilog under
2018-10-31 09:57:56 +00:00
AArch64TargetTransformInfo.h
[LV] Support vectorization of interleave-groups that require an epilog under
2018-10-31 09:57:56 +00:00
CMakeLists.txt
[llvm-exegesis][NFC] Add a way to declare the default counter binding for unbound CPUs for a target.
2018-11-09 13:15:32 +00:00
LLVMBuild.txt
…
SVEInstrFormats.td
Remove extra whitespace. NFC. (test commit)
2018-09-28 08:45:28 +00:00