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mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-22 10:42:39 +01:00
llvm-mirror/test/CodeGen/SystemZ
Ulrich Weigand 81afdbc83c [SystemZ] Add support for new cpu architecture - arch14
This patch adds support for the next-generation arch14
CPU architecture to the SystemZ backend.

This includes:
- Basic support for the new processor and its features.
- Detection of arch14 as host processor.
- Assembler/disassembler support for new instructions.
- New LLVM intrinsics for certain new instructions.
- Support for low-level builtins mapped to new LLVM intrinsics.
- New high-level intrinsics in vecintrin.h.
- Indicate support by defining  __VEC__ == 10304.

Note: No currently available Z system supports the arch14
architecture.  Once new systems become available, the
official system name will be added as supported -march name.
2021-07-26 16:57:28 +02:00
..
Large tests/CodeGen: Use %python lit substitution when invoking python 2021-07-06 18:46:36 -07:00
addr-01.ll [DAG] Reassociate Add with Or 2021-07-07 10:21:07 +01:00
addr-02.ll [DAG] Reassociate Add with Or 2021-07-07 10:21:07 +01:00
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inline-asm-i128.ll [SystemZ] Bugfix for the 'N' code for inline asm operand. 2021-07-12 15:04:08 +02:00
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memset-05.ll [SystemZ] Handle NoRegister in SystemZTargetLowering::emitMemMemWrapper(). 2021-07-19 20:04:44 +02:00
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vec-intrinsics-03.ll
vec-intrinsics-04.ll [SystemZ] Add support for new cpu architecture - arch14 2021-07-26 16:57:28 +02:00
vec-load-element.ll
vec-log-01.ll
vec-max-01.ll
vec-max-02.ll
vec-max-03.ll
vec-max-04.ll
vec-max-05.ll
vec-max-min-zerosplat.ll
vec-min-01.ll
vec-min-02.ll
vec-min-03.ll
vec-min-04.ll
vec-min-05.ll
vec-move-01.ll
vec-move-02.ll
vec-move-03.ll
vec-move-04.ll
vec-move-05.ll
vec-move-06.ll
vec-move-07.ll
vec-move-08.ll
vec-move-09.ll
vec-move-10.ll
vec-move-11.ll
vec-move-12.ll
vec-move-13.ll
vec-move-14.ll
vec-move-15.ll
vec-move-16.ll
vec-move-17.ll
vec-move-18.ll
vec-move-19.ll
vec-move-20.ll
vec-move-21.ll
vec-move-22.ll
vec-move-23.ll
vec-move-24.ll
vec-mul-01.ll
vec-mul-02.ll
vec-mul-03.ll
vec-mul-04.ll
vec-mul-05.ll
vec-neg-01.ll
vec-neg-02.ll
vec-or-01.ll
vec-or-02.ll
vec-or-03.ll
vec-perm-01.ll
vec-perm-02.ll
vec-perm-03.ll
vec-perm-04.ll
vec-perm-05.ll
vec-perm-06.ll
vec-perm-07.ll
vec-perm-08.ll
vec-perm-09.ll
vec-perm-10.ll
vec-perm-11.ll
vec-perm-12.ll
vec-perm-13.ll
vec-perm-14.ll
vec-rem.ll
vec-round-01.ll
vec-round-02.ll
vec-sext.ll
vec-shift-01.ll
vec-shift-02.ll
vec-shift-03.ll
vec-shift-04.ll
vec-shift-05.ll
vec-shift-06.ll
vec-shift-07.ll
vec-sqrt-01.ll
vec-sqrt-02.ll
vec-strict-add-01.ll
vec-strict-add-02.ll
vec-strict-cmp-01.ll
vec-strict-cmp-02.ll
vec-strict-cmp-03.ll
vec-strict-cmps-01.ll
vec-strict-cmps-02.ll
vec-strict-cmps-03.ll
vec-strict-conv-01.ll
vec-strict-conv-02.ll
vec-strict-conv-03.ll
vec-strict-div-01.ll
vec-strict-div-02.ll
vec-strict-max-01.ll
vec-strict-min-01.ll
vec-strict-mul-01.ll
vec-strict-mul-02.ll
vec-strict-mul-03.ll
vec-strict-mul-04.ll
vec-strict-mul-05.ll
vec-strict-round-01.ll
vec-strict-round-02.ll
vec-strict-sqrt-01.ll
vec-strict-sqrt-02.ll
vec-strict-sub-01.ll
vec-strict-sub-02.ll
vec-sub-01.ll
vec-sub-02.ll
vec-trunc-to-i1.ll
vec-xor-01.ll
vec-xor-02.ll
vec-zext.ll
vector-constrained-fp-intrinsics.ll
vectorizer-output-3xi32.ll
xor-01.ll
xor-02.ll
xor-03.ll
xor-04.ll
xor-05.ll
xor-06.ll
xor-07.ll
xor-08.ll