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07186d14a9
Vector load/store instructions support an optional alignment field that the compiler can use to provide known alignment info to the hardware. If the field is used (and the information is correct), the hardware may be able (on some models) to perform faster memory accesses than otherwise. This patch adds support for alignment hints in the assembler and disassembler, and fills in known alignment during codegen. llvm-svn: 363806
185 lines
4.3 KiB
LLVM
185 lines
4.3 KiB
LLVM
; Test vector stores.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
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; Test v16i8 stores.
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define void @f1(<16 x i8> %val, <16 x i8> *%ptr) {
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; CHECK-LABEL: f1:
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; CHECK: vst %v24, 0(%r2), 3
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; CHECK: br %r14
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store <16 x i8> %val, <16 x i8> *%ptr
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ret void
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}
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; Test v8i16 stores.
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define void @f2(<8 x i16> %val, <8 x i16> *%ptr) {
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; CHECK-LABEL: f2:
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; CHECK: vst %v24, 0(%r2), 3
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; CHECK: br %r14
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store <8 x i16> %val, <8 x i16> *%ptr
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ret void
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}
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; Test v4i32 stores.
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define void @f3(<4 x i32> %val, <4 x i32> *%ptr) {
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; CHECK-LABEL: f3:
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; CHECK: vst %v24, 0(%r2), 3
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; CHECK: br %r14
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store <4 x i32> %val, <4 x i32> *%ptr
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ret void
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}
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; Test v2i64 stores.
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define void @f4(<2 x i64> %val, <2 x i64> *%ptr) {
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; CHECK-LABEL: f4:
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; CHECK: vst %v24, 0(%r2), 3
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; CHECK: br %r14
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store <2 x i64> %val, <2 x i64> *%ptr
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ret void
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}
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; Test v4f32 stores.
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define void @f5(<4 x float> %val, <4 x float> *%ptr) {
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; CHECK-LABEL: f5:
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; CHECK: vst %v24, 0(%r2), 3
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; CHECK: br %r14
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store <4 x float> %val, <4 x float> *%ptr
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ret void
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}
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; Test v2f64 stores.
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define void @f6(<2 x double> %val, <2 x double> *%ptr) {
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; CHECK-LABEL: f6:
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; CHECK: vst %v24, 0(%r2), 3
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; CHECK: br %r14
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store <2 x double> %val, <2 x double> *%ptr
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ret void
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}
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; Test the highest aligned in-range offset.
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define void @f7(<16 x i8> %val, <16 x i8> *%base) {
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; CHECK-LABEL: f7:
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; CHECK: vst %v24, 4080(%r2), 3
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; CHECK: br %r14
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%ptr = getelementptr <16 x i8>, <16 x i8> *%base, i64 255
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store <16 x i8> %val, <16 x i8> *%ptr
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ret void
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}
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; Test the highest unaligned in-range offset.
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define void @f8(<16 x i8> %val, i8 *%base) {
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; CHECK-LABEL: f8:
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; CHECK: vst %v24, 4095(%r2)
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; CHECK: br %r14
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%addr = getelementptr i8, i8 *%base, i64 4095
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%ptr = bitcast i8 *%addr to <16 x i8> *
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store <16 x i8> %val, <16 x i8> *%ptr, align 1
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ret void
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}
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; Test the next offset up, which requires separate address logic,
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define void @f9(<16 x i8> %val, <16 x i8> *%base) {
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; CHECK-LABEL: f9:
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; CHECK: aghi %r2, 4096
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; CHECK: vst %v24, 0(%r2), 3
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; CHECK: br %r14
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%ptr = getelementptr <16 x i8>, <16 x i8> *%base, i64 256
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store <16 x i8> %val, <16 x i8> *%ptr
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ret void
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}
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; Test negative offsets, which also require separate address logic,
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define void @f10(<16 x i8> %val, <16 x i8> *%base) {
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; CHECK-LABEL: f10:
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; CHECK: aghi %r2, -16
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; CHECK: vst %v24, 0(%r2), 3
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; CHECK: br %r14
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%ptr = getelementptr <16 x i8>, <16 x i8> *%base, i64 -1
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store <16 x i8> %val, <16 x i8> *%ptr
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ret void
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}
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; Check that indexes are allowed.
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define void @f11(<16 x i8> %val, i8 *%base, i64 %index) {
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; CHECK-LABEL: f11:
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; CHECK: vst %v24, 0(%r3,%r2)
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; CHECK: br %r14
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%addr = getelementptr i8, i8 *%base, i64 %index
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%ptr = bitcast i8 *%addr to <16 x i8> *
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store <16 x i8> %val, <16 x i8> *%ptr, align 1
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ret void
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}
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; Test v2i8 stores.
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define void @f12(<2 x i8> %val, <2 x i8> *%ptr) {
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; CHECK-LABEL: f12:
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; CHECK: vsteh %v24, 0(%r2), 0
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; CHECK: br %r14
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store <2 x i8> %val, <2 x i8> *%ptr
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ret void
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}
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; Test v4i8 stores.
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define void @f13(<4 x i8> %val, <4 x i8> *%ptr) {
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; CHECK-LABEL: f13:
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; CHECK: vstef %v24, 0(%r2)
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; CHECK: br %r14
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store <4 x i8> %val, <4 x i8> *%ptr
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ret void
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}
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; Test v8i8 stores.
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define void @f14(<8 x i8> %val, <8 x i8> *%ptr) {
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; CHECK-LABEL: f14:
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; CHECK: vsteg %v24, 0(%r2)
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; CHECK: br %r14
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store <8 x i8> %val, <8 x i8> *%ptr
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ret void
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}
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; Test v2i16 stores.
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define void @f15(<2 x i16> %val, <2 x i16> *%ptr) {
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; CHECK-LABEL: f15:
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; CHECK: vstef %v24, 0(%r2), 0
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; CHECK: br %r14
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store <2 x i16> %val, <2 x i16> *%ptr
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ret void
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}
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; Test v4i16 stores.
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define void @f16(<4 x i16> %val, <4 x i16> *%ptr) {
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; CHECK-LABEL: f16:
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; CHECK: vsteg %v24, 0(%r2)
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; CHECK: br %r14
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store <4 x i16> %val, <4 x i16> *%ptr
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ret void
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}
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; Test v2i32 stores.
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define void @f17(<2 x i32> %val, <2 x i32> *%ptr) {
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; CHECK-LABEL: f17:
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; CHECK: vsteg %v24, 0(%r2), 0
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; CHECK: br %r14
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store <2 x i32> %val, <2 x i32> *%ptr
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ret void
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}
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; Test v2f32 stores.
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define void @f18(<2 x float> %val, <2 x float> *%ptr) {
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; CHECK-LABEL: f18:
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; CHECK: vsteg %v24, 0(%r2), 0
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; CHECK: br %r14
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store <2 x float> %val, <2 x float> *%ptr
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ret void
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}
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; Test quadword-aligned stores.
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define void @f19(<16 x i8> %val, <16 x i8> *%ptr) {
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; CHECK-LABEL: f19:
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; CHECK: vst %v24, 0(%r2), 4
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; CHECK: br %r14
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store <16 x i8> %val, <16 x i8> *%ptr, align 16
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ret void
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}
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