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llvm-mirror/lib/Target/Hexagon
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Sam Parker 6ffd0e23b3 [CostModel] Unify getArithmeticInstrCost 
Add the remaining arithmetic opcodes into the generic implementation
of getUserCost and then call this from getInstructionThroughput. Most
of the backends have been modified to return the base implementation
for cost kinds other RecipThroughput. The outlier here is AMDGPU
which already uses getArithmeticInstrCost for all the cost kinds.
This change means that most of the opcodes can be removed from that
backends implementation of getUserCost.

Differential Revision: https://reviews.llvm.org/D80992
2020-06-10 09:08:45 +01:00
..
AsmParser
std::isspace -> llvm::isSpace (where locale should be ignored)
2020-05-02 15:36:04 +02:00
Disassembler
[Hexagon] v67+ HVX register pairs should support either direction
2020-02-14 12:43:43 -06:00
MCTargetDesc
[MC] Change MCCFIInstruction::createDefCfa to cfiDefCfa which does not negate Offset
2020-05-22 15:47:26 -07:00
TargetInfo
CMake: Make most target symbols hidden by default
2020-01-14 19:46:52 -08:00
BitTracker.cpp
[Hexagon] Fixes -Wrange-loop-analysis warnings
2019-12-22 19:35:02 +01:00
BitTracker.h
…
CMakeLists.txt
Move RDF from Hexagon to Codegen
2020-03-17 12:43:14 -07:00
Hexagon.h
…
Hexagon.td
[TableGen] Support combining AssemblerPredicates with ORs
2020-03-13 17:13:51 +00:00
HexagonArch.h
[Hexagon] Add support for Hexagon/HVX v67 ISA
2020-01-20 16:16:49 -06:00
HexagonAsmPrinter.cpp
[MCStreamer] De-capitalize EmitValue EmitIntValue{,InHex}
2020-02-14 23:08:40 -08:00
HexagonAsmPrinter.h
[AsmPrinter][MCStreamer] De-capitalize EmitInstruction and EmitCFI*
2020-02-13 22:08:55 -08:00
HexagonBitSimplify.cpp
[Hexagon] Add support for Hexagon v67t microarchitecture (tiny core)
2020-01-21 11:35:10 -06:00
HexagonBitTracker.cpp
[Alignment][NFC] Transition to MachineFrameInfo::getObjectAlign()
2020-04-01 14:08:28 +00:00
HexagonBitTracker.h
…
HexagonBlockRanges.cpp
Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC
2019-08-01 23:27:28 +00:00
HexagonBlockRanges.h
…
HexagonBranchRelaxation.cpp
[Alignment][NFC] Deprecate Align::None()
2020-01-24 12:53:58 +01:00
HexagonCallingConv.td
…
HexagonCFGOptimizer.cpp
…
HexagonCommonGEP.cpp
Fix several places that were calling verifyFunction or verifyModule without checking the return value.
2020-05-18 13:28:46 -07:00
HexagonConstExtenders.cpp
[Hexagon] Add a target feature to disable compound instructions
2020-01-16 12:37:30 -06:00
HexagonConstPropagation.cpp
[Hexagon] Add support for Hexagon v67t microarchitecture (tiny core)
2020-01-21 11:35:10 -06:00
HexagonCopyToCombine.cpp
[Pass] Ensure we don't include PassSupport.h or PassAnalysisSupport.h directly
2020-04-26 12:58:20 +01:00
HexagonDepArch.h
[Hexagon] Add support for Hexagon v67t microarchitecture (tiny core)
2020-01-21 11:35:10 -06:00
HexagonDepArch.td
[TableGen] Support combining AssemblerPredicates with ORs
2020-03-13 17:13:51 +00:00
HexagonDepDecoders.inc
[Hexagon] Remove unused operand definitions: s10_0Imm and s10_6Imm
2020-01-23 09:38:54 -06:00
HexagonDepIICHVX.td
[Hexagon] Add support for Hexagon/HVX v67 ISA
2020-01-20 16:16:49 -06:00
HexagonDepIICScalar.td
[Hexagon] Add support for Hexagon v67t microarchitecture (tiny core)
2020-01-21 11:35:10 -06:00
HexagonDepInstrFormats.td
[Hexagon] Add support for Hexagon/HVX v67 ISA
2020-01-20 16:16:49 -06:00
HexagonDepInstrInfo.td
[Hexagon] Add support for Hexagon/HVX v67 ISA
2020-01-20 16:16:49 -06:00
HexagonDepITypes.h
[Hexagon] Add support for Hexagon/HVX v67 ISA
2020-01-20 16:16:49 -06:00
HexagonDepITypes.td
[Hexagon] Add support for Hexagon/HVX v67 ISA
2020-01-20 16:16:49 -06:00
HexagonDepMapAsm2Intrin.td
[TableGen] Drop deprecated leading # operation (NOP) and replace ## with #
2020-04-25 16:26:45 -07:00
HexagonDepMappings.td
[Hexagon] Add support for Hexagon/HVX v67 ISA
2020-01-20 16:16:49 -06:00
HexagonDepMask.h
[Hexagon] Add support for Hexagon/HVX v67 ISA
2020-01-20 16:16:49 -06:00
HexagonDepOperands.td
[Hexagon] Remove unused operand definitions: s10_0Imm and s10_6Imm
2020-01-23 09:38:54 -06:00
HexagonDepTimingClasses.h
[Hexagon] Add support for Hexagon/HVX v67 ISA
2020-01-20 16:16:49 -06:00
HexagonEarlyIfConv.cpp
MachineBasicBlock::updateTerminator now requires an explicit layout successor.
2020-06-06 22:30:51 -04:00
HexagonExpandCondsets.cpp
Make more use of MachineInstr::mayLoadOrStore.
2019-12-19 11:51:52 +00:00
HexagonFixupHwLoops.cpp
[Pass] Ensure we don't include PassSupport.h or PassAnalysisSupport.h directly
2020-04-26 12:58:20 +01:00
HexagonFrameLowering.cpp
[MC] Change MCCFIInstruction::createDefCfa to cfiDefCfa which does not negate Offset
2020-05-22 15:47:26 -07:00
HexagonFrameLowering.h
CodeGen: Use Register in TargetFrameLowering
2020-04-07 17:07:44 -04:00
HexagonGenExtract.cpp
[IR] Split out target specific intrinsic enums into separate headers
2019-12-11 18:02:14 -08:00
HexagonGenInsert.cpp
Reland 'Fixed -Wdeprecated-copy warnings. NFCI.'
2019-11-23 23:09:39 +01:00
HexagonGenMux.cpp
[Hexagon] Validate the iterators before converting them to mux.
2019-11-14 13:01:16 -06:00
HexagonGenPredicate.cpp
Sink all InitializePasses.h includes
2019-11-13 16:34:37 -08:00
HexagonHardwareLoops.cpp
CodeGen: Convert some TII hooks to use Register
2020-04-03 14:52:54 -04:00
HexagonHazardRecognizer.cpp
…
HexagonHazardRecognizer.h
…
HexagonIICHVX.td
…
HexagonIICScalar.td
[llvm] NFC: Fix trivial typo in rst and td files
2020-04-23 14:26:32 +09:00
HexagonInstrFormats.td
[llvm] NFC: Fix trivial typo in rst and td files
2020-04-23 14:26:32 +09:00
HexagonInstrFormatsV60.td
…
HexagonInstrFormatsV65.td
[llvm] NFC: Fix trivial typo in rst and td files
2020-04-23 14:26:32 +09:00
HexagonInstrInfo.cpp
[AMDGPU/MemOpsCluster] Let mem ops clustering logic also consider number of clustered bytes
2020-06-01 22:52:34 +05:30
HexagonInstrInfo.h
[AMDGPU/MemOpsCluster] Let mem ops clustering logic also consider number of clustered bytes
2020-06-01 22:52:34 +05:30
HexagonIntrinsics.td
[TableGen] Drop deprecated leading # operation (NOP) and replace ## with #
2020-04-25 16:26:45 -07:00
HexagonIntrinsicsV5.td
…
HexagonIntrinsicsV60.td
[Hexagon] Change HVX vector predicate types from v512/1024i1 to v64/128i1
2020-02-19 14:14:56 -06:00
HexagonISelDAGToDAG.cpp
[Alignment][NFC] Deprecate getMaxAlignment
2020-03-18 14:48:45 +01:00
HexagonISelDAGToDAG.h
[Hexagon] Remove unused forward declarations. NFC.
2020-04-22 18:26:50 +01:00
HexagonISelDAGToDAGHVX.cpp
[Hexagon] Change HVX vector predicate types from v512/1024i1 to v64/128i1
2020-02-19 14:14:56 -06:00
HexagonISelLowering.cpp
Revert "[Alignment][NFC] Migrate TargetLowering::allowsMemoryAccess"
2020-06-09 10:43:59 +00:00
HexagonISelLowering.h
Revert "[Alignment][NFC] Migrate TargetLowering::allowsMemoryAccess"
2020-06-09 10:43:59 +00:00
HexagonISelLoweringHVX.cpp
[SelectionDAG] Use Align/MaybeAlign for ConstantPoolSDNode.
2020-05-08 16:04:11 -07:00
HexagonLoopIdiomRecognition.cpp
[SCEV] Move ScalarEvolutionExpander.cpp to Transforms/Utils (NFC).
2020-05-20 10:53:40 +01:00
HexagonMachineFunctionInfo.cpp
…
HexagonMachineFunctionInfo.h
Add support for Linux/Musl ABI
2020-01-20 09:59:56 -06:00
HexagonMachineScheduler.cpp
…
HexagonMachineScheduler.h
…
HexagonMapAsm2IntrinV62.gen.td
…
HexagonMapAsm2IntrinV65.gen.td
…
HexagonMCInstLower.cpp
[Hexagon][NFC] Rename VK_Hexagon_PCREL to VK_PCREL
2020-02-19 09:52:58 -06:00
HexagonNewValueJump.cpp
Sink all InitializePasses.h includes
2019-11-13 16:34:37 -08:00
HexagonOperands.td
…
HexagonOptAddrMode.cpp
Move RDF from Hexagon to Codegen
2020-03-17 12:43:14 -07:00
HexagonOptimizeSZextends.cpp
[IR] Split out target specific intrinsic enums into separate headers
2019-12-11 18:02:14 -08:00
HexagonPatterns.td
[Hexagon] Fix fshl/fshr -> combine() bug identified in D75114
2020-03-06 17:23:10 +00:00
HexagonPatternsHVX.td
[Hexagon] Bitcast v4i16 to v8i8, unify no-op casts between scalar and HVX
2019-09-23 14:33:27 +00:00
HexagonPatternsV65.td
…
HexagonPeephole.cpp
[Pass] Ensure we don't include PassSupport.h or PassAnalysisSupport.h directly
2020-04-26 12:58:20 +01:00
HexagonPseudo.td
[TableGen] Drop deprecated leading # operation (NOP) and replace ## with #
2020-04-25 16:26:45 -07:00
HexagonRDFOpt.cpp
Move RDF from Hexagon to Codegen
2020-03-17 12:43:14 -07:00
HexagonRegisterInfo.cpp
CodeGen: Use Register in TargetFrameLowering
2020-04-07 17:07:44 -04:00
HexagonRegisterInfo.h
[TargetRegisterInfo] Default trackLivenessAfterRegAlloc() to true
2020-01-19 14:20:37 -08:00
HexagonRegisterInfo.td
[Hexagon] Change HVX vector predicate types from v512/1024i1 to v64/128i1
2020-02-19 14:14:56 -06:00
HexagonSchedule.td
[Hexagon] Add support for Hexagon v67t microarchitecture (tiny core)
2020-01-21 11:35:10 -06:00
HexagonScheduleV5.td
…
HexagonScheduleV55.td
…
HexagonScheduleV60.td
…
HexagonScheduleV62.td
…
HexagonScheduleV65.td
…
HexagonScheduleV66.td
…
HexagonScheduleV67.td
[Hexagon] Add support for Hexagon/HVX v67 ISA
2020-01-20 16:16:49 -06:00
HexagonScheduleV67T.td
[Hexagon] Add support for Hexagon v67t microarchitecture (tiny core)
2020-01-21 11:35:10 -06:00
HexagonSelectionDAGInfo.cpp
…
HexagonSelectionDAGInfo.h
…
HexagonSplitConst32AndConst64.cpp
Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
2019-08-15 19:22:08 +00:00
HexagonSplitDouble.cpp
CodeGen: Convert some TII hooks to use Register
2020-04-03 14:52:54 -04:00
HexagonStoreWidening.cpp
[Alignment][NFC] Use Align version of getMachineMemOperand
2020-03-30 15:46:27 +00:00
HexagonSubtarget.cpp
[Hexagon] Check isInstr() before getInstr() with SUnit
2020-05-14 08:47:54 -05:00
HexagonSubtarget.h
Provide operand indices to adjustSchedDependency
2020-04-17 11:08:44 +01:00
HexagonTargetMachine.cpp
[Hexagon] Add support for Hexagon/HVX v67 ISA
2020-01-20 16:16:49 -06:00
HexagonTargetMachine.h
…
HexagonTargetObjectFile.cpp
TargetLoweringObjectFile.h - remove unnecessary includes. NFCI.
2020-05-19 09:28:13 +01:00
HexagonTargetObjectFile.h
TargetLoweringObjectFile.h - remove unnecessary includes. NFCI.
2020-05-19 09:28:13 +01:00
HexagonTargetStreamer.h
[MC] De-capitalize another set of MCStreamer::Emit* functions
2020-02-14 19:26:52 -08:00
HexagonTargetTransformInfo.cpp
[CostModel] Unify getArithmeticInstrCost
2020-06-10 09:08:45 +01:00
HexagonTargetTransformInfo.h
[NFCI][CostModel] Refactor getIntrinsicInstrCost
2020-05-20 11:59:08 +01:00
HexagonVectorLoopCarriedReuse.cpp
[IR] Split out target specific intrinsic enums into separate headers
2019-12-11 18:02:14 -08:00
HexagonVectorPrint.cpp
[Hexagon] v67+ HVX register pairs should support either direction
2020-02-14 12:43:43 -06:00
HexagonVExtract.cpp
[Pass] Ensure we don't include PassSupport.h or PassAnalysisSupport.h directly
2020-04-26 12:58:20 +01:00
HexagonVLIWPacketizer.cpp
[Target] Fix typos. NFC
2020-05-22 14:40:43 +02:00
HexagonVLIWPacketizer.h
[Hexagon] Add support for Hexagon v67t microarchitecture (tiny core)
2020-01-21 11:35:10 -06:00
LLVMBuild.txt
…
RDFCopy.cpp
Move RDF from Hexagon to Codegen
2020-03-17 12:43:14 -07:00
RDFCopy.h
Move RDF from Hexagon to Codegen
2020-03-17 12:43:14 -07:00
RDFDeadCode.cpp
Move RDF from Hexagon to Codegen
2020-03-17 12:43:14 -07:00
RDFDeadCode.h
Move RDF from Hexagon to Codegen
2020-03-17 12:43:14 -07:00