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llvm-mirror/test/CodeGen
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Matt Arsenault 6842150224 AMDGPU/GlobalISel: Fix 8-byte aligned, 96-bit scalar loads 
These are legal since we can do a 96-bit load on some subtargets, but
this is only for vector loads. If we can't widen the load, it needs to
be broken down once known scalar. For 16-byte alignment, widen to a
128-bit load.
2020-06-15 11:33:16 -04:00
..
AArch64
[AArch64] Fix BTI instruction emission.
2020-06-15 15:04:36 +02:00
AMDGPU
AMDGPU/GlobalISel: Fix 8-byte aligned, 96-bit scalar loads
2020-06-15 11:33:16 -04:00
ARC
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ARM
[ARM][MachineOutliner] Fix no-lr-save testcase.
2020-06-15 16:09:31 +02:00
AVR
[AVR][test] Remove test for naked function containing a return.
2020-06-09 09:06:47 +01:00
BPF
[BPF] fix incorrect type in BPFISelDAGToDAG readonly load optimization
2020-06-11 19:31:06 -07:00
Generic
[Tests] Migrate a number of tests to gc-live bundle representation
2020-06-05 16:44:04 -07:00
Hexagon
Simplify MachineVerifier's block-successor verification.
2020-06-06 22:30:51 -04:00
Inputs
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Lanai
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Mips
[DAGCombine] Generalize the case (add (or x, c1), c2) -> (add x, (c1 + c2))
2020-06-12 13:53:08 -04:00
MIR
[MachineVerifier] Verify that a DBG_VALUE has a debug location
2020-05-28 13:53:40 -07:00
MSP430
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NVPTX
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PowerPC
[PowerPC] Do not add the relocation addend to the instruction encoding
2020-06-15 09:51:34 -05:00
RISCV
[DAGCombine] Generalize the case (add (or x, c1), c2) -> (add x, (c1 + c2))
2020-06-12 13:53:08 -04:00
SPARC
[SPARC] Lower fp16 ops to libcalls
2020-06-10 19:15:26 -07:00
SystemZ
[CostModel] Unify Shuffle and InsertElement Costs
2020-06-10 09:13:34 +01:00
Thumb
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Thumb2
[ARM] Add some MVE vecreduce tests. NFC
2020-06-09 12:07:19 +01:00
VE
[VE] Support relocation information in MC layer
2020-06-15 11:24:53 +02:00
WebAssembly
[WebAssembly] Adding 64-bit versions of all load & store ops.
2020-06-15 08:31:56 -07:00
WinCFGuard
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WinEH
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X86
[X86][SSE] LowerVectorAllZeroTest - add support for >256-bit vectors
2020-06-15 15:30:24 +01:00
XCore
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