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AsmParser
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[AArch64][SVE] Asm: Support for structured LD4 (scalar+imm) load instructions.
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2018-04-16 10:46:18 +00:00 |
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Disassembler
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[AArch64][SVE] Asm: Support for structured LD4 (scalar+imm) load instructions.
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2018-04-16 10:46:18 +00:00 |
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InstPrinter
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[AArch64][SVE] Asm: Support for structured LD4 (scalar+imm) load instructions.
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2018-04-16 10:46:18 +00:00 |
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MCTargetDesc
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Recommit r329716 "Add missing nullptr check before getSection() to AArch64MachObjectWriter::recordRelocation"
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2018-04-10 19:46:43 +00:00 |
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TargetInfo
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Add backend name to Target to enable runtime info to be fed back into TableGen
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2017-11-15 23:55:44 +00:00 |
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Utils
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[AArch64][SVE] Asm: Predicate patterns
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2018-01-22 10:46:00 +00:00 |
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AArch64.h
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[AArch64] Avoid SIMD interleaved store instruction for Exynos.
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2017-12-08 00:58:49 +00:00 |
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AArch64.td
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[PATCH] [AArch64] Add new target feature to fuse conditional select
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2018-02-23 19:27:43 +00:00 |
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AArch64A53Fix835769.cpp
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Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layering
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2017-11-08 01:01:31 +00:00 |
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AArch64A57FPLoadBalancing.cpp
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[AArch64] Change std::sort to llvm::sort in response to r327219
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2018-04-04 18:20:28 +00:00 |
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AArch64AdvSIMDScalarPass.cpp
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MachineFunction: Return reference from getFunction(); NFC
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2017-12-15 22:22:58 +00:00 |
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AArch64AsmPrinter.cpp
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[CodeGen] Hoist common AsmPrinter code out of X86, ARM, and AArch64
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2018-01-17 23:55:23 +00:00 |
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AArch64CallingConvention.h
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Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layering
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2017-11-08 01:01:31 +00:00 |
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AArch64CallingConvention.td
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AArch64: Implement support for the shadowcallstack attribute.
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2018-04-04 21:55:44 +00:00 |
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AArch64CallLowering.cpp
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[IR][CodeGen] Remove dependency on EVT from IR/Function.cpp. Move EVT to CodeGen layer.
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2018-03-29 17:21:10 +00:00 |
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AArch64CallLowering.h
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AArch64CleanupLocalDynamicTLSPass.cpp
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MachineFunction: Return reference from getFunction(); NFC
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2017-12-15 22:22:58 +00:00 |
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AArch64CollectLOH.cpp
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Revert "[CodeGen] Move printing '\n' from MachineInstr::print to MachineBasicBlock::print"
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2018-02-19 15:08:49 +00:00 |
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AArch64CondBrTuning.cpp
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MachineFunction: Return reference from getFunction(); NFC
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2017-12-15 22:22:58 +00:00 |
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AArch64ConditionalCompares.cpp
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MachineFunction: Return reference from getFunction(); NFC
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2017-12-15 22:22:58 +00:00 |
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AArch64ConditionOptimizer.cpp
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MachineFunction: Return reference from getFunction(); NFC
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2017-12-15 22:22:58 +00:00 |
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AArch64DeadRegisterDefinitionsPass.cpp
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MachineFunction: Return reference from getFunction(); NFC
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2017-12-15 22:22:58 +00:00 |
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AArch64ExpandPseudoInsts.cpp
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[AArch64] Fold adds with tprel_lo12_nc and secrel_lo12 into a following ldr/str
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2018-03-12 18:47:43 +00:00 |
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AArch64FalkorHWPFFix.cpp
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[AArch64][Falkor] Fix bug in Falkor HWPF collision avoidance pass.
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2018-04-10 21:43:03 +00:00 |
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AArch64FastISel.cpp
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[IR][CodeGen] Remove dependency on EVT from IR/Function.cpp. Move EVT to CodeGen layer.
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2018-03-29 17:21:10 +00:00 |
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AArch64FrameLowering.cpp
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[AArch64] Move AFI->setRedZone(false) to top of emitPrologue
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2018-04-12 16:16:18 +00:00 |
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AArch64FrameLowering.h
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Move TargetFrameLowering.h to CodeGen where it's implemented
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2017-11-03 22:32:11 +00:00 |
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AArch64GenRegisterBankInfo.def
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[AArch64][RegisterBankInfo] Teach instruction mapping about gpr32 -> fpr16 cross copies
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2017-11-18 04:28:56 +00:00 |
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AArch64InstrAtomics.td
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[AArch64] Improve v8.1-A code-gen for atomic load-and
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2018-02-12 17:03:11 +00:00 |
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AArch64InstrFormats.td
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[AArch64][SVE] Asm: Add support for SVE INDEX instructions.
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2018-04-10 07:01:53 +00:00 |
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AArch64InstrInfo.cpp
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[MachineOutliner] Keep track of fns that use a redzone in AArch64FunctionInfo
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2018-04-03 21:56:10 +00:00 |
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AArch64InstrInfo.h
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[MachineOutliner] Add useMachineOutliner target hook
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2018-04-04 19:13:31 +00:00 |
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AArch64InstrInfo.td
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[AArch64] Add patterns matching (fabs (fsub x y)) to (fabd x y)
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2018-04-04 10:12:53 +00:00 |
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AArch64InstructionSelector.cpp
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[AArch64][GlobalISel] When copying from a gpr32 to an fpr16 reg, convert to fpr32 first.
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2018-02-20 05:11:57 +00:00 |
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AArch64ISelDAGToDAG.cpp
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Revert r329956, "AArch64: Introduce a DAG combine for folding offsets into addresses."
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2018-04-13 20:21:00 +00:00 |
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AArch64ISelLowering.cpp
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Revert r329956, "AArch64: Introduce a DAG combine for folding offsets into addresses."
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2018-04-13 20:21:00 +00:00 |
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AArch64ISelLowering.h
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[AArch64] Don't reduce the width of loads if it prevents combining a shift
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2018-03-23 14:47:07 +00:00 |
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AArch64LegalizerInfo.cpp
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[globalisel][legalizerinfo] Add support for the Lower action in getActionDefinitionsBuilder() and use it in AArch64.
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2018-04-09 21:10:09 +00:00 |
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AArch64LegalizerInfo.h
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[aarch64][globalisel] Define G_ATOMIC_CMPXCHG and G_ATOMICRMW_* and make them legal
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2017-11-28 20:21:15 +00:00 |
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AArch64LoadStoreOptimizer.cpp
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[CodeGen] Add a new pass for PostRA sink
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2018-03-22 20:06:47 +00:00 |
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AArch64MachineFunctionInfo.h
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[MachineOutliner] Keep track of fns that use a redzone in AArch64FunctionInfo
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2018-04-03 21:56:10 +00:00 |
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AArch64MacroFusion.cpp
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[PATCH] [AArch64] Add new target feature to fuse conditional select
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2018-02-23 19:27:43 +00:00 |
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AArch64MacroFusion.h
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AArch64MCInstLower.cpp
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Move TargetLoweringObjectFile from CodeGen to Target to fix layering
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2018-03-23 23:58:19 +00:00 |
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AArch64MCInstLower.h
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AArch64PBQPRegAlloc.cpp
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Rename LiveIntervalAnalysis.h to LiveIntervals.h
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2017-12-13 02:51:04 +00:00 |
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AArch64PBQPRegAlloc.h
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AArch64PerfectShuffle.h
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AArch64PromoteConstant.cpp
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AArch64RedundantCopyElimination.cpp
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MachineFunction: Return reference from getFunction(); NFC
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2017-12-15 22:22:58 +00:00 |
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AArch64RegisterBankInfo.cpp
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[AArch64] Map G_LOAD on FPR when the definition goes to a copy to FPR
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2017-11-18 04:28:59 +00:00 |
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AArch64RegisterBankInfo.h
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[AArch64][RegisterBankInfo] Add mapping for G_FPEXT.
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2017-11-02 23:38:19 +00:00 |
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AArch64RegisterBanks.td
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[aarch64][globalisel] Register banks and classes should have distinct names.
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2017-10-18 00:12:43 +00:00 |
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AArch64RegisterInfo.cpp
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AArch64: Implement support for the shadowcallstack attribute.
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2018-04-04 21:55:44 +00:00 |
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AArch64RegisterInfo.h
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[AArch64] Implement dynamic stack probing for windows
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2018-02-17 14:26:32 +00:00 |
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AArch64RegisterInfo.td
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[AArch64][SVE] Asm: Support for structured LD4 (scalar+imm) load instructions.
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2018-04-16 10:46:18 +00:00 |
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AArch64SchedA53.td
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[AArch64] Clean-up a few over-eager regexps in models.
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2018-03-23 11:00:42 +00:00 |
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AArch64SchedA57.td
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[AArch64][SVE] Asm: Set SVE as unsupported feature for existing scheduler models.
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2017-11-07 15:03:11 +00:00 |
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AArch64SchedA57WriteRes.td
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AArch64SchedCyclone.td
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[AArch64][SVE] Asm: Set SVE as unsupported feature for existing scheduler models.
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2017-11-07 15:03:11 +00:00 |
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AArch64SchedExynosM1.td
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[AArch64][NFC] Make all ProcResource definitions include their SchedModel.
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2018-02-01 12:12:01 +00:00 |
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AArch64SchedExynosM3.td
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[AArch64] Adjust the cost model for Exynos M3
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2018-04-03 22:57:17 +00:00 |
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AArch64SchedFalkor.td
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[TableGen] When trying to reuse a scheduler class for instructions from an InstRW, make sure we haven't already seen another InstRW containing this instruction on this CPU.
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2018-03-18 19:56:15 +00:00 |
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AArch64SchedFalkorDetails.td
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[AArch64][Falkor] Correct load/store increment scheduling details
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2018-03-20 13:46:35 +00:00 |
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AArch64SchedKryo.td
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[TableGen] When trying to reuse a scheduler class for instructions from an InstRW, make sure we haven't already seen another InstRW containing this instruction on this CPU.
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2018-03-18 19:56:15 +00:00 |
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AArch64SchedKryoDetails.td
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AArch64SchedThunderX2T99.td
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[AArch64] Clean-up a few over-eager regexps in models.
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2018-03-23 11:00:42 +00:00 |
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AArch64SchedThunderX.td
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[TableGen] When trying to reuse a scheduler class for instructions from an InstRW, make sure we haven't already seen another InstRW containing this instruction on this CPU.
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2018-03-18 19:56:15 +00:00 |
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AArch64Schedule.td
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AArch64SelectionDAGInfo.cpp
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AArch64/X86: Factor out common bzero logic; NFC
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2017-12-18 23:14:28 +00:00 |
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AArch64SelectionDAGInfo.h
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AArch64SIMDInstrOpt.cpp
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[TargetSchedule] shrink interface for init(); NFCI
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2018-04-08 19:56:04 +00:00 |
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AArch64StorePairSuppress.cpp
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[TargetSchedule] shrink interface for init(); NFCI
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2018-04-08 19:56:04 +00:00 |
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AArch64Subtarget.cpp
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AArch64: Implement support for the shadowcallstack attribute.
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2018-04-04 21:55:44 +00:00 |
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AArch64Subtarget.h
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[PATCH] [AArch64] Add new target feature to fuse conditional select
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2018-02-23 19:27:43 +00:00 |
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AArch64SVEInstrInfo.td
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[AArch64][SVE] Asm: Support for structured LD4 (scalar+imm) load instructions.
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2018-04-16 10:46:18 +00:00 |
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AArch64SystemOperands.td
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[AArch64] Fix spelling of ICH_ELRSR_EL2 system register
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2018-02-06 09:39:04 +00:00 |
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AArch64TargetMachine.cpp
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MachO: trap unreachable instructions
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2018-04-13 22:25:20 +00:00 |
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AArch64TargetMachine.h
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(Re-landing) Expose a TargetMachine::getTargetTransformInfo function
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2017-12-22 18:21:59 +00:00 |
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AArch64TargetObjectFile.cpp
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AArch64TargetObjectFile.h
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Move TargetLoweringObjectFile from CodeGen to Target to fix layering
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2018-03-23 23:58:19 +00:00 |
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AArch64TargetTransformInfo.cpp
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[AArch64] Implement getArithmeticReductionCost
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2018-03-16 11:34:15 +00:00 |
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AArch64TargetTransformInfo.h
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[AArch64] Implement getArithmeticReductionCost
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2018-03-16 11:34:15 +00:00 |
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CMakeLists.txt
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Sort targetgen calls in lib/Target/*/CMakeLists.
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2018-04-04 12:37:44 +00:00 |
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LLVMBuild.txt
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SVEInstrFormats.td
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[AArch64][SVE] Asm: Support for structured LD4 (scalar+imm) load instructions.
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2018-04-16 10:46:18 +00:00 |
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