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AsmParser
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[AMDGPU][MC] Disabled use of 2 different literals with SOP2/SOPC instructions
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2019-01-18 13:57:43 +00:00 |
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Disassembler
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AMDGPU: Separate R600 and GCN TableGen files
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2018-06-28 23:47:12 +00:00 |
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InstPrinter
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[AMDGPU][MC][GFX8+][DISASSEMBLER] Corrected 1/2pi value for 64-bit operands
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2019-01-18 15:17:17 +00:00 |
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MCTargetDesc
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AMDGPU: Use an ABS32_LO relocation for SCRATCH_RSRC_DWORD1
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2018-12-19 11:55:03 +00:00 |
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TargetInfo
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Utils
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[AMDGPU] Add support for TFE/LWE in image intrinsics. 2nd try
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2019-01-14 11:55:24 +00:00 |
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AMDGPU.h
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AMDGPU: Add llvm.amdgcn.ds.ordered.add & swap
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2019-01-16 15:43:53 +00:00 |
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AMDGPU.td
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AMDGPU: Remove llvm.SI.load.const
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2019-01-18 20:27:02 +00:00 |
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AMDGPUAliasAnalysis.cpp
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Allow subclassing ExternalAA
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2018-11-07 20:26:42 +00:00 |
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AMDGPUAliasAnalysis.h
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Allow subclassing ExternalAA
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2018-11-07 20:26:42 +00:00 |
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AMDGPUAlwaysInlinePass.cpp
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AMDGPU: Remove remnants of old address space mapping
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2018-08-31 05:49:54 +00:00 |
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AMDGPUAnnotateKernelFeatures.cpp
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Revert r348971: [AMDGPU] Support for "uniform-work-group-size" attribute
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2018-12-13 21:23:12 +00:00 |
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AMDGPUAnnotateUniformValues.cpp
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AMDGPU: Remove llvm.SI.load.const
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2019-01-18 20:27:02 +00:00 |
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AMDGPUArgumentUsageInfo.cpp
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AMDGPU/AMDHSA: Remove GridWorkGroupCountX/Y/Z
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2018-06-21 18:36:04 +00:00 |
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AMDGPUArgumentUsageInfo.h
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AMDGPU: Refactor Subtarget classes
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2018-07-11 20:59:01 +00:00 |
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AMDGPUAsmPrinter.cpp
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[AMDGPU] Emit MessagePack HSA Metadata for v3 code object
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2018-12-12 19:39:27 +00:00 |
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AMDGPUAsmPrinter.h
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[AMDGPU] Emit MessagePack HSA Metadata for v3 code object
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2018-12-12 19:39:27 +00:00 |
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AMDGPUAtomicOptimizer.cpp
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[AMDGPU] Fix the new atomic optimizer in pixel shaders.
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2018-11-05 12:04:48 +00:00 |
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AMDGPUCallingConv.td
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AMDGPU: Partially fix handling of packed amdgpu_ps arguments
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2018-08-01 19:57:34 +00:00 |
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AMDGPUCallLowering.cpp
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AMDGPU: Remove remnants of old address space mapping
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2018-08-31 05:49:54 +00:00 |
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AMDGPUCallLowering.h
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AMDGPU: Remove remnants of old address space mapping
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2018-08-31 05:49:54 +00:00 |
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AMDGPUCodeGenPrepare.cpp
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[IRBuilder] Fixup CreateIntrinsic to allow specifying Types to Mangle.
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2018-10-08 10:32:33 +00:00 |
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AMDGPUFeatures.td
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AMDGPU: Allow fp32-denormals feature for r600 targets
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2018-08-01 15:04:36 +00:00 |
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AMDGPUFixFunctionBitcasts.cpp
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[AMDGPU] Add a pass to promote bitcast calls
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2018-10-26 13:18:36 +00:00 |
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AMDGPUFrameLowering.cpp
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AMDGPUFrameLowering.h
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AMDGPUGenRegisterBankInfo.def
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AMDGPU/GlobalISel: Introduce vcc reg bank
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2019-01-08 06:30:53 +00:00 |
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AMDGPUGISel.td
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AMDGPU/GlobalISel: Select amdgcn.cvt.pkrtz to 64-bit instructions
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2018-10-08 17:49:29 +00:00 |
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AMDGPUHSAMetadataStreamer.cpp
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[AMDGPU] Emit MessagePack HSA Metadata for v3 code object
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2018-12-12 19:39:27 +00:00 |
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AMDGPUHSAMetadataStreamer.h
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[AMDGPU] Emit MessagePack HSA Metadata for v3 code object
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2018-12-12 19:39:27 +00:00 |
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AMDGPUInline.cpp
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fix typos aggressively; NFC
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2018-11-07 14:35:36 +00:00 |
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AMDGPUInstrInfo.cpp
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AMDGPU: Refactor Subtarget classes
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2018-07-11 20:59:01 +00:00 |
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AMDGPUInstrInfo.h
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AMDGPU: Refactor Subtarget classes
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2018-07-11 20:59:01 +00:00 |
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AMDGPUInstrInfo.td
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AMDGPU: Remove PHI loop condition optimization
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2018-10-31 13:26:48 +00:00 |
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AMDGPUInstructions.td
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AMDGPU: Raise the priority of MAD24 in instruction selection.
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2019-01-15 23:12:36 +00:00 |
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AMDGPUInstructionSelector.cpp
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Revert "AMDGPU/GlobalISel: Implement select for G_INSERT"
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2018-10-11 23:36:46 +00:00 |
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AMDGPUInstructionSelector.h
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Revert "AMDGPU/GlobalISel: Implement select for G_INSERT"
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2018-10-11 23:36:46 +00:00 |
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AMDGPUISelDAGToDAG.cpp
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AMDGPU: Don't peel of the offset if the resulting base could possibly be negative in Indirect addressing.
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2018-12-21 20:57:34 +00:00 |
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AMDGPUISelLowering.cpp
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AMDGPU: Remove llvm.SI.load.const
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2019-01-18 20:27:02 +00:00 |
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AMDGPUISelLowering.h
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AMDGPU: Add llvm.amdgcn.ds.ordered.add & swap
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2019-01-16 15:43:53 +00:00 |
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AMDGPULegalizerInfo.cpp
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AMDGPU/GlobalISel: Legalize more types for select
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2019-01-18 21:42:55 +00:00 |
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AMDGPULegalizerInfo.h
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AMDGPU: Refactor Subtarget classes
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2018-07-11 20:59:01 +00:00 |
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AMDGPULibCalls.cpp
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AMDGPU: Remove remnants of old address space mapping
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2018-08-31 05:49:54 +00:00 |
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AMDGPULibFunc.cpp
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[AMDGPU] Fix discarded result of addAttribute
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2018-12-09 21:56:50 +00:00 |
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AMDGPULibFunc.h
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AMDGPU: Fix missing C++ mode comment
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2018-06-20 19:45:40 +00:00 |
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AMDGPULowerIntrinsics.cpp
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AMDGPU: Refactor Subtarget classes
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2018-07-11 20:59:01 +00:00 |
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AMDGPULowerKernelArguments.cpp
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AMDGPU: Fix offsets for < 4-byte aggregate kernel arguments
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2018-12-07 22:12:17 +00:00 |
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AMDGPULowerKernelAttributes.cpp
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AMDGPU: Add pass to optimize reqd_work_group_size
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2018-05-18 21:35:00 +00:00 |
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AMDGPUMachineCFGStructurizer.cpp
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AMDGPU: Refactor Subtarget classes
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2018-07-11 20:59:01 +00:00 |
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AMDGPUMachineFunction.cpp
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Reapply "AMDGPU: Fix handling of alignment padding in DAG argument lowering"
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2018-07-20 09:05:08 +00:00 |
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AMDGPUMachineFunction.h
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Reapply "AMDGPU: Fix handling of alignment padding in DAG argument lowering"
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2018-07-20 09:05:08 +00:00 |
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AMDGPUMachineModuleInfo.cpp
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AMDGPUMachineModuleInfo.h
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AMDGPUMacroFusion.cpp
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[AMDGPU] Always pass TRI into findRegister[Use/Def]OperandIdx
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2018-11-09 17:58:59 +00:00 |
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AMDGPUMacroFusion.h
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AMDGPUMCInstLower.cpp
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AMDGPU: Fix getInstSizeInBytes
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2018-08-29 07:46:09 +00:00 |
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AMDGPUOpenCLEnqueuedBlockLowering.cpp
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[AMDGPU] Change enqueue kernel handle type
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2018-06-13 17:31:51 +00:00 |
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AMDGPUPerfHintAnalysis.cpp
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AMDGPU: Remove remnants of old address space mapping
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2018-08-31 05:49:54 +00:00 |
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AMDGPUPerfHintAnalysis.h
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Fix -Winconsistent-missing-overrides in AMDGPU code
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2018-05-25 17:46:24 +00:00 |
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AMDGPUPromoteAlloca.cpp
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[AMDGPU] Extend promote alloca vectorization
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2018-11-08 00:16:23 +00:00 |
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AMDGPUPTNote.h
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[AMDGPU] Emit MessagePack HSA Metadata for v3 code object
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2018-12-12 19:39:27 +00:00 |
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AMDGPURegAsmNames.inc.cpp
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AMDGPURegisterBankInfo.cpp
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AMDGPU/GlobalISel: Introduce vcc reg bank
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2019-01-08 06:30:53 +00:00 |
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AMDGPURegisterBankInfo.h
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AMDGPU/GlobalISel: Legality/regbankselect for atomicrmw/atomic_cmpxchg
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2018-12-20 00:33:49 +00:00 |
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AMDGPURegisterBanks.td
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AMDGPU/GlobalISel: Introduce vcc reg bank
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2019-01-08 06:30:53 +00:00 |
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AMDGPURegisterInfo.cpp
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AMDGPU: Remove #include "MCTargetDesc/AMDGPUMCTargetDesc.h" from common headers
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2018-05-22 02:03:23 +00:00 |
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AMDGPURegisterInfo.h
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[TargetRegisterInfo] Remove temporary hook enableMultipleCopyHints()
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2018-10-05 14:23:11 +00:00 |
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AMDGPURegisterInfo.td
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AMDGPU: Separate R600 and GCN TableGen files
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2018-06-28 23:47:12 +00:00 |
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AMDGPURewriteOutArguments.cpp
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[opaque pointer types] Remove some calls to generic Type subtype accessors.
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2019-01-10 16:07:20 +00:00 |
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AMDGPUSearchableTables.td
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AMDGPU: Add llvm.amdgcn.ds.ordered.add & swap
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2019-01-16 15:43:53 +00:00 |
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AMDGPUSubtarget.cpp
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[AMDGPU] Add support for TFE/LWE in image intrinsics. 2nd try
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2019-01-14 11:55:24 +00:00 |
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AMDGPUSubtarget.h
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[AMDGPU] Add support for TFE/LWE in image intrinsics. 2nd try
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2019-01-14 11:55:24 +00:00 |
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AMDGPUTargetMachine.cpp
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[AMDGPU] Add support for TFE/LWE in image intrinsics. 2nd try
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2019-01-14 11:55:24 +00:00 |
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AMDGPUTargetMachine.h
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AMDGPU: Remove llvm.SI.load.const
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2019-01-18 20:27:02 +00:00 |
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AMDGPUTargetObjectFile.cpp
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[AMDGPU] Change section name with metadata access
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2019-01-03 11:22:58 +00:00 |
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AMDGPUTargetObjectFile.h
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[AMDGPU] Set metadata access for explicit section
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2018-12-12 11:20:04 +00:00 |
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AMDGPUTargetTransformInfo.cpp
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[AMDGPU] Add some missing always-uniform values.
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2019-01-18 16:39:27 +00:00 |
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AMDGPUTargetTransformInfo.h
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AMDGPU: Remove remnants of old address space mapping
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2018-08-31 05:49:54 +00:00 |
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AMDGPUUnifyDivergentExitNodes.cpp
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[NFC] Rename the DivergenceAnalysis to LegacyDivergenceAnalysis
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2018-08-30 14:21:36 +00:00 |
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AMDGPUUnifyMetadata.cpp
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AMDILCFGStructurizer.cpp
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AMDGPU: Separate R600 and GCN TableGen files
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2018-06-28 23:47:12 +00:00 |
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AMDKernelCodeT.h
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BUFInstructions.td
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[AMDGPU] Extend the SI Load/Store optimizer to combine more things.
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2018-12-12 16:15:21 +00:00 |
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CaymanInstructions.td
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CMakeLists.txt
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AMDGPU: Remove llvm.SI.load.const
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2019-01-18 20:27:02 +00:00 |
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DSInstructions.td
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AMDGPU: Add llvm.amdgcn.ds.ordered.add & swap
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2019-01-16 15:43:53 +00:00 |
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EvergreenInstructions.td
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AMDGPU: Refactor Subtarget classes
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2018-07-11 20:59:01 +00:00 |
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FLATInstructions.td
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[AMDGPU] Add FixupVectorISel pass, currently Supports SREGs in GLOBAL LD/ST
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2018-11-16 01:13:34 +00:00 |
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GCNDPPCombine.cpp
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Revert "[AMDGPU] Fix DPP combiner"
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2019-01-09 15:21:53 +00:00 |
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GCNHazardRecognizer.cpp
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AMDGPU: Add llvm.amdgcn.ds.ordered.add & swap
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2019-01-16 15:43:53 +00:00 |
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GCNHazardRecognizer.h
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AMDGPU: Refactor Subtarget classes
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2018-07-11 20:59:01 +00:00 |
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GCNILPSched.cpp
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ScheduleDAG: Cleanup dumping code; NFC
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2018-09-19 00:23:35 +00:00 |
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GCNIterativeScheduler.cpp
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llvm::sort(C.begin(), C.end(), ...) -> llvm::sort(C, ...)
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2018-09-27 02:13:45 +00:00 |
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GCNIterativeScheduler.h
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GCNMinRegStrategy.cpp
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ScheduleDAG: Cleanup dumping code; NFC
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2018-09-19 00:23:35 +00:00 |
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GCNProcessors.td
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[AMDGPU] Defined gfx909 Raven Ridge 2
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2018-10-24 08:14:07 +00:00 |
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GCNRegPressure.cpp
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AMDGPU: Refactor Subtarget classes
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2018-07-11 20:59:01 +00:00 |
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GCNRegPressure.h
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AMDGPU: Refactor Subtarget classes
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2018-07-11 20:59:01 +00:00 |
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GCNSchedStrategy.cpp
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AMDGPU: Refactor Subtarget classes
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2018-07-11 20:59:01 +00:00 |
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GCNSchedStrategy.h
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AMDGPU: Refactor Subtarget classes
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2018-07-11 20:59:01 +00:00 |
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LLVMBuild.txt
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[AMDGPU] Emit MessagePack HSA Metadata for v3 code object
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2018-12-12 19:39:27 +00:00 |
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MIMGInstructions.td
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[AMDGPU] Add support for TFE/LWE in image intrinsics. 2nd try
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2019-01-14 11:55:24 +00:00 |
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R600.td
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Reapply "AMDGPU: Fix handling of alignment padding in DAG argument lowering"
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2018-07-20 09:05:08 +00:00 |
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R600AsmPrinter.cpp
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AMDGPU: Refactor Subtarget classes
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2018-07-11 20:59:01 +00:00 |
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R600AsmPrinter.h
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AMDGPU: Split R600 AsmPrinter code into its own class
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2018-05-24 20:02:01 +00:00 |
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R600ClauseMergePass.cpp
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AMDGPU: Separate R600 and GCN TableGen files
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2018-06-28 23:47:12 +00:00 |
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R600ControlFlowFinalizer.cpp
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AMDGPU: Refactor Subtarget classes
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2018-07-11 20:59:01 +00:00 |
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R600Defines.h
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R600EmitClauseMarkers.cpp
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[AMDGPU] Always pass TRI into findRegister[Use/Def]OperandIdx
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2018-11-09 17:58:59 +00:00 |
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R600ExpandSpecialInstrs.cpp
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AMDGPU: Separate R600 and GCN TableGen files
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2018-06-28 23:47:12 +00:00 |
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R600FrameLowering.cpp
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R600FrameLowering.h
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R600InstrFormats.td
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AMDGPU: Refactor Subtarget classes
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2018-07-11 20:59:01 +00:00 |
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R600InstrInfo.cpp
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[AMDGPU] Always pass TRI into findRegister[Use/Def]OperandIdx
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2018-11-09 17:58:59 +00:00 |
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R600InstrInfo.h
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[PSV] Update API to be able to use TargetCustom without UB.
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2018-08-20 19:23:45 +00:00 |
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R600Instructions.td
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AMDGPU: Remove remnants of old address space mapping
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2018-08-31 05:49:54 +00:00 |
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R600ISelLowering.cpp
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[SelectionDAG] Add FoldBUILD_VECTOR to simplify new BUILD_VECTOR nodes
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2018-10-30 10:32:11 +00:00 |
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R600ISelLowering.h
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AMDGPU/R600: Convert kernel param loads to use PARAM_I_ADDRESS
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2018-08-01 18:36:07 +00:00 |
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R600MachineFunctionInfo.cpp
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R600MachineFunctionInfo.h
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R600MachineScheduler.cpp
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Fix clang -Wimplicit-fallthrough warnings across llvm, NFC
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2018-11-01 19:54:45 +00:00 |
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R600MachineScheduler.h
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R600OpenCLImageTypeLoweringPass.cpp
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AMDGPU: Rename OpenCL lowering pass to be R600 specific.
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2018-05-13 10:04:48 +00:00 |
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R600OptimizeVectorRegisters.cpp
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AMDGPU: Separate R600 and GCN TableGen files
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2018-06-28 23:47:12 +00:00 |
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R600Packetizer.cpp
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AMDGPU: Separate R600 and GCN TableGen files
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2018-06-28 23:47:12 +00:00 |
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R600Processors.td
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AMDGPU: Separate R600 and GCN TableGen files
|
2018-06-28 23:47:12 +00:00 |
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R600RegisterInfo.cpp
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AMDGPU: Separate R600 and GCN TableGen files
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2018-06-28 23:47:12 +00:00 |
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R600RegisterInfo.h
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AMDGPU: Refactor Subtarget classes
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2018-07-11 20:59:01 +00:00 |
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R600RegisterInfo.td
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AMDGPU: Separate R600 and GCN TableGen files
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2018-06-28 23:47:12 +00:00 |
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R600Schedule.td
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R700Instructions.td
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AMDGPU: Refactor Subtarget classes
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2018-07-11 20:59:01 +00:00 |
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SIAddIMGInit.cpp
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[AMDGPU] Add support for TFE/LWE in image intrinsics. 2nd try
|
2019-01-14 11:55:24 +00:00 |
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SIAnnotateControlFlow.cpp
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AMDGPU: test for uniformity of branch instruction, not its condition
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2019-01-07 15:52:28 +00:00 |
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SIDebuggerInsertNops.cpp
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AMDGPU: Refactor Subtarget classes
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2018-07-11 20:59:01 +00:00 |
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SIDefines.h
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[AMDGPU] Add new Mode Register pass
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2018-12-10 12:06:10 +00:00 |
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SIFixSGPRCopies.cpp
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AMDGPU: Rewrite SILowerI1Copies to always stay on SALU
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2018-10-31 13:27:08 +00:00 |
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SIFixupVectorISel.cpp
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[AMDGPU] Disable SReg Global LD/ST, perf regression
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2018-11-30 18:29:17 +00:00 |
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SIFixVGPRCopies.cpp
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AMDGPU: Refactor Subtarget classes
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2018-07-11 20:59:01 +00:00 |
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SIFixWWMLiveness.cpp
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[AMDGPU] Reworked SIFixWWMLiveness
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2018-08-02 23:31:32 +00:00 |
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SIFoldOperands.cpp
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[AMDGPU] Fix scalar operand folding bug that causes SHOC performance regression.
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2019-01-03 19:55:32 +00:00 |
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SIFormMemoryClauses.cpp
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llvm::sort(C.begin(), C.end(), ...) -> llvm::sort(C, ...)
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2018-09-27 02:13:45 +00:00 |
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SIFrameLowering.cpp
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AMDGPU: Rename isAmdCodeObjectV2 -> isAmdHsaOrMesa
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2018-10-04 21:02:16 +00:00 |
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SIFrameLowering.h
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AMDGPU: Refactor Subtarget classes
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2018-07-11 20:59:01 +00:00 |
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SIInsertSkips.cpp
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AMDGPU: Fix analyzeBranch failing with pseudoterminators
|
2018-11-16 05:03:02 +00:00 |
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SIInsertWaitcnts.cpp
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AMDGPU: Add llvm.amdgcn.ds.ordered.add & swap
|
2019-01-16 15:43:53 +00:00 |
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SIInstrFormats.td
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[AMDGPU] Add new Mode Register pass
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2018-12-10 12:06:10 +00:00 |
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SIInstrInfo.cpp
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AMDGPU: Remove llvm.SI.load.const
|
2019-01-18 20:27:02 +00:00 |
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SIInstrInfo.h
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AMDGPU: Add llvm.amdgcn.ds.ordered.add & swap
|
2019-01-16 15:43:53 +00:00 |
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SIInstrInfo.td
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AMDGPU: Add llvm.amdgcn.ds.ordered.add & swap
|
2019-01-16 15:43:53 +00:00 |
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SIInstructions.td
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AMDGPU: Add a fast path for icmp.i1(src, false, NE)
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2019-01-15 02:13:18 +00:00 |
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SIISelLowering.cpp
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AMDGPU: Remove llvm.SI.load.const
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2019-01-18 20:27:02 +00:00 |
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SIISelLowering.h
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[AMDGPU] Promote constant offset to the immediate by finding a new base with 13bit constant offset from the nearby instructions.
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2018-12-14 21:13:14 +00:00 |
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SILoadStoreOptimizer.cpp
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[AMDGPU] Fix dwordx3/southern-islands failures.
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2019-01-10 16:21:08 +00:00 |
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SILowerControlFlow.cpp
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AMDGPU: Remove PHI loop condition optimization
|
2018-10-31 13:26:48 +00:00 |
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SILowerI1Copies.cpp
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AMDGPU: Rewrite SILowerI1Copies to always stay on SALU
|
2018-10-31 13:27:08 +00:00 |
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SIMachineFunctionInfo.cpp
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[AMDGPU] Remove FeatureVGPRSpilling
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2018-10-31 18:54:06 +00:00 |
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SIMachineFunctionInfo.h
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AMDGPU/AMDHSA: Remove GridWorkGroupCountX/Y/Z
|
2018-06-21 18:36:04 +00:00 |
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SIMachineScheduler.cpp
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[CodeGen][NFC] Make TII::getMemOpBaseImmOfs return a base operand
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2018-11-28 12:00:20 +00:00 |
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SIMachineScheduler.h
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SIMemoryLegalizer.cpp
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[AMDGPU] Change the l1 flush instruction for AMDPAL/MESA3D.
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2018-12-10 16:35:53 +00:00 |
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SIModeRegister.cpp
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[AMDGPU] Add new Mode Register pass - minor fix
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2018-12-10 16:23:30 +00:00 |
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SIOptimizeExecMasking.cpp
|
AMDGPU: Refactor Subtarget classes
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2018-07-11 20:59:01 +00:00 |
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SIOptimizeExecMaskingPreRA.cpp
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[AMDGPU] Fix build failure, second attempt
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2018-12-13 05:52:11 +00:00 |
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SIPeepholeSDWA.cpp
|
[AMDGPU] Add sdwa support for ADD|SUB U64 decomposed Pseudos
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2018-12-03 13:04:54 +00:00 |
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SIProgramInfo.h
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[AMDGPU] Refactor HSAMetadataStream::emitKernel (NFC)
|
2018-07-10 17:31:32 +00:00 |
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SIRegisterInfo.cpp
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[AMDGPU] Simplify negated condition
|
2018-12-13 03:17:40 +00:00 |
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SIRegisterInfo.h
|
[AMDGPU] Simplify negated condition
|
2018-12-13 03:17:40 +00:00 |
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SIRegisterInfo.td
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AMDGPU: Remove v16i8 from register classes
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2019-01-07 13:31:55 +00:00 |
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SISchedule.td
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SIShrinkInstructions.cpp
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[AMDGPU] Shrink scalar AND, OR, XOR instructions
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2018-12-07 15:33:21 +00:00 |
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SIWholeQuadMode.cpp
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AMDGPU: Refactor Subtarget classes
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2018-07-11 20:59:01 +00:00 |
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SMInstructions.td
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AMDGPU: Allow f32 types for llvm.amdgcn.s.buffer.load
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2018-12-07 18:41:39 +00:00 |
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SOPInstructions.td
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[AMDGPU][MC] Disabled use of 2 different literals with SOP2/SOPC instructions
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2019-01-18 13:57:43 +00:00 |
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VIInstrFormats.td
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VIInstructions.td
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VOP1Instructions.td
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[AMDGPU] Add new Mode Register pass
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2018-12-10 12:06:10 +00:00 |
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VOP2Instructions.td
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[AMDGPU] Add new Mode Register pass
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2018-12-10 12:06:10 +00:00 |
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VOP3Instructions.td
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[AMDGPU] Add new Mode Register pass
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2018-12-10 12:06:10 +00:00 |
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VOP3PInstructions.td
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[AMDGPU] Separate feature dot-insts
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2019-01-10 03:25:20 +00:00 |
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VOPCInstructions.td
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AMDGPU: Implement llvm.amdgcn.icmp/fcmp for i16/f16
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2018-08-15 21:25:20 +00:00 |
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VOPInstructions.td
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[AMDGPU] Combine DPP mov with use instructions (VOP1/2/3)
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2018-11-30 14:21:56 +00:00 |
