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b52bf01ef4
llvm-mirror/lib/Target/AMDGPU
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Tom Stellard b52bf01ef4 AMDGPU/SI: Don't use fixup_si_rodata for scratch rsrc relocations 
Summary:
We need to set the fixup type to FK_Data_4 for the
SCRATCH_RSRC_DWORD[01] symbols, since these require absolute
relocations, and fixup_si_rodata is for relative relocations.

Reviewers: arsenm, kzhuravl

Subscribers: arsenm, kzhuravl, llvm-commits

Differential Revision: http://reviews.llvm.org/D21153

llvm-svn: 272417
2016-06-10 19:26:38 +00:00
..
AsmParser [AMDGPU] AsmParser: Support for sext() modifier in SDWA. Some code cleaning in AMDGPUOperand. 2016-06-10 09:57:59 +00:00
Disassembler AMDGPU: Fix trailing whitespace 2016-06-10 02:18:02 +00:00
InstPrinter [AMDGPU] AsmParser: Support for sext() modifier in SDWA. Some code cleaning in AMDGPUOperand. 2016-06-10 09:57:59 +00:00
MCTargetDesc AMDGPU/SI: Don't use fixup_si_rodata for scratch rsrc relocations 2016-06-10 19:26:38 +00:00
TargetInfo
Utils [AMDGPU][llvm-mc] s_getreg/setreg* - hwreg - factor out strings/literals etc. 2016-05-26 17:00:33 +00:00
AMDGPU.h AMDGPU: Properly initialize SIShrinkInstructions 2016-06-09 23:18:47 +00:00
AMDGPU.td [AMDGPU][NFC] Rename ReserveTrapVGPRs -> ReserveRegs 2016-05-24 18:37:18 +00:00
AMDGPUAlwaysInlinePass.cpp Cloning: Clean up the interface to the CloneFunction function. 2016-05-10 20:23:24 +00:00
AMDGPUAnnotateKernelFeatures.cpp AMDGPU: Fix constantexpr addrspacecasts 2016-06-06 20:03:31 +00:00
AMDGPUAnnotateUniformValues.cpp Add optimization bisect opt-in calls for AMDGPU passes 2016-04-25 22:23:44 +00:00
AMDGPUAsmPrinter.cpp [AMDGPU][NFC] Rename ReserveTrapVGPRs -> ReserveRegs 2016-05-24 18:37:18 +00:00
AMDGPUAsmPrinter.h [AMDGPU] Move reserved vgpr count for trap handler usage to SIMachineFunctionInfo + minor commenting changes 2016-04-26 17:24:40 +00:00
AMDGPUCallingConv.td AMDGPU: Add a shader calling convention 2016-04-06 19:40:20 +00:00
AMDGPUCallLowering.cpp AMDGPU: Add skeleton GlobalIsel implementation 2016-04-14 19:09:28 +00:00
AMDGPUCallLowering.h AMDGPU: Add skeleton GlobalIsel implementation 2016-04-14 19:09:28 +00:00
AMDGPUFrameLowering.cpp
AMDGPUFrameLowering.h
AMDGPUInstrInfo.cpp
AMDGPUInstrInfo.h AMDGPU: Add SIWholeQuadMode pass 2016-03-21 20:28:33 +00:00
AMDGPUInstrInfo.td AMDGPU: Make CONST_DATA_PTR available to R600 2016-05-13 20:39:18 +00:00
AMDGPUInstructions.td AMDGPU: Fix trailing whitespace 2016-06-10 02:18:02 +00:00
AMDGPUIntrinsicInfo.cpp
AMDGPUIntrinsicInfo.h AMDGPU: R600 code splitting cleanup 2016-03-11 08:00:27 +00:00
AMDGPUIntrinsics.td
AMDGPUISelDAGToDAG.cpp AMDGPU/SI: Make sure to emit TargetConstant nodes when matching ds_*permute 2016-06-10 00:01:04 +00:00
AMDGPUISelLowering.cpp AMDGPU: Temporary fix for broken store combine 2016-06-02 19:00:55 +00:00
AMDGPUISelLowering.h AMDGPU: Remove custom load/store scalarization 2016-04-14 23:31:26 +00:00
AMDGPUMachineFunction.cpp Revert "AMDGPU/SI: Add amdgpu_kernel calling convention. Part 2." 2016-05-06 14:59:04 +00:00
AMDGPUMachineFunction.h Revert "AMDGPU/SI: Add amdgpu_kernel calling convention. Part 2." 2016-05-06 14:59:04 +00:00
AMDGPUMCInstLower.cpp AMDGPU/SI: Don't use fixup_si_rodata for scratch rsrc relocations 2016-06-10 19:26:38 +00:00
AMDGPUMCInstLower.h AMDGPU: R600 code splitting cleanup 2016-03-11 08:00:27 +00:00
AMDGPUOpenCLImageTypeLoweringPass.cpp [NFC] Header cleanup 2016-04-18 09:17:29 +00:00
AMDGPUPromoteAlloca.cpp AMDGPU: Fix promote alloca for pointer loads 2016-05-18 23:20:24 +00:00
AMDGPURegisterInfo.cpp
AMDGPURegisterInfo.h AMDGPU: R600 code splitting cleanup 2016-03-11 08:00:27 +00:00
AMDGPURegisterInfo.td
AMDGPUSubtarget.cpp AMDGPU: Fix crashes on unknown processor name 2016-06-02 18:37:16 +00:00
AMDGPUSubtarget.h AMDGPU: Fix i64 global cmpxchg 2016-06-09 23:42:48 +00:00
AMDGPUTargetMachine.cpp AMDGPU: Run verifer after insert waits pass 2016-06-09 23:19:14 +00:00
AMDGPUTargetMachine.h Delete Reloc::Default. 2016-05-18 22:04:49 +00:00
AMDGPUTargetObjectFile.cpp AMDGPU/SI: Add support for AMD code object version 2. 2016-05-05 17:03:33 +00:00
AMDGPUTargetObjectFile.h AMDGPU/SI: Add support for AMD code object version 2. 2016-05-05 17:03:33 +00:00
AMDGPUTargetTransformInfo.cpp AMDGPU: llvm.SI.fs.constant is a source of divergence 2016-05-02 17:37:01 +00:00
AMDGPUTargetTransformInfo.h AMDGPU: Other sizes of popcnt are fast 2016-05-18 16:10:19 +00:00
AMDILCFGStructurizer.cpp
AMDKernelCodeT.h
CaymanInstructions.td AMDGPU/EG,CM: Add instruction to read from constant AS (VTX2) 2016-05-13 20:39:16 +00:00
CIInstructions.td AMDGPU: Fix flat atomics 2016-06-09 23:42:54 +00:00
CMakeLists.txt [AMDGPU][NFC] Rename SIInsertNops -> SIDebuggerInsertNops 2016-05-10 18:33:41 +00:00
EvergreenInstructions.td AMDGPU/EG,CM: Add instruction to read from constant AS (VTX2) 2016-05-13 20:39:16 +00:00
GCNHazardRecognizer.cpp Silence unused variable warning; NFC. 2016-05-03 15:17:25 +00:00
GCNHazardRecognizer.h AMDGPU/SI: Use the hazard recognizer to break SMEM soft clauses 2016-05-02 17:39:06 +00:00
LLVMBuild.txt
Processors.td AMDGPU: Fix crashes on unknown processor name 2016-06-02 18:37:16 +00:00
R600ClauseMergePass.cpp Add optimization bisect opt-in calls for AMDGPU passes 2016-04-25 22:23:44 +00:00
R600ControlFlowFinalizer.cpp AMDGPU: Fix trailing whitespace 2016-06-10 02:18:02 +00:00
R600Defines.h AMDGPU: R600 code splitting cleanup 2016-03-11 08:00:27 +00:00
R600EmitClauseMarkers.cpp AMDGPU: Fix trailing whitespace 2016-06-10 02:18:02 +00:00
R600ExpandSpecialInstrs.cpp
R600InstrFormats.td
R600InstrInfo.cpp AMDGPU/R600: There are other uses for ALU_LITERAL besides Imm 2016-05-13 20:39:20 +00:00
R600InstrInfo.h [NFC] Header cleanup 2016-04-18 09:17:29 +00:00
R600Instructions.td AMDGPU/R600: Implement memory loads from constant AS 2016-05-13 20:39:29 +00:00
R600Intrinsics.td
R600ISelLowering.cpp AMDGPU: Cleanup load tests 2016-06-02 19:54:26 +00:00
R600ISelLowering.h Fix instance of -Winconsistent-missing-override in AMDGPU code 2016-05-02 19:45:10 +00:00
R600MachineFunctionInfo.cpp
R600MachineFunctionInfo.h [NFC] Header cleanup 2016-04-18 09:17:29 +00:00
R600MachineScheduler.cpp
R600MachineScheduler.h AMDGPU: R600 code splitting cleanup 2016-03-11 08:00:27 +00:00
R600OptimizeVectorRegisters.cpp Add optimization bisect opt-in calls for AMDGPU passes 2016-04-25 22:23:44 +00:00
R600Packetizer.cpp AMDGPU: Fix crashes on unknown processor name 2016-06-02 18:37:16 +00:00
R600RegisterInfo.cpp
R600RegisterInfo.h AMDGPU: R600 code splitting cleanup 2016-03-11 08:00:27 +00:00
R600RegisterInfo.td
R600Schedule.td AMDGPU: Fix trailing whitespace 2016-06-10 02:18:02 +00:00
R600TextureIntrinsicsReplacer.cpp
R700Instructions.td
SIAnnotateControlFlow.cpp AMDGPU: Fix trailing whitespace 2016-06-10 02:18:02 +00:00
SIDebuggerInsertNops.cpp AMDGPU: SIDebuggerInsertNops preserves CFG 2016-06-02 00:04:22 +00:00
SIDefines.h [AMDGPU] AsmParser: Support for sext() modifier in SDWA. Some code cleaning in AMDGPUOperand. 2016-06-10 09:57:59 +00:00
SIFixControlFlowLiveIntervals.cpp
SIFixSGPRCopies.cpp AMDGPU: Fix debug name of pass to better match 2016-04-21 18:21:54 +00:00
SIFoldOperands.cpp Add optimization bisect opt-in calls for AMDGPU passes 2016-04-25 22:23:44 +00:00
SIFrameLowering.cpp Soften assertion in AMDGPU emitPrologue. 2016-05-25 01:45:42 +00:00
SIFrameLowering.h
SIInsertWaits.cpp AMDGPU/SI: Use the hazard recognizer to break SMEM soft clauses 2016-05-02 17:39:06 +00:00
SIInstrFormats.td [TableGen] AsmMatcher: support for default values for optional operands 2016-05-06 11:31:17 +00:00
SIInstrInfo.cpp AMDGPU: Add function for getting instruction size 2016-06-06 20:10:33 +00:00
SIInstrInfo.h AMDGPU: Add function for getting instruction size 2016-06-06 20:10:33 +00:00
SIInstrInfo.td [AMDGPU] AsmParser: Support for sext() modifier in SDWA. Some code cleaning in AMDGPUOperand. 2016-06-10 09:57:59 +00:00
SIInstructions.td AMDGPU: Fix i64 global cmpxchg 2016-06-09 23:42:48 +00:00
SIIntrinsics.td Split IntrReadArgMem into IntrReadMem and IntrArgMemOnly 2016-04-21 17:48:02 +00:00
SIISelLowering.cpp AMDGPU: Fix trailing whitespace 2016-06-10 02:18:02 +00:00
SIISelLowering.h AMDGPU: Unify LowerGlobalAddress 2016-05-13 20:39:34 +00:00
SILoadStoreOptimizer.cpp Add optimization bisect opt-in calls for AMDGPU passes 2016-04-25 22:23:44 +00:00
SILowerControlFlow.cpp AMDGPU: Also look for s_cbranch_vccz 2016-05-19 18:20:25 +00:00
SILowerI1Copies.cpp
SIMachineFunctionInfo.cpp [AMDGPU][NFC] Rename ReserveTrapVGPRs -> ReserveRegs 2016-05-24 18:37:18 +00:00
SIMachineFunctionInfo.h [AMDGPU][NFC] Rename ReserveTrapVGPRs -> ReserveRegs 2016-05-24 18:37:18 +00:00
SIMachineScheduler.cpp AMDGPU/SI: Use common topological sort algorithm in SIScheduleDAGMI 2016-06-09 23:48:02 +00:00
SIMachineScheduler.h AMDGPU: R600 code splitting cleanup 2016-03-11 08:00:27 +00:00
SIRegisterInfo.cpp AMDGPU: Remove incorrect assertion 2016-06-09 23:19:08 +00:00
SIRegisterInfo.h AMDGPU/SI: Enable the post-ra scheduler 2016-04-30 00:23:06 +00:00
SIRegisterInfo.td AMDGPU: Define priorities for register classes 2016-05-21 03:55:07 +00:00
SISchedule.td AMDGPU/SI: Enable the post-ra scheduler 2016-04-30 00:23:06 +00:00
SIShrinkInstructions.cpp AMDGPU: Properly initialize SIShrinkInstructions 2016-06-09 23:18:47 +00:00
SITypeRewriter.cpp AMDGPU: Add a shader calling convention 2016-04-06 19:40:20 +00:00
SIWholeQuadMode.cpp AMDGPU: Add amdgpu-ps-wqm-outputs function attributes 2016-06-07 21:37:17 +00:00
VIInstrFormats.td [AMDGPU] Assembler: More tests for SDWA instructions. Fix for SDWA float modifiers. 2016-06-03 11:43:09 +00:00
VIInstructions.td AMDGPU: Fix trailing whitespace 2016-06-10 02:18:02 +00:00