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llvm-mirror/lib/Target/AArch64
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Marcin Koscielnicki 0919e582e6 [AArch64] [ARM] Make a target-independent llvm.thread.pointer intrinsic. 
Both AArch64 and ARM support llvm.<arch>.thread.pointer intrinsics that
just return the thread pointer.  I have a pending patch that does the same
for SystemZ (D19054), and there are many more targets that could benefit
from one.

This patch merges the ARM and AArch64 intrinsics into a single target
independent one that will also be used by subsequent targets.

Differential Revision: http://reviews.llvm.org/D19098

llvm-svn: 266818
2016-04-19 20:51:05 +00:00
..
AsmParser [NFC] Header cleanup 2016-04-18 09:17:29 +00:00
Disassembler Remove autoconf support 2016-01-26 21:29:08 +00:00
InstPrinter Remove autoconf support 2016-01-26 21:29:08 +00:00
MCTargetDesc [NFC] Header cleanup 2016-04-18 09:17:29 +00:00
TargetInfo Remove autoconf support 2016-01-26 21:29:08 +00:00
Utils [NFC] Header cleanup 2016-04-18 09:17:29 +00:00
AArch64.h AArch64: avoid clobbering SP for dead MOVimm pseudos. 2016-04-01 23:14:52 +00:00
AArch64.td AArch64: remove CRC feature from Cyclone. 2016-02-24 18:10:17 +00:00
AArch64A53Fix835769.cpp [NFC] Header cleanup 2016-04-18 09:17:29 +00:00
AArch64A57FPLoadBalancing.cpp [NFC] Header cleanup 2016-04-18 09:17:29 +00:00
AArch64AddressTypePromotion.cpp Simplify some boolean conditional return statements in AArch64. 2016-02-29 22:50:49 +00:00
AArch64AdvSIMDScalarPass.cpp AArch64: Remove implicit ilist iterator conversions, NFC 2015-10-13 20:02:15 +00:00
AArch64AsmPrinter.cpp
AArch64BranchRelaxation.cpp [AArch64] Fix typo. NFC. 2016-03-25 14:37:43 +00:00
AArch64CallingConvention.h Replace uint16_t with the MCPhysReg typedef in many places. A lot of physical register arrays already use this typedef. 2015-12-05 07:13:35 +00:00
AArch64CallingConvention.td AArch64: Use a callee save registers for swiftself parameters 2016-04-13 21:43:16 +00:00
AArch64CallLowering.cpp [GlobalISel] Coding style and whitespace fixes 2016-04-14 17:23:33 +00:00
AArch64CallLowering.h [GlobalISel] Coding style and whitespace fixes 2016-04-14 17:23:33 +00:00
AArch64CleanupLocalDynamicTLSPass.cpp Revert "CodeGen: MachineInstr::getIterator() => getInstrIterator(), NFC" 2016-02-22 20:49:58 +00:00
AArch64CollectLOH.cpp Add MachineFunctionProperty checks for AllVRegsAllocated for target passes 2016-04-04 17:09:25 +00:00
AArch64ConditionalCompares.cpp [NFC] Header cleanup 2016-04-18 09:17:29 +00:00
AArch64ConditionOptimizer.cpp [NFC] Header cleanup 2016-04-18 09:17:29 +00:00
AArch64DeadRegisterDefinitionsPass.cpp AArch64: don't create instructions that write to xzr/wzr twice. 2016-04-13 16:25:39 +00:00
AArch64ExpandPseudoInsts.cpp AArch64: expand cmpxchg after regalloc at -O0. 2016-04-14 17:03:29 +00:00
AArch64FastISel.cpp [NFC] Header cleanup 2016-04-18 09:17:29 +00:00
AArch64FrameLowering.cpp [AArch64] Add MMOs to callee-save load/store instructions. 2016-04-15 15:16:19 +00:00
AArch64FrameLowering.h Change eliminateCallFramePseudoInstr() to return an iterator 2016-03-31 18:33:38 +00:00
AArch64InstrAtomics.td AArch64: expand cmpxchg after regalloc at -O0. 2016-04-14 17:03:29 +00:00
AArch64InstrFormats.td AArch64: Add missing schedinfo, check completeness for cyclone 2016-03-01 21:20:31 +00:00
AArch64InstrInfo.cpp [AArch64] Add load/store pair instructions to getMemOpBaseRegImmOfsWidth(). 2016-04-15 18:09:10 +00:00
AArch64InstrInfo.h [MachineScheduler]Add support for store clustering 2016-04-15 14:58:38 +00:00
AArch64InstrInfo.td AArch64: remove pseudo-instructions used only for their patterns. 2016-03-10 18:46:12 +00:00
AArch64ISelDAGToDAG.cpp AArch64: expand cmpxchg after regalloc at -O0. 2016-04-14 17:03:29 +00:00
AArch64ISelLowering.cpp [AArch64] [ARM] Make a target-independent llvm.thread.pointer intrinsic. 2016-04-19 20:51:05 +00:00
AArch64ISelLowering.h Use MVT instead of EVT to remove a bunch of unnecessary calls to getSimpleVT. 2016-04-15 06:20:21 +00:00
AArch64LoadStoreOptimizer.cpp Add MachineFunctionProperty checks for AllVRegsAllocated for target passes 2016-04-04 17:09:25 +00:00
AArch64MachineFunctionInfo.h [AArch64] Break the dependency between FP and SP when possible. 2016-03-14 18:17:41 +00:00
AArch64MCInstLower.cpp
AArch64MCInstLower.h
AArch64PBQPRegAlloc.cpp CodeGen: Take MachineInstr& in SlotIndexes and LiveIntervals, NFC 2016-02-27 06:40:41 +00:00
AArch64PBQPRegAlloc.h
AArch64PerfectShuffle.h
AArch64PromoteConstant.cpp Fix -Wdocumentation warnings from r263853 2016-03-21 22:13:44 +00:00
AArch64RedundantCopyElimination.cpp Add MachineFunctionProperty checks for AllVRegsAllocated for target passes 2016-04-04 17:09:25 +00:00
AArch64RegisterBankInfo.cpp [AArch64] Fix a typo in the register class to register bank mapping. 2016-04-07 23:10:14 +00:00
AArch64RegisterBankInfo.h [AArch64] Teach RegisterBankInfo about the CC register bank. 2016-04-07 00:39:29 +00:00
AArch64RegisterInfo.cpp [NFC] Header cleanup 2016-04-18 09:17:29 +00:00
AArch64RegisterInfo.h CXX_FAST_TLS calling convention: performance improvement for AArch64. 2015-12-16 21:04:19 +00:00
AArch64RegisterInfo.td [AArch64] Add ARMv8.2-A FP16 vector instructions 2015-12-08 12:16:10 +00:00
AArch64SchedA53.td AArch64: Reenable CompleteModel for A53, A57 and Kryo models 2016-03-01 21:55:35 +00:00
AArch64SchedA57.td AArch64: Reenable CompleteModel for A53, A57 and Kryo models 2016-03-01 21:55:35 +00:00
AArch64SchedA57WriteRes.td
AArch64SchedCyclone.td AArch64: Add missing schedinfo, check completeness for cyclone 2016-03-01 21:20:31 +00:00
AArch64SchedKryo.td AArch64: Reenable CompleteModel for A53, A57 and Kryo models 2016-03-01 21:55:35 +00:00
AArch64SchedKryoDetails.td [AArch64] Add support for Qualcomm Kryo CPU. 2016-02-12 15:51:51 +00:00
AArch64SchedM1.td [AArch64] Fuse AES{D,E}/AESMC for Exynos M1. (NFC) 2016-04-12 22:42:36 +00:00
AArch64Schedule.td AArch64: Add missing schedinfo, check completeness for cyclone 2016-03-01 21:20:31 +00:00
AArch64SelectionDAGInfo.cpp
AArch64SelectionDAGInfo.h Rename TargetSelectionDAGInfo into SelectionDAGTargetInfo and move it to CodeGen/ 2016-01-27 16:32:26 +00:00
AArch64StorePairSuppress.cpp [TII] Allow getMemOpBaseRegImmOfs() to accept negative offsets. NFC. 2016-03-09 16:00:35 +00:00
AArch64Subtarget.cpp [NFC] Header cleanup 2016-04-18 09:17:29 +00:00
AArch64Subtarget.h [GlobalISel] Move GISelAccessor class into public headers 2016-04-14 17:45:38 +00:00
AArch64TargetMachine.cpp [GlobalISel] Move GISelAccessor class into public headers 2016-04-14 17:45:38 +00:00
AArch64TargetMachine.h
AArch64TargetObjectFile.cpp
AArch64TargetObjectFile.h
AArch64TargetTransformInfo.cpp [LoopDataPrefetch] Centralize the tuning cl::opts under the pass 2016-03-29 23:45:52 +00:00
AArch64TargetTransformInfo.h [LoopDataPrefetch] Add TTI to limit the number of iterations to prefetch ahead 2016-03-18 00:27:43 +00:00
CMakeLists.txt [AArch64][CallLowering] Do not build the API if GlobalISel is not built. 2016-04-07 20:47:51 +00:00
LLVMBuild.txt [AArch64] Plug the beginning of the GlobalISel pipeline. 2016-02-11 19:35:06 +00:00