Sam Kolton 0ab0b61c0c [AMDGPU] Disassembler: fix for disaasembling v_mac_f32/16_dpp/sdwa ... Summary: Real instruction should copy constraints from real instruction. This allows auto-generated disassembler to correctly process tied operands. Reviewers: nhaustov, vpykhtin, tstellarAMD Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, tony-tye Differential Revision: https://reviews.llvm.org/D27847 llvm-svn: 290336		2016-12-22 11:30:48 +00:00
..
dpp_vi.txt	[AMDGPU] Disassembler: fix for disaasembling v_mac_f32/16_dpp/sdwa	2016-12-22 11:30:48 +00:00
ds_vi.txt	[AMDGPU][mc] Fix ds_min/max[_rtn]_f32 - extra source operand removed.	2016-10-21 14:49:22 +00:00
flat_vi.txt
lit.local.cfg
literal16_vi.txt	AMDGPU: Fix handling of 16-bit immediates	2016-12-10 00:39:12 +00:00
mov.txt
mubuf_vi.txt	[AMDGPU][mc] Add support for buffer_load_dwordx3, buffer_store_dwordx3.	2016-10-07 15:53:16 +00:00
nop.txt
sdwa_vi.txt	[AMDGPU] Disassembler: fix for disaasembling v_mac_f32/16_dpp/sdwa	2016-12-22 11:30:48 +00:00
smem_vi.txt	[AMDGPU] Disassembler: fix s_buffer_store_dword instructions	2016-12-05 09:58:51 +00:00
smrd_vi.txt	[AMDGPU][MC][gfx8] Support 20-bit immediate offset in SMEM instructions.	2016-10-31 16:07:39 +00:00
sop1_vi.txt
sop2_vi.txt
sopc_vi.txt
sopk_vi.txt
sopp_vi.txt
trap_vi.txt
vintrp.txt	AMDGPU: Change vintrp printing	2016-12-14 16:36:12 +00:00
vop1_vi.txt
vop1.txt	AMDGPU: Fix handling of 16-bit immediates	2016-12-10 00:39:12 +00:00
vop2_vi.txt	AMDGPU: Fix name for v_ashrrev_i16	2016-12-16 17:40:11 +00:00
vop3_vi.txt
vopc_vi.txt