David Greene e14c99cea5 [AArch64] Create proper memoperand for multi-vector stores ... Include all of the store's source vector operands when creating the MachineMemOperand. Previously, we were missing the first operand, making the store size seem smaller than it really is. Differential Revision: https://reviews.llvm.org/D52816 llvm-svn: 345315		2018-10-25 21:10:39 +00:00
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AArch64	[AArch64] Create proper memoperand for multi-vector stores	2018-10-25 21:10:39 +00:00
AMDGPU	[AMDGPU] Defined gfx909 Raven Ridge 2	2018-10-24 08:14:07 +00:00
ARC
ARM	[ARM] Regenerate vdup tests	2018-10-25 15:33:47 +00:00
AVR
BPF
Generic
Hexagon	Reapply "[MachineCopyPropagation] Reimplement CopyTracker in terms of register units"	2018-10-22 19:51:31 +00:00
Inputs
Lanai
Mips	[MIPS GlobalISel] Legalize constants	2018-10-17 10:30:03 +00:00
MIR
MSP430
Nios2
NVPTX
PowerPC	[Power9] Add __float128 support in the backend for bitcast to a i128	2018-10-23 17:11:36 +00:00
RISCV	[RISCV] Eliminate unnecessary masking of promoted shift amounts	2018-10-12 23:18:52 +00:00
SPARC
SystemZ	[NFC] Rename minnan and maxnan to minimum and maximum	2018-10-24 22:49:55 +00:00
Thumb
Thumb2	CGP: Clear data structures at the end of a loop iteration instead of the beginning.	2018-10-23 21:23:18 +00:00
WebAssembly	[WebAssembly] Use target-independent saturating add	2018-10-25 19:06:13 +00:00
WinCFGuard
WinEH
X86	[X86] Add some non-AVX512VL command lines to the *vl-vec-test-testn.ll tests.	2018-10-25 18:23:48 +00:00
XCore