2014-05-24 14:50:23 +02:00
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//===--- AArch64Subtarget.h - Define Subtarget for the AArch64 -*- C++ -*--===//
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2014-03-29 11:18:08 +01:00
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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2014-05-24 14:50:23 +02:00
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// This file declares the AArch64 specific subclass of TargetSubtarget.
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2014-03-29 11:18:08 +01:00
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//
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//===----------------------------------------------------------------------===//
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2014-08-13 18:26:38 +02:00
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#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
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#define LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
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2014-03-29 11:18:08 +01:00
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2014-06-10 19:44:12 +02:00
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#include "AArch64FrameLowering.h"
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2014-06-11 01:26:45 +02:00
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#include "AArch64ISelLowering.h"
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2014-07-25 13:42:14 +02:00
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#include "AArch64InstrInfo.h"
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2014-05-24 14:50:23 +02:00
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#include "AArch64RegisterInfo.h"
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2014-06-10 20:21:53 +02:00
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#include "AArch64SelectionDAGInfo.h"
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2016-04-14 19:45:38 +02:00
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#include "llvm/CodeGen/GlobalISel/GISelAccessor.h"
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2014-06-10 20:06:23 +02:00
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#include "llvm/IR/DataLayout.h"
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2014-06-10 19:44:12 +02:00
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#include "llvm/Target/TargetSubtargetInfo.h"
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2014-03-29 11:18:08 +01:00
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#include <string>
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#define GET_SUBTARGETINFO_HEADER
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2014-05-24 14:50:23 +02:00
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#include "AArch64GenSubtargetInfo.inc"
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2014-03-29 11:18:08 +01:00
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namespace llvm {
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class GlobalValue;
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class StringRef;
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2015-06-10 14:11:26 +02:00
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class Triple;
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2014-03-29 11:18:08 +01:00
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2016-07-27 16:31:46 +02:00
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class AArch64Subtarget final : public AArch64GenSubtargetInfo {
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2016-06-02 20:03:53 +02:00
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public:
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enum ARMProcFamilyEnum : uint8_t {
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2016-01-05 13:51:59 +01:00
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Others,
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CortexA35,
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CortexA53,
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CortexA57,
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[AArch64] Restore codegen for AArch64 Cortex-A72/A73 after NFCI
Summary:
Code generation for Cortex-A72/Cortex-A73 was accidentally changed
by r271555, which was a NFCI. The isCortexA57() predicate was not true
for Cortex-A72/Cortex-A73 before r271555 (since it was checking the CPU
string). Because Cortex-A72/Cortex-A73 inherit all features from Cortex-A57,
all decisions previously guarded by isCortexA57() are now taken.
This change restores the behaviour before r271555 by adding separate
ProcA72/ProcA73, which have the required features to preserve code
generation.
Reviewers: kristof.beyls, aadg, mcrosier, rengolin
Subscribers: mcrosier, llvm-commits, aemerson, t.p.northover, MatzeB, rengolin
Differential Revision: http://reviews.llvm.org/D21182
llvm-svn: 273277
2016-06-21 17:53:54 +02:00
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CortexA72,
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CortexA73,
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2016-01-05 13:51:59 +01:00
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Cyclone,
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2016-02-12 16:51:51 +01:00
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ExynosM1,
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2016-11-15 22:34:12 +01:00
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Falkor,
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2016-06-20 13:13:31 +02:00
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Kryo,
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Vulcan
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2016-01-05 13:51:59 +01:00
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};
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2014-04-14 19:38:00 +02:00
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2016-06-02 20:03:53 +02:00
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protected:
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2014-04-14 19:38:00 +02:00
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/// ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
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2016-05-28 00:14:09 +02:00
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ARMProcFamilyEnum ARMProcFamily = Others;
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2014-04-14 19:38:00 +02:00
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2016-05-28 00:14:09 +02:00
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bool HasV8_1aOps = false;
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bool HasV8_2aOps = false;
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2015-04-01 16:49:29 +02:00
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2016-05-28 00:14:09 +02:00
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bool HasFPARMv8 = false;
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bool HasNEON = false;
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bool HasCrypto = false;
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bool HasCRC = false;
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2016-11-30 23:25:24 +01:00
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bool HasLSE = false;
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2016-06-03 16:03:27 +02:00
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bool HasRAS = false;
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2016-05-28 00:14:09 +02:00
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bool HasPerfMon = false;
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bool HasFullFP16 = false;
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bool HasSPE = false;
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2014-04-14 19:38:00 +02:00
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2014-03-29 11:18:08 +01:00
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// HasZeroCycleRegMove - Has zero-cycle register mov instructions.
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2016-05-28 00:14:09 +02:00
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bool HasZeroCycleRegMove = false;
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2014-03-29 11:18:08 +01:00
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// HasZeroCycleZeroing - Has zero-cycle zeroing instructions.
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2016-05-28 00:14:09 +02:00
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bool HasZeroCycleZeroing = false;
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2014-03-29 11:18:08 +01:00
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2015-07-29 16:17:26 +02:00
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// StrictAlign - Disallow unaligned memory accesses.
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2016-05-28 00:14:09 +02:00
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bool StrictAlign = false;
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2016-06-02 20:03:53 +02:00
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bool UseAA = false;
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bool PredictableSelectIsExpensive = false;
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bool BalanceFPOps = false;
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bool CustomAsCheapAsMove = false;
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bool UsePostRAScheduler = false;
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bool Misaligned128StoreIsSlow = false;
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bool AvoidQuadLdStPairs = false;
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bool UseAlternateSExtLoadCVTF32Pattern = false;
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2016-10-04 21:28:21 +02:00
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bool HasArithmeticBccFusion = false;
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bool HasArithmeticCbzFusion = false;
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2016-06-02 20:03:53 +02:00
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bool DisableLatencySchedHeuristic = false;
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2016-10-24 18:14:58 +02:00
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bool UseRSqrt = false;
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2016-06-02 20:03:53 +02:00
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uint8_t MaxInterleaveFactor = 2;
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uint8_t VectorInsertExtractBaseCost = 3;
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uint16_t CacheLineSize = 0;
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uint16_t PrefetchDistance = 0;
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uint16_t MinPrefetchStride = 1;
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unsigned MaxPrefetchIterationsAhead = UINT_MAX;
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2016-06-10 18:00:18 +02:00
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unsigned PrefFunctionAlignment = 0;
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unsigned PrefLoopAlignment = 0;
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2016-09-26 17:32:33 +02:00
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unsigned MaxJumpTableSize = 0;
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2015-07-29 16:17:26 +02:00
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2015-07-25 02:18:31 +02:00
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// ReserveX18 - X18 is not available as a general purpose register.
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bool ReserveX18;
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2015-01-26 20:03:15 +01:00
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bool IsLittle;
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2014-03-29 11:18:08 +01:00
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/// TargetTriple - What processor and OS we're targeting.
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Triple TargetTriple;
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2014-06-10 19:44:12 +02:00
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AArch64FrameLowering FrameLowering;
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2014-06-11 00:57:25 +02:00
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AArch64InstrInfo InstrInfo;
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2014-06-10 20:21:53 +02:00
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AArch64SelectionDAGInfo TSInfo;
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2014-06-11 02:46:34 +02:00
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AArch64TargetLowering TLInfo;
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2016-04-06 19:26:03 +02:00
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/// Gather the accessor points to GlobalISel-related APIs.
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/// This is used to avoid ifndefs spreading around while GISel is
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/// an optional library.
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2016-04-14 19:45:38 +02:00
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std::unique_ptr<GISelAccessor> GISel;
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2016-02-16 20:26:02 +01:00
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2014-06-11 02:46:34 +02:00
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private:
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/// initializeSubtargetDependencies - Initializes using CPUString and the
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/// passed in feature string so that we can use initializer lists for
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/// subtarget initialization.
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2016-10-03 22:17:02 +02:00
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AArch64Subtarget &initializeSubtargetDependencies(StringRef FS,
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StringRef CPUString);
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2014-06-10 19:44:12 +02:00
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2016-06-02 20:03:53 +02:00
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/// Initialize properties based on the selected processor family.
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void initializeProperties();
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2014-03-29 11:18:08 +01:00
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public:
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/// This constructor initializes the data members to match that
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/// of the specified triple.
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2015-06-10 14:11:26 +02:00
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AArch64Subtarget(const Triple &TT, const std::string &CPU,
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2015-03-18 21:37:30 +01:00
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const std::string &FS, const TargetMachine &TM,
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2014-10-03 02:42:41 +02:00
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bool LittleEndian);
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2014-03-29 11:18:08 +01:00
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2016-04-06 19:26:03 +02:00
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/// This object will take onwership of \p GISelAccessor.
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2016-04-14 19:45:38 +02:00
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void setGISelAccessor(GISelAccessor &GISel) {
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this->GISel.reset(&GISel);
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2016-04-06 19:26:03 +02:00
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}
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2014-08-04 23:25:23 +02:00
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const AArch64SelectionDAGInfo *getSelectionDAGInfo() const override {
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return &TSInfo;
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}
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const AArch64FrameLowering *getFrameLowering() const override {
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2014-06-10 19:44:12 +02:00
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return &FrameLowering;
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}
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2014-08-04 23:25:23 +02:00
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const AArch64TargetLowering *getTargetLowering() const override {
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2014-06-11 02:46:34 +02:00
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return &TLInfo;
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2014-06-11 01:26:45 +02:00
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}
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2014-08-04 23:25:23 +02:00
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const AArch64InstrInfo *getInstrInfo() const override { return &InstrInfo; }
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2015-03-18 21:37:30 +01:00
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const AArch64RegisterInfo *getRegisterInfo() const override {
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return &getInstrInfo()->getRegisterInfo();
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}
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2016-02-16 20:26:02 +01:00
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const CallLowering *getCallLowering() const override;
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2016-07-27 16:31:55 +02:00
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const InstructionSelector *getInstructionSelector() const override;
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2016-10-15 00:18:18 +02:00
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const LegalizerInfo *getLegalizerInfo() const override;
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2016-04-06 19:26:03 +02:00
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const RegisterBankInfo *getRegBankInfo() const override;
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2015-03-12 03:04:46 +01:00
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const Triple &getTargetTriple() const { return TargetTriple; }
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2014-03-30 09:25:18 +02:00
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bool enableMachineScheduler() const override { return true; }
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2015-06-13 05:42:16 +02:00
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bool enablePostRAScheduler() const override {
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2016-06-02 20:03:53 +02:00
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return UsePostRAScheduler;
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}
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/// Returns ARM processor family.
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/// Avoid this function! CPU specifics should be kept local to this class
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/// and preferably modeled with SubtargetFeatures or properties in
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/// initializeProperties().
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ARMProcFamilyEnum getProcFamily() const {
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return ARMProcFamily;
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2014-09-12 19:40:39 +02:00
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}
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2014-03-29 11:18:08 +01:00
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2015-04-01 16:49:29 +02:00
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bool hasV8_1aOps() const { return HasV8_1aOps; }
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2015-11-26 16:23:32 +01:00
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bool hasV8_2aOps() const { return HasV8_2aOps; }
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2015-04-01 16:49:29 +02:00
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2014-03-29 11:18:08 +01:00
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bool hasZeroCycleRegMove() const { return HasZeroCycleRegMove; }
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bool hasZeroCycleZeroing() const { return HasZeroCycleZeroing; }
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2015-07-29 16:17:26 +02:00
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bool requiresStrictAlign() const { return StrictAlign; }
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2016-11-17 06:15:37 +01:00
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bool isXRaySupported() const override { return true; }
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2015-07-25 02:18:31 +02:00
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bool isX18Reserved() const { return ReserveX18; }
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2014-04-14 19:38:00 +02:00
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bool hasFPARMv8() const { return HasFPARMv8; }
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bool hasNEON() const { return HasNEON; }
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bool hasCrypto() const { return HasCrypto; }
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2014-04-25 11:25:42 +02:00
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bool hasCRC() const { return HasCRC; }
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2016-11-30 23:25:24 +01:00
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bool hasLSE() const { return HasLSE; }
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2016-06-03 16:03:27 +02:00
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bool hasRAS() const { return HasRAS; }
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2016-06-02 20:03:53 +02:00
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bool balanceFPOps() const { return BalanceFPOps; }
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bool predictableSelectIsExpensive() const {
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return PredictableSelectIsExpensive;
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}
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bool hasCustomCheapAsMoveHandling() const { return CustomAsCheapAsMove; }
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bool isMisaligned128StoreSlow() const { return Misaligned128StoreIsSlow; }
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bool avoidQuadLdStPairs() const { return AvoidQuadLdStPairs; }
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bool useAlternateSExtLoadCVTF32Pattern() const {
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return UseAlternateSExtLoadCVTF32Pattern;
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}
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2016-10-04 21:28:21 +02:00
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bool hasArithmeticBccFusion() const { return HasArithmeticBccFusion; }
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bool hasArithmeticCbzFusion() const { return HasArithmeticCbzFusion; }
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2016-10-24 18:14:58 +02:00
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bool useRSqrt() const { return UseRSqrt; }
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2016-06-02 20:03:53 +02:00
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unsigned getMaxInterleaveFactor() const { return MaxInterleaveFactor; }
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unsigned getVectorInsertExtractBaseCost() const {
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return VectorInsertExtractBaseCost;
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}
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unsigned getCacheLineSize() const { return CacheLineSize; }
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unsigned getPrefetchDistance() const { return PrefetchDistance; }
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unsigned getMinPrefetchStride() const { return MinPrefetchStride; }
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unsigned getMaxPrefetchIterationsAhead() const {
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return MaxPrefetchIterationsAhead;
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}
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2016-06-10 18:00:18 +02:00
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unsigned getPrefFunctionAlignment() const { return PrefFunctionAlignment; }
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unsigned getPrefLoopAlignment() const { return PrefLoopAlignment; }
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2016-06-02 20:03:53 +02:00
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2016-09-26 17:32:33 +02:00
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unsigned getMaximumJumpTableSize() const { return MaxJumpTableSize; }
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2015-11-10 01:44:23 +01:00
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/// CPU has TBI (top byte of addresses is ignored during HW address
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/// translation) and OS enables it.
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bool supportsAddressTopByteIgnored() const;
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2015-09-01 18:23:45 +02:00
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bool hasPerfMon() const { return HasPerfMon; }
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2015-11-26 16:23:32 +01:00
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bool hasFullFP16() const { return HasFullFP16; }
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2015-12-01 11:48:51 +01:00
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bool hasSPE() const { return HasSPE; }
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2014-04-14 19:38:00 +02:00
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2015-01-26 20:03:15 +01:00
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bool isLittleEndian() const { return IsLittle; }
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2014-04-23 12:26:40 +02:00
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2014-03-29 11:18:08 +01:00
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bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
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2014-08-06 18:56:58 +02:00
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bool isTargetIOS() const { return TargetTriple.isiOS(); }
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bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
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bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
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2015-10-08 23:21:24 +02:00
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bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
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2014-03-29 11:18:08 +01:00
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2014-08-06 18:56:58 +02:00
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bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
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2014-03-29 11:18:08 +01:00
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bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
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bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
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2016-06-02 20:03:53 +02:00
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bool useAA() const override { return UseAA; }
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2014-09-08 16:31:49 +02:00
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2014-03-29 11:18:08 +01:00
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/// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
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/// that still makes it profitable to inline the call.
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unsigned getMaxInlineSizeThreshold() const { return 64; }
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/// ParseSubtargetFeatures - Parses features string setting specified
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/// subtarget options. Definition of function is auto generated by tblgen.
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void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
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/// ClassifyGlobalReference - Find the target operand flags that describe
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/// how a global value should be referenced for the current subtarget.
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unsigned char ClassifyGlobalReference(const GlobalValue *GV,
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const TargetMachine &TM) const;
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/// This function returns the name of a function which has an interface
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/// like the non-standard bzero function, if such a function exists on
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/// the current subtarget and it is considered prefereable over
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/// memset with zero passed as the second argument. Otherwise it
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/// returns null.
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const char *getBZeroEntry() const;
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2016-07-01 02:23:27 +02:00
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void overrideSchedPolicy(MachineSchedPolicy &Policy,
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2014-04-29 09:58:25 +02:00
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unsigned NumRegionInstrs) const override;
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2014-05-22 01:40:26 +02:00
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bool enableEarlyIfConversion() const override;
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2014-10-09 20:20:51 +02:00
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std::unique_ptr<PBQPRAConstraint> getCustomPBQPConstraints() const override;
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2014-03-29 11:18:08 +01:00
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};
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2015-06-23 11:49:53 +02:00
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} // End llvm namespace
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2014-03-29 11:18:08 +01:00
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2014-08-13 18:26:38 +02:00
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#endif
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