2014-05-24 14:50:23 +02:00
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//===--- AArch64Subtarget.h - Define Subtarget for the AArch64 -*- C++ -*--===//
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2014-03-29 11:18:08 +01:00
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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2014-05-24 14:50:23 +02:00
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// This file declares the AArch64 specific subclass of TargetSubtarget.
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2014-03-29 11:18:08 +01:00
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//
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//===----------------------------------------------------------------------===//
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2014-08-13 18:26:38 +02:00
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#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
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#define LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
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2014-03-29 11:18:08 +01:00
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2014-06-10 19:44:12 +02:00
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#include "AArch64FrameLowering.h"
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2014-06-11 01:26:45 +02:00
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#include "AArch64ISelLowering.h"
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2014-07-25 13:42:14 +02:00
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#include "AArch64InstrInfo.h"
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2014-05-24 14:50:23 +02:00
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#include "AArch64RegisterInfo.h"
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2014-06-10 20:21:53 +02:00
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#include "AArch64SelectionDAGInfo.h"
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2017-08-16 00:31:51 +02:00
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#include "llvm/CodeGen/GlobalISel/CallLowering.h"
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#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
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#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
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#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
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2017-11-17 02:07:10 +01:00
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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2014-06-10 20:06:23 +02:00
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#include "llvm/IR/DataLayout.h"
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2014-03-29 11:18:08 +01:00
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#include <string>
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#define GET_SUBTARGETINFO_HEADER
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2014-05-24 14:50:23 +02:00
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#include "AArch64GenSubtargetInfo.inc"
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2014-03-29 11:18:08 +01:00
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namespace llvm {
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class GlobalValue;
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class StringRef;
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2015-06-10 14:11:26 +02:00
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class Triple;
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2014-03-29 11:18:08 +01:00
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2016-07-27 16:31:46 +02:00
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class AArch64Subtarget final : public AArch64GenSubtargetInfo {
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2016-06-02 20:03:53 +02:00
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public:
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enum ARMProcFamilyEnum : uint8_t {
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2016-01-05 13:51:59 +01:00
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Others,
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CortexA35,
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CortexA53,
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2017-08-21 10:43:06 +02:00
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CortexA55,
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2016-01-05 13:51:59 +01:00
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CortexA57,
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[AArch64] Restore codegen for AArch64 Cortex-A72/A73 after NFCI
Summary:
Code generation for Cortex-A72/Cortex-A73 was accidentally changed
by r271555, which was a NFCI. The isCortexA57() predicate was not true
for Cortex-A72/Cortex-A73 before r271555 (since it was checking the CPU
string). Because Cortex-A72/Cortex-A73 inherit all features from Cortex-A57,
all decisions previously guarded by isCortexA57() are now taken.
This change restores the behaviour before r271555 by adding separate
ProcA72/ProcA73, which have the required features to preserve code
generation.
Reviewers: kristof.beyls, aadg, mcrosier, rengolin
Subscribers: mcrosier, llvm-commits, aemerson, t.p.northover, MatzeB, rengolin
Differential Revision: http://reviews.llvm.org/D21182
llvm-svn: 273277
2016-06-21 17:53:54 +02:00
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CortexA72,
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CortexA73,
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2017-08-21 10:43:06 +02:00
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CortexA75,
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2016-01-05 13:51:59 +01:00
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Cyclone,
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2016-02-12 16:51:51 +01:00
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ExynosM1,
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2018-01-30 16:40:16 +01:00
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ExynosM3,
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2016-11-15 22:34:12 +01:00
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Falkor,
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2016-06-20 13:13:31 +02:00
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Kryo,
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2017-09-25 16:05:00 +02:00
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Saphira,
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2017-03-07 20:42:40 +01:00
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ThunderX2T99,
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2017-02-17 19:34:24 +01:00
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ThunderX,
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ThunderXT81,
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ThunderXT83,
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2018-11-09 20:32:08 +01:00
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ThunderXT88,
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TSV110
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2016-01-05 13:51:59 +01:00
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};
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2014-04-14 19:38:00 +02:00
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2016-06-02 20:03:53 +02:00
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protected:
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2014-04-14 19:38:00 +02:00
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/// ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
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2016-05-28 00:14:09 +02:00
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ARMProcFamilyEnum ARMProcFamily = Others;
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2014-04-14 19:38:00 +02:00
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2016-05-28 00:14:09 +02:00
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bool HasV8_1aOps = false;
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bool HasV8_2aOps = false;
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2017-08-10 11:41:00 +02:00
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bool HasV8_3aOps = false;
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[ARM][AArch64] Armv8.4-A Enablement
Initial patch adding assembly support for Armv8.4-A.
Besides adding v8.4 as a supported architecture to the usual places, this also
adds target features for the different crypto algorithms. Armv8.4-A introduced
new crypto algorithms, made them optional, and allows different combinations:
- none of the v8.4 crypto functions are supported, which is independent of the
implementation of the Armv8.0 SHA1 and SHA2 instructions.
- the v8.4 SHA512 and SHA3 support is implemented, in this case the Armv8.0
SHA1 and SHA2 instructions must also be implemented.
- the v8.4 SM3 and SM4 support is implemented, which is independent of the
implementation of the Armv8.0 SHA1 and SHA2 instructions.
- all of the v8.4 crypto functions are supported, in this case the Armv8.0 SHA1
and SHA2 instructions must also be implemented.
The v8.4 crypto instructions are added to AArch64 only, and not AArch32,
and are made optional extensions to Armv8.2-A.
The user-facing Clang options will map on these new target features, their
naming will be compatible with GCC and added in follow-up patches.
The Armv8.4-A instruction sets can be downloaded here:
https://developer.arm.com/products/architecture/a-profile/exploration-tools
Differential Revision: https://reviews.llvm.org/D48625
llvm-svn: 335953
2018-06-29 10:43:19 +02:00
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bool HasV8_4aOps = false;
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2018-09-26 14:48:21 +02:00
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bool HasV8_5aOps = false;
|
2015-04-01 16:49:29 +02:00
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2016-05-28 00:14:09 +02:00
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bool HasFPARMv8 = false;
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bool HasNEON = false;
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bool HasCrypto = false;
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2017-08-09 16:59:54 +02:00
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bool HasDotProd = false;
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2016-05-28 00:14:09 +02:00
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bool HasCRC = false;
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2016-11-30 23:25:24 +01:00
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bool HasLSE = false;
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2016-06-03 16:03:27 +02:00
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bool HasRAS = false;
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2017-01-16 17:28:43 +01:00
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bool HasRDM = false;
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2016-05-28 00:14:09 +02:00
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bool HasPerfMon = false;
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bool HasFullFP16 = false;
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2018-08-17 13:29:49 +02:00
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bool HasFP16FML = false;
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2016-05-28 00:14:09 +02:00
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bool HasSPE = false;
|
[ARM][AArch64] Armv8.4-A Enablement
Initial patch adding assembly support for Armv8.4-A.
Besides adding v8.4 as a supported architecture to the usual places, this also
adds target features for the different crypto algorithms. Armv8.4-A introduced
new crypto algorithms, made them optional, and allows different combinations:
- none of the v8.4 crypto functions are supported, which is independent of the
implementation of the Armv8.0 SHA1 and SHA2 instructions.
- the v8.4 SHA512 and SHA3 support is implemented, in this case the Armv8.0
SHA1 and SHA2 instructions must also be implemented.
- the v8.4 SM3 and SM4 support is implemented, which is independent of the
implementation of the Armv8.0 SHA1 and SHA2 instructions.
- all of the v8.4 crypto functions are supported, in this case the Armv8.0 SHA1
and SHA2 instructions must also be implemented.
The v8.4 crypto instructions are added to AArch64 only, and not AArch32,
and are made optional extensions to Armv8.2-A.
The user-facing Clang options will map on these new target features, their
naming will be compatible with GCC and added in follow-up patches.
The Armv8.4-A instruction sets can be downloaded here:
https://developer.arm.com/products/architecture/a-profile/exploration-tools
Differential Revision: https://reviews.llvm.org/D48625
llvm-svn: 335953
2018-06-29 10:43:19 +02:00
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// ARMv8.4 Crypto extensions
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bool HasSM4 = true;
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bool HasSHA3 = true;
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bool HasSHA2 = true;
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bool HasAES = true;
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2017-03-31 20:16:53 +02:00
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bool HasLSLFast = false;
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2017-07-13 17:19:56 +02:00
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bool HasSVE = false;
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2017-08-10 11:52:55 +02:00
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bool HasRCPC = false;
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2018-01-25 22:55:39 +01:00
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bool HasAggressiveFMA = false;
|
2014-04-14 19:38:00 +02:00
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2018-09-27 11:11:27 +02:00
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// Armv8.5-A Extensions
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bool HasAlternativeNZCV = false;
|
2018-09-27 15:32:06 +02:00
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bool HasFRInt3264 = false;
|
2018-09-27 16:05:46 +02:00
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bool HasSpecRestrict = false;
|
2018-09-27 15:39:06 +02:00
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bool HasSpecCtrl = false;
|
2018-12-03 15:00:47 +01:00
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bool HasSSBS = false;
|
2018-09-27 15:47:40 +02:00
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bool HasPredCtrl = false;
|
2018-09-27 15:53:35 +02:00
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bool HasCCDP = false;
|
2018-09-27 16:54:33 +02:00
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bool HasBTI = false;
|
2018-09-27 16:01:40 +02:00
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bool HasRandGen = false;
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2018-10-02 11:36:28 +02:00
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bool HasMTE = false;
|
2018-09-27 11:11:27 +02:00
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2014-03-29 11:18:08 +01:00
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// HasZeroCycleRegMove - Has zero-cycle register mov instructions.
|
2016-05-28 00:14:09 +02:00
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bool HasZeroCycleRegMove = false;
|
2014-03-29 11:18:08 +01:00
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// HasZeroCycleZeroing - Has zero-cycle zeroing instructions.
|
2016-05-28 00:14:09 +02:00
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bool HasZeroCycleZeroing = false;
|
2018-09-28 21:05:09 +02:00
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bool HasZeroCycleZeroingGP = false;
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bool HasZeroCycleZeroingFP = false;
|
2017-12-18 11:36:00 +01:00
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bool HasZeroCycleZeroingFPWorkaround = false;
|
2014-03-29 11:18:08 +01:00
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|
2015-07-29 16:17:26 +02:00
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// StrictAlign - Disallow unaligned memory accesses.
|
2016-05-28 00:14:09 +02:00
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bool StrictAlign = false;
|
2017-03-28 12:02:56 +02:00
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// NegativeImmediates - transform instructions with negative immediates
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bool NegativeImmediates = true;
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|
2017-05-15 23:15:01 +02:00
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// Enable 64-bit vectorization in SLP.
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unsigned MinVectorRegisterBitWidth = 64;
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2016-06-02 20:03:53 +02:00
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bool UseAA = false;
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bool PredictableSelectIsExpensive = false;
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bool BalanceFPOps = false;
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bool CustomAsCheapAsMove = false;
|
2018-01-30 16:40:22 +01:00
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bool ExynosAsCheapAsMove = false;
|
2016-06-02 20:03:53 +02:00
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bool UsePostRAScheduler = false;
|
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bool Misaligned128StoreIsSlow = false;
|
2017-01-24 18:34:31 +01:00
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bool Paired128IsSlow = false;
|
2017-08-28 22:48:43 +02:00
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bool STRQroIsSlow = false;
|
2016-06-02 20:03:53 +02:00
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bool UseAlternateSExtLoadCVTF32Pattern = false;
|
2016-10-04 21:28:21 +02:00
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bool HasArithmeticBccFusion = false;
|
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bool HasArithmeticCbzFusion = false;
|
2018-01-30 17:28:01 +01:00
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bool HasFuseAddress = false;
|
2017-02-01 03:54:39 +01:00
|
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bool HasFuseAES = false;
|
2018-09-19 22:50:51 +02:00
|
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bool HasFuseCryptoEOR = false;
|
2018-02-23 20:27:43 +01:00
|
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bool HasFuseCCSelect = false;
|
2017-02-01 03:54:42 +01:00
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bool HasFuseLiterals = false;
|
2016-06-02 20:03:53 +02:00
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bool DisableLatencySchedHeuristic = false;
|
2016-10-24 18:14:58 +02:00
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bool UseRSqrt = false;
|
2018-10-24 22:19:09 +02:00
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bool Force32BitJumpTables = false;
|
2016-06-02 20:03:53 +02:00
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uint8_t MaxInterleaveFactor = 2;
|
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uint8_t VectorInsertExtractBaseCost = 3;
|
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uint16_t CacheLineSize = 0;
|
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uint16_t PrefetchDistance = 0;
|
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uint16_t MinPrefetchStride = 1;
|
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unsigned MaxPrefetchIterationsAhead = UINT_MAX;
|
2016-06-10 18:00:18 +02:00
|
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unsigned PrefFunctionAlignment = 0;
|
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unsigned PrefLoopAlignment = 0;
|
2016-09-26 17:32:33 +02:00
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unsigned MaxJumpTableSize = 0;
|
2017-05-09 22:18:12 +02:00
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unsigned WideningBaseCost = 0;
|
2015-07-29 16:17:26 +02:00
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[AArch64] Support reserving x1-7 registers.
Summary:
Reserving registers x1-7 is used to support CONFIG_ARM64_LSE_ATOMICS in Linux kernel. This change adds support for reserving registers x1 through x7.
Reviewers: javed.absar, phosek, srhines, nickdesaulniers, efriedma
Reviewed By: nickdesaulniers, efriedma
Subscribers: niravd, jfb, manojgupta, nickdesaulniers, jyknight, efriedma, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D48580
llvm-svn: 341706
2018-09-07 22:58:57 +02:00
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// ReserveXRegister[i] - X#i is not available as a general purpose register.
|
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BitVector ReserveXRegister;
|
2018-06-12 22:00:50 +02:00
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|
2018-09-23 00:17:50 +02:00
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// CustomCallUsedXRegister[i] - X#i call saved.
|
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|
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BitVector CustomCallSavedXRegs;
|
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|
|
2015-01-26 20:03:15 +01:00
|
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|
bool IsLittle;
|
|
|
|
|
2014-03-29 11:18:08 +01:00
|
|
|
/// TargetTriple - What processor and OS we're targeting.
|
|
|
|
Triple TargetTriple;
|
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|
|
|
2014-06-10 19:44:12 +02:00
|
|
|
AArch64FrameLowering FrameLowering;
|
2014-06-11 00:57:25 +02:00
|
|
|
AArch64InstrInfo InstrInfo;
|
2014-06-10 20:21:53 +02:00
|
|
|
AArch64SelectionDAGInfo TSInfo;
|
2014-06-11 02:46:34 +02:00
|
|
|
AArch64TargetLowering TLInfo;
|
2017-08-16 00:31:51 +02:00
|
|
|
|
|
|
|
/// GlobalISel related APIs.
|
|
|
|
std::unique_ptr<CallLowering> CallLoweringInfo;
|
|
|
|
std::unique_ptr<InstructionSelector> InstSelector;
|
|
|
|
std::unique_ptr<LegalizerInfo> Legalizer;
|
|
|
|
std::unique_ptr<RegisterBankInfo> RegBankInfo;
|
2016-02-16 20:26:02 +01:00
|
|
|
|
2014-06-11 02:46:34 +02:00
|
|
|
private:
|
|
|
|
/// initializeSubtargetDependencies - Initializes using CPUString and the
|
|
|
|
/// passed in feature string so that we can use initializer lists for
|
|
|
|
/// subtarget initialization.
|
2016-10-03 22:17:02 +02:00
|
|
|
AArch64Subtarget &initializeSubtargetDependencies(StringRef FS,
|
|
|
|
StringRef CPUString);
|
2014-06-10 19:44:12 +02:00
|
|
|
|
2016-06-02 20:03:53 +02:00
|
|
|
/// Initialize properties based on the selected processor family.
|
|
|
|
void initializeProperties();
|
|
|
|
|
2014-03-29 11:18:08 +01:00
|
|
|
public:
|
|
|
|
/// This constructor initializes the data members to match that
|
|
|
|
/// of the specified triple.
|
2015-06-10 14:11:26 +02:00
|
|
|
AArch64Subtarget(const Triple &TT, const std::string &CPU,
|
2015-03-18 21:37:30 +01:00
|
|
|
const std::string &FS, const TargetMachine &TM,
|
2017-05-19 13:08:33 +02:00
|
|
|
bool LittleEndian);
|
2014-03-29 11:18:08 +01:00
|
|
|
|
2014-08-04 23:25:23 +02:00
|
|
|
const AArch64SelectionDAGInfo *getSelectionDAGInfo() const override {
|
|
|
|
return &TSInfo;
|
|
|
|
}
|
|
|
|
const AArch64FrameLowering *getFrameLowering() const override {
|
2014-06-10 19:44:12 +02:00
|
|
|
return &FrameLowering;
|
|
|
|
}
|
2014-08-04 23:25:23 +02:00
|
|
|
const AArch64TargetLowering *getTargetLowering() const override {
|
2014-06-11 02:46:34 +02:00
|
|
|
return &TLInfo;
|
2014-06-11 01:26:45 +02:00
|
|
|
}
|
2014-08-04 23:25:23 +02:00
|
|
|
const AArch64InstrInfo *getInstrInfo() const override { return &InstrInfo; }
|
2015-03-18 21:37:30 +01:00
|
|
|
const AArch64RegisterInfo *getRegisterInfo() const override {
|
|
|
|
return &getInstrInfo()->getRegisterInfo();
|
|
|
|
}
|
2016-02-16 20:26:02 +01:00
|
|
|
const CallLowering *getCallLowering() const override;
|
2016-07-27 16:31:55 +02:00
|
|
|
const InstructionSelector *getInstructionSelector() const override;
|
2016-10-15 00:18:18 +02:00
|
|
|
const LegalizerInfo *getLegalizerInfo() const override;
|
2016-04-06 19:26:03 +02:00
|
|
|
const RegisterBankInfo *getRegBankInfo() const override;
|
2015-03-12 03:04:46 +01:00
|
|
|
const Triple &getTargetTriple() const { return TargetTriple; }
|
2014-03-30 09:25:18 +02:00
|
|
|
bool enableMachineScheduler() const override { return true; }
|
2015-06-13 05:42:16 +02:00
|
|
|
bool enablePostRAScheduler() const override {
|
2016-06-02 20:03:53 +02:00
|
|
|
return UsePostRAScheduler;
|
|
|
|
}
|
|
|
|
|
|
|
|
/// Returns ARM processor family.
|
|
|
|
/// Avoid this function! CPU specifics should be kept local to this class
|
|
|
|
/// and preferably modeled with SubtargetFeatures or properties in
|
|
|
|
/// initializeProperties().
|
|
|
|
ARMProcFamilyEnum getProcFamily() const {
|
|
|
|
return ARMProcFamily;
|
2014-09-12 19:40:39 +02:00
|
|
|
}
|
2014-03-29 11:18:08 +01:00
|
|
|
|
2015-04-01 16:49:29 +02:00
|
|
|
bool hasV8_1aOps() const { return HasV8_1aOps; }
|
2015-11-26 16:23:32 +01:00
|
|
|
bool hasV8_2aOps() const { return HasV8_2aOps; }
|
2017-08-10 11:41:00 +02:00
|
|
|
bool hasV8_3aOps() const { return HasV8_3aOps; }
|
[ARM][AArch64] Armv8.4-A Enablement
Initial patch adding assembly support for Armv8.4-A.
Besides adding v8.4 as a supported architecture to the usual places, this also
adds target features for the different crypto algorithms. Armv8.4-A introduced
new crypto algorithms, made them optional, and allows different combinations:
- none of the v8.4 crypto functions are supported, which is independent of the
implementation of the Armv8.0 SHA1 and SHA2 instructions.
- the v8.4 SHA512 and SHA3 support is implemented, in this case the Armv8.0
SHA1 and SHA2 instructions must also be implemented.
- the v8.4 SM3 and SM4 support is implemented, which is independent of the
implementation of the Armv8.0 SHA1 and SHA2 instructions.
- all of the v8.4 crypto functions are supported, in this case the Armv8.0 SHA1
and SHA2 instructions must also be implemented.
The v8.4 crypto instructions are added to AArch64 only, and not AArch32,
and are made optional extensions to Armv8.2-A.
The user-facing Clang options will map on these new target features, their
naming will be compatible with GCC and added in follow-up patches.
The Armv8.4-A instruction sets can be downloaded here:
https://developer.arm.com/products/architecture/a-profile/exploration-tools
Differential Revision: https://reviews.llvm.org/D48625
llvm-svn: 335953
2018-06-29 10:43:19 +02:00
|
|
|
bool hasV8_4aOps() const { return HasV8_4aOps; }
|
2018-09-26 14:48:21 +02:00
|
|
|
bool hasV8_5aOps() const { return HasV8_5aOps; }
|
2015-04-01 16:49:29 +02:00
|
|
|
|
2014-03-29 11:18:08 +01:00
|
|
|
bool hasZeroCycleRegMove() const { return HasZeroCycleRegMove; }
|
|
|
|
|
2018-09-28 21:05:09 +02:00
|
|
|
bool hasZeroCycleZeroingGP() const { return HasZeroCycleZeroingGP; }
|
|
|
|
|
|
|
|
bool hasZeroCycleZeroingFP() const { return HasZeroCycleZeroingFP; }
|
2014-03-29 11:18:08 +01:00
|
|
|
|
2017-12-18 11:36:00 +01:00
|
|
|
bool hasZeroCycleZeroingFPWorkaround() const {
|
|
|
|
return HasZeroCycleZeroingFPWorkaround;
|
|
|
|
}
|
|
|
|
|
2015-07-29 16:17:26 +02:00
|
|
|
bool requiresStrictAlign() const { return StrictAlign; }
|
|
|
|
|
2016-11-17 06:15:37 +01:00
|
|
|
bool isXRaySupported() const override { return true; }
|
|
|
|
|
2017-05-15 23:15:01 +02:00
|
|
|
unsigned getMinVectorRegisterBitWidth() const {
|
|
|
|
return MinVectorRegisterBitWidth;
|
|
|
|
}
|
|
|
|
|
[AArch64] Support reserving x1-7 registers.
Summary:
Reserving registers x1-7 is used to support CONFIG_ARM64_LSE_ATOMICS in Linux kernel. This change adds support for reserving registers x1 through x7.
Reviewers: javed.absar, phosek, srhines, nickdesaulniers, efriedma
Reviewed By: nickdesaulniers, efriedma
Subscribers: niravd, jfb, manojgupta, nickdesaulniers, jyknight, efriedma, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D48580
llvm-svn: 341706
2018-09-07 22:58:57 +02:00
|
|
|
bool isXRegisterReserved(size_t i) const { return ReserveXRegister[i]; }
|
|
|
|
unsigned getNumXRegisterReserved() const { return ReserveXRegister.count(); }
|
2018-09-23 00:17:50 +02:00
|
|
|
bool isXRegCustomCalleeSaved(size_t i) const {
|
|
|
|
return CustomCallSavedXRegs[i];
|
|
|
|
}
|
|
|
|
bool hasCustomCallingConv() const { return CustomCallSavedXRegs.any(); }
|
2014-04-14 19:38:00 +02:00
|
|
|
bool hasFPARMv8() const { return HasFPARMv8; }
|
|
|
|
bool hasNEON() const { return HasNEON; }
|
|
|
|
bool hasCrypto() const { return HasCrypto; }
|
2017-08-09 16:59:54 +02:00
|
|
|
bool hasDotProd() const { return HasDotProd; }
|
2014-04-25 11:25:42 +02:00
|
|
|
bool hasCRC() const { return HasCRC; }
|
2016-11-30 23:25:24 +01:00
|
|
|
bool hasLSE() const { return HasLSE; }
|
2016-06-03 16:03:27 +02:00
|
|
|
bool hasRAS() const { return HasRAS; }
|
2017-01-16 17:28:43 +01:00
|
|
|
bool hasRDM() const { return HasRDM; }
|
[ARM][AArch64] Armv8.4-A Enablement
Initial patch adding assembly support for Armv8.4-A.
Besides adding v8.4 as a supported architecture to the usual places, this also
adds target features for the different crypto algorithms. Armv8.4-A introduced
new crypto algorithms, made them optional, and allows different combinations:
- none of the v8.4 crypto functions are supported, which is independent of the
implementation of the Armv8.0 SHA1 and SHA2 instructions.
- the v8.4 SHA512 and SHA3 support is implemented, in this case the Armv8.0
SHA1 and SHA2 instructions must also be implemented.
- the v8.4 SM3 and SM4 support is implemented, which is independent of the
implementation of the Armv8.0 SHA1 and SHA2 instructions.
- all of the v8.4 crypto functions are supported, in this case the Armv8.0 SHA1
and SHA2 instructions must also be implemented.
The v8.4 crypto instructions are added to AArch64 only, and not AArch32,
and are made optional extensions to Armv8.2-A.
The user-facing Clang options will map on these new target features, their
naming will be compatible with GCC and added in follow-up patches.
The Armv8.4-A instruction sets can be downloaded here:
https://developer.arm.com/products/architecture/a-profile/exploration-tools
Differential Revision: https://reviews.llvm.org/D48625
llvm-svn: 335953
2018-06-29 10:43:19 +02:00
|
|
|
bool hasSM4() const { return HasSM4; }
|
|
|
|
bool hasSHA3() const { return HasSHA3; }
|
|
|
|
bool hasSHA2() const { return HasSHA2; }
|
|
|
|
bool hasAES() const { return HasAES; }
|
2016-06-02 20:03:53 +02:00
|
|
|
bool balanceFPOps() const { return BalanceFPOps; }
|
|
|
|
bool predictableSelectIsExpensive() const {
|
|
|
|
return PredictableSelectIsExpensive;
|
|
|
|
}
|
|
|
|
bool hasCustomCheapAsMoveHandling() const { return CustomAsCheapAsMove; }
|
2018-01-30 16:40:22 +01:00
|
|
|
bool hasExynosCheapAsMoveHandling() const { return ExynosAsCheapAsMove; }
|
2016-06-02 20:03:53 +02:00
|
|
|
bool isMisaligned128StoreSlow() const { return Misaligned128StoreIsSlow; }
|
2017-01-24 18:34:31 +01:00
|
|
|
bool isPaired128Slow() const { return Paired128IsSlow; }
|
2017-08-28 22:48:43 +02:00
|
|
|
bool isSTRQroSlow() const { return STRQroIsSlow; }
|
2016-06-02 20:03:53 +02:00
|
|
|
bool useAlternateSExtLoadCVTF32Pattern() const {
|
|
|
|
return UseAlternateSExtLoadCVTF32Pattern;
|
|
|
|
}
|
2016-10-04 21:28:21 +02:00
|
|
|
bool hasArithmeticBccFusion() const { return HasArithmeticBccFusion; }
|
|
|
|
bool hasArithmeticCbzFusion() const { return HasArithmeticCbzFusion; }
|
2018-01-30 17:28:01 +01:00
|
|
|
bool hasFuseAddress() const { return HasFuseAddress; }
|
2017-02-01 03:54:39 +01:00
|
|
|
bool hasFuseAES() const { return HasFuseAES; }
|
2018-09-19 22:50:51 +02:00
|
|
|
bool hasFuseCryptoEOR() const { return HasFuseCryptoEOR; }
|
2018-02-23 20:27:43 +01:00
|
|
|
bool hasFuseCCSelect() const { return HasFuseCCSelect; }
|
2017-02-01 03:54:42 +01:00
|
|
|
bool hasFuseLiterals() const { return HasFuseLiterals; }
|
[AArch64] Add AArch64Subtarget::isFusion function.
Summary:
isFusion returns true if the subtarget supports any kind of instruction
fusion, similar to ARMSubtarget::isFusion. This was suggested in D34142.
This changes the current behavior slightly, because the macro fusion mutation
is now added to the PostRA MachineScheduler in case the subtarget supports
any kind of fusion. I think that makes sense because if the PostRA
MachineScheduler is run, there is potential that instructions scheduled back to
back are re-scheduled.
Reviewers: evandro, t.p.northover, joelkevinjones, joel_k_jones, steleman
Reviewed By: joelkevinjones
Subscribers: joel_k_jones, aemerson, rengolin, javed.absar, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D34958
llvm-svn: 307842
2017-07-12 22:53:22 +02:00
|
|
|
|
2018-05-01 17:54:18 +02:00
|
|
|
/// Return true if the CPU supports any kind of instruction fusion.
|
[AArch64] Add AArch64Subtarget::isFusion function.
Summary:
isFusion returns true if the subtarget supports any kind of instruction
fusion, similar to ARMSubtarget::isFusion. This was suggested in D34142.
This changes the current behavior slightly, because the macro fusion mutation
is now added to the PostRA MachineScheduler in case the subtarget supports
any kind of fusion. I think that makes sense because if the PostRA
MachineScheduler is run, there is potential that instructions scheduled back to
back are re-scheduled.
Reviewers: evandro, t.p.northover, joelkevinjones, joel_k_jones, steleman
Reviewed By: joelkevinjones
Subscribers: joel_k_jones, aemerson, rengolin, javed.absar, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D34958
llvm-svn: 307842
2017-07-12 22:53:22 +02:00
|
|
|
bool hasFusion() const {
|
|
|
|
return hasArithmeticBccFusion() || hasArithmeticCbzFusion() ||
|
2018-02-23 20:27:43 +01:00
|
|
|
hasFuseAES() || hasFuseCCSelect() || hasFuseLiterals();
|
[AArch64] Add AArch64Subtarget::isFusion function.
Summary:
isFusion returns true if the subtarget supports any kind of instruction
fusion, similar to ARMSubtarget::isFusion. This was suggested in D34142.
This changes the current behavior slightly, because the macro fusion mutation
is now added to the PostRA MachineScheduler in case the subtarget supports
any kind of fusion. I think that makes sense because if the PostRA
MachineScheduler is run, there is potential that instructions scheduled back to
back are re-scheduled.
Reviewers: evandro, t.p.northover, joelkevinjones, joel_k_jones, steleman
Reviewed By: joelkevinjones
Subscribers: joel_k_jones, aemerson, rengolin, javed.absar, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D34958
llvm-svn: 307842
2017-07-12 22:53:22 +02:00
|
|
|
}
|
|
|
|
|
2016-10-24 18:14:58 +02:00
|
|
|
bool useRSqrt() const { return UseRSqrt; }
|
2018-10-24 22:19:09 +02:00
|
|
|
bool force32BitJumpTables() const { return Force32BitJumpTables; }
|
2016-06-02 20:03:53 +02:00
|
|
|
unsigned getMaxInterleaveFactor() const { return MaxInterleaveFactor; }
|
|
|
|
unsigned getVectorInsertExtractBaseCost() const {
|
|
|
|
return VectorInsertExtractBaseCost;
|
|
|
|
}
|
|
|
|
unsigned getCacheLineSize() const { return CacheLineSize; }
|
|
|
|
unsigned getPrefetchDistance() const { return PrefetchDistance; }
|
|
|
|
unsigned getMinPrefetchStride() const { return MinPrefetchStride; }
|
|
|
|
unsigned getMaxPrefetchIterationsAhead() const {
|
|
|
|
return MaxPrefetchIterationsAhead;
|
|
|
|
}
|
2016-06-10 18:00:18 +02:00
|
|
|
unsigned getPrefFunctionAlignment() const { return PrefFunctionAlignment; }
|
|
|
|
unsigned getPrefLoopAlignment() const { return PrefLoopAlignment; }
|
2016-06-02 20:03:53 +02:00
|
|
|
|
2016-09-26 17:32:33 +02:00
|
|
|
unsigned getMaximumJumpTableSize() const { return MaxJumpTableSize; }
|
|
|
|
|
2017-05-09 22:18:12 +02:00
|
|
|
unsigned getWideningBaseCost() const { return WideningBaseCost; }
|
|
|
|
|
2015-11-10 01:44:23 +01:00
|
|
|
/// CPU has TBI (top byte of addresses is ignored during HW address
|
|
|
|
/// translation) and OS enables it.
|
|
|
|
bool supportsAddressTopByteIgnored() const;
|
|
|
|
|
2015-09-01 18:23:45 +02:00
|
|
|
bool hasPerfMon() const { return HasPerfMon; }
|
2015-11-26 16:23:32 +01:00
|
|
|
bool hasFullFP16() const { return HasFullFP16; }
|
2018-08-17 13:29:49 +02:00
|
|
|
bool hasFP16FML() const { return HasFP16FML; }
|
2015-12-01 11:48:51 +01:00
|
|
|
bool hasSPE() const { return HasSPE; }
|
2017-03-31 20:16:53 +02:00
|
|
|
bool hasLSLFast() const { return HasLSLFast; }
|
2017-07-13 17:19:56 +02:00
|
|
|
bool hasSVE() const { return HasSVE; }
|
2017-08-10 11:52:55 +02:00
|
|
|
bool hasRCPC() const { return HasRCPC; }
|
2018-01-25 22:55:39 +01:00
|
|
|
bool hasAggressiveFMA() const { return HasAggressiveFMA; }
|
2018-09-27 11:11:27 +02:00
|
|
|
bool hasAlternativeNZCV() const { return HasAlternativeNZCV; }
|
2018-09-27 15:32:06 +02:00
|
|
|
bool hasFRInt3264() const { return HasFRInt3264; }
|
2018-10-02 12:04:39 +02:00
|
|
|
bool hasSpecRestrict() const { return HasSpecRestrict; }
|
|
|
|
bool hasSpecCtrl() const { return HasSpecCtrl; }
|
2018-12-03 15:00:47 +01:00
|
|
|
bool hasSSBS() const { return HasSSBS; }
|
2018-10-02 12:04:39 +02:00
|
|
|
bool hasPredCtrl() const { return HasPredCtrl; }
|
|
|
|
bool hasCCDP() const { return HasCCDP; }
|
|
|
|
bool hasBTI() const { return HasBTI; }
|
|
|
|
bool hasRandGen() const { return HasRandGen; }
|
|
|
|
bool hasMTE() const { return HasMTE; }
|
2014-04-14 19:38:00 +02:00
|
|
|
|
2015-01-26 20:03:15 +01:00
|
|
|
bool isLittleEndian() const { return IsLittle; }
|
2014-04-23 12:26:40 +02:00
|
|
|
|
2014-03-29 11:18:08 +01:00
|
|
|
bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
|
2014-08-06 18:56:58 +02:00
|
|
|
bool isTargetIOS() const { return TargetTriple.isiOS(); }
|
|
|
|
bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
|
|
|
|
bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
|
2015-10-08 23:21:24 +02:00
|
|
|
bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
|
2017-02-24 04:10:10 +01:00
|
|
|
bool isTargetFuchsia() const { return TargetTriple.isOSFuchsia(); }
|
2014-03-29 11:18:08 +01:00
|
|
|
|
2014-08-06 18:56:58 +02:00
|
|
|
bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
|
2014-03-29 11:18:08 +01:00
|
|
|
bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
|
|
|
|
bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
|
|
|
|
|
2016-06-02 20:03:53 +02:00
|
|
|
bool useAA() const override { return UseAA; }
|
2014-09-08 16:31:49 +02:00
|
|
|
|
2017-04-04 21:51:53 +02:00
|
|
|
bool useSmallAddressing() const {
|
|
|
|
switch (TLInfo.getTargetMachine().getCodeModel()) {
|
|
|
|
case CodeModel::Kernel:
|
|
|
|
// Kernel is currently allowed only for Fuchsia targets,
|
|
|
|
// where it is the same as Small for almost all purposes.
|
|
|
|
case CodeModel::Small:
|
|
|
|
return true;
|
|
|
|
default:
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-03-29 11:18:08 +01:00
|
|
|
/// ParseSubtargetFeatures - Parses features string setting specified
|
|
|
|
/// subtarget options. Definition of function is auto generated by tblgen.
|
|
|
|
void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
|
|
|
|
|
|
|
|
/// ClassifyGlobalReference - Find the target operand flags that describe
|
|
|
|
/// how a global value should be referenced for the current subtarget.
|
|
|
|
unsigned char ClassifyGlobalReference(const GlobalValue *GV,
|
|
|
|
const TargetMachine &TM) const;
|
|
|
|
|
2017-04-17 19:27:56 +02:00
|
|
|
unsigned char classifyGlobalFunctionReference(const GlobalValue *GV,
|
|
|
|
const TargetMachine &TM) const;
|
|
|
|
|
2016-07-01 02:23:27 +02:00
|
|
|
void overrideSchedPolicy(MachineSchedPolicy &Policy,
|
2014-04-29 09:58:25 +02:00
|
|
|
unsigned NumRegionInstrs) const override;
|
2014-05-22 01:40:26 +02:00
|
|
|
|
|
|
|
bool enableEarlyIfConversion() const override;
|
2014-10-09 20:20:51 +02:00
|
|
|
|
|
|
|
std::unique_ptr<PBQPRAConstraint> getCustomPBQPConstraints() const override;
|
2017-07-17 22:05:19 +02:00
|
|
|
|
|
|
|
bool isCallingConvWin64(CallingConv::ID CC) const {
|
|
|
|
switch (CC) {
|
|
|
|
case CallingConv::C:
|
2018-12-05 08:09:20 +01:00
|
|
|
case CallingConv::Fast:
|
|
|
|
case CallingConv::Swift:
|
2017-07-17 22:05:19 +02:00
|
|
|
return isTargetWindows();
|
|
|
|
case CallingConv::Win64:
|
|
|
|
return true;
|
|
|
|
default:
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
2018-01-19 04:16:36 +01:00
|
|
|
|
|
|
|
void mirFileLoaded(MachineFunction &MF) const override;
|
2014-03-29 11:18:08 +01:00
|
|
|
};
|
2015-06-23 11:49:53 +02:00
|
|
|
} // End llvm namespace
|
2014-03-29 11:18:08 +01:00
|
|
|
|
2014-08-13 18:26:38 +02:00
|
|
|
#endif
|