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557 Commits

Author SHA1 Message Date
Chris Lattner
3d38dbff2a Make this more likely to generate a libcall. 
llvm-svn: 92387
 2010-01-01 03:26:51 +00:00
Bob Wilson
a9f20f9f6e Handle ARM inline asm "w" constraints with 64-bit ("d") registers. 
The change in SelectionDAGBuilder is needed to allow using bitcasts to convert
between f64 (the default type for ARM "d" registers) and 64-bit Neon vector
types.  Radar 7457110.

llvm-svn: 91649
 2009-12-18 01:03:29 +00:00
Evan Cheng
edcc21919f - Support inline asm 'w' constraint for 128-bit vector types. 
- Also support the 'q' NEON registers asm code.

llvm-svn: 90894
 2009-12-08 23:06:22 +00:00
Bob Wilson
b53c801366 Recognize canonical forms of vector shuffles where the same vector is used for 
both source operands.  In the canonical form, the 2nd operand is changed to an
undef and the shuffle mask is adjusted to only reference elements from the 1st
operand.  Radar 7434842.

llvm-svn: 90417
 2009-12-03 06:40:55 +00:00
Evan Cheng
fcbc30f36e Fix PR5614: parts of a physical register def may be killed the rest. 
llvm-svn: 90180
 2009-12-01 00:44:45 +00:00
Anton Korobeynikov
0f885eb7fd Materialize global addresses via movt/movw pair, this is always better 
than doing the same via constpool:
1. Load from constpool costs 3 cycles on A9, movt/movw pair - just 2.
2. Load from constpool might stall up to 300 cycles due to cache miss.
3. Movt/movw does not use load/store unit.
4. Less constpool entries => better compiler performance.

This is only enabled on ELF systems, since darwin does not have needed
relocations (yet).

llvm-svn: 89720
 2009-11-24 00:44:37 +00:00
Jim Grosbach
76b545e988 move fconst[sd] to UAL. <rdar://7414913> 
llvm-svn: 89700
 2009-11-23 21:08:25 +00:00
Edward O'Callaghan
d1c7b40bb5 Convert ARM tests to FileCheck for PR5307. 
llvm-svn: 89593
 2009-11-22 14:23:33 +00:00
Edward O'Callaghan
1a250b4109 Forgot to alter RUN line when converting to FileCheck. 
llvm-svn: 89588
 2009-11-22 13:09:48 +00:00
Edward O'Callaghan
5ae4559914 Fix for bad FileCheck converts in revision 89584. 
llvm-svn: 89586
 2009-11-22 12:50:05 +00:00
Edward O'Callaghan
949850890f Convert a few tests to FileCheck for PR5307. 
llvm-svn: 89584
 2009-11-22 11:45:44 +00:00
Jim Grosbach
99c5b49c61 Revert 89562. We're being sneakier than I was giving us credit for, and this 
isn't necessary.

llvm-svn: 89568
 2009-11-21 23:34:09 +00:00
Jim Grosbach
d4603a5c4e Darwin requires a frame pointer for all non-leaf functions to support correct 
backtraces.

llvm-svn: 89562
 2009-11-21 21:40:08 +00:00
Evan Cheng
9f57c4916e Remat VLDRD from constpool. Clean up some instruction property specifications. 
llvm-svn: 89478
 2009-11-20 19:57:15 +00:00
Evan Cheng
405012b096 Fix codegen of conditional move of immediates. We were not making use of the immediate forms of cmov instructions at all. 
llvm-svn: 89423
 2009-11-20 00:54:03 +00:00
Bob Wilson
70bfa110eb Fix buildbots. 
llvm-svn: 89274
 2009-11-18 23:30:38 +00:00
Bob Wilson
dccd3bdb4e Tail duplication still needs to iterate. Duplicating new instructions onto 
the tail of a block may make that block a new candidate for duplication.

llvm-svn: 89264
 2009-11-18 22:52:37 +00:00
Anton Korobeynikov
6b1a243be8 Forgot to commit test fixes 
llvm-svn: 89138
 2009-11-17 20:38:36 +00:00
Jim Grosbach
1aa571da3c Detect need for autoalignment of the stack earlier to catch spills more 
conservatively. eliminateFrameIndex() machinery adjust to handle addr mode
6 (vld1/vst1) used for spills. Fix tests to expect aligned Q-reg spilling

llvm-svn: 88874
 2009-11-15 21:45:34 +00:00
Evan Cheng
9b46e74f42 - Change TargetInstrInfo::reMaterialize to pass in TargetRegisterInfo. 
- If destination is a physical register and it has a subreg index, use the
  sub-register instead.
This fixes PR5423.

llvm-svn: 88745
 2009-11-14 02:55:43 +00:00
Evan Cheng
3781b2e7b3 Add radar number. 
llvm-svn: 88739
 2009-11-14 02:11:32 +00:00
Evan Cheng
c56b0a0f14 Fix PR5412: Fix an inverted check and another missing sub-register check. 
llvm-svn: 88738
 2009-11-14 02:09:09 +00:00
Evan Cheng
e2907b91de Fix PR5411. Bug in UpdateKills. A reg def partially define its super-registers. 
llvm-svn: 88719
 2009-11-13 23:16:41 +00:00
Evan Cheng
f629fdcab2 Fix PR5410: LiveVariables lost subreg def: 
D0<def,dead> = ...
...
             = S0<use, kill>
S0<def>      = ...
...
D0<def>      = 

The first D0 def is correctly marked dead, however, livevariables should have
added an implicit def of S0 or we end up with a use without a def.

llvm-svn: 88690
 2009-11-13 20:36:40 +00:00
Jim Grosbach
ea6c9c17f5 Use Unified Assembly Syntax for the ARM backend. 
llvm-svn: 86494
 2009-11-09 00:11:35 +00:00
Anton Korobeynikov
30095499fc It turns out that the testcase in question uncovered subreg-handling bug. 
Add assert in asmprinter to catch such cases and xfail the tests.
PR is to be filled.

llvm-svn: 86375
 2009-11-07 15:20:32 +00:00
Anton Korobeynikov
dca40933ee Honour subreg machine operands during asmprinting 
llvm-svn: 86303
 2009-11-06 23:45:15 +00:00
Bob Wilson
e79354a831 Print VMOV (immediate) operands as hexadecimal values. Apple's assembler 
will not accept negative values for these.  LLVM's default operand printing
sign extends values, so that valid unsigned values appear as negative
immediates.  Print all VMOV immediate operands as hex values to resolve this.
Radar 7372576.

llvm-svn: 86301
 2009-11-06 23:33:28 +00:00
Evan Cheng
aaf30ce699 Remove ARMPCLabelIndex from ARMISelLowering. Use ARMFunctionInfo::createConstPoolEntryUId() instead. 
llvm-svn: 86294
 2009-11-06 22:24:13 +00:00
Dan Gohman
229f9edf7a Update these tests for the new label names. 
llvm-svn: 86192
 2009-11-05 23:31:40 +00:00
Bob Wilson
d14be3d83c Attempt again to fix buildbot failures: make expected output less specific 
and compile with -mtriple to specify *-apple-darwin targets.

llvm-svn: 86081
 2009-11-05 00:30:35 +00:00
Bob Wilson
9e30ecad4e Fix broken test. 
llvm-svn: 86045
 2009-11-04 20:04:11 +00:00
Bob Wilson
ca42ca296d Add test for ARM indirectbr codegen. 
llvm-svn: 86042
 2009-11-04 19:25:34 +00:00
Evan Cheng
caab17007b fconsts / fconstd immediate should be proceeded with #. 
llvm-svn: 85952
 2009-11-03 21:59:33 +00:00
Evan Cheng
d783406059 Re-apply 85799. It turns out my code isn't buggy. 
llvm-svn: 85947
 2009-11-03 21:40:02 +00:00
Evan Cheng
ed22395c61 Fix PR5367. QPR_8 is the super regclass of DPR_8 and SPR_8. 
llvm-svn: 85871
 2009-11-03 05:52:54 +00:00
Anton Korobeynikov
48b30c79be Revert r85049, it is causing PR5367 
llvm-svn: 85847
 2009-11-03 00:24:48 +00:00
Evan Cheng
ca5847665b Revert 85799 for now. It might be breaking llvm-gcc driver. 
llvm-svn: 85827
 2009-11-02 21:49:14 +00:00
Evan Cheng
ec5cb0cdbd Initilize the machine LICM CSE map upon the first time an instruction is hoisted to 
the loop preheader. Add instructions which are already in the preheader block that
may be common expressions of those that are hoisted out. These does get a few more
instructions CSE'ed.

llvm-svn: 85799
 2009-11-02 08:09:49 +00:00
Evan Cheng
ce9d8e2737 Remove an irrelevant and poorly reduced test case. 
llvm-svn: 85794
 2009-11-02 07:11:54 +00:00
Anton Korobeynikov
09147da530 Handle splats of undefs properly. This includes the testcase for PR5364 as well. 
llvm-svn: 85767
 2009-11-02 00:12:06 +00:00
Anton Korobeynikov
ed410a8ee3 64-bit FP loads & stores operate on both NEON and VFP pipelines. 
llvm-svn: 85765
 2009-11-02 00:11:06 +00:00
Jim Grosbach
5b094f3b36 vml[as].f32 cause stalls in following advanced SIMD instructions. Avoid using 
them for scalar floating point operations for now.

llvm-svn: 85697
 2009-10-31 22:57:36 +00:00
Jim Grosbach
2a445e5d0a Update test to be more explicit about what instruction sequences are expected for each operation. 
llvm-svn: 85689
 2009-10-31 21:52:58 +00:00
Jim Grosbach
ace75c4288 Expand 64-bit logical shift right inline 
llvm-svn: 85687
 2009-10-31 21:42:19 +00:00
Jim Grosbach
16ae289667 Expand 64-bit arithmetic shift right inline 
llvm-svn: 85685
 2009-10-31 21:00:56 +00:00
Jim Grosbach
534d2cb249 Expand 64 bit left shift inline rather than using the libcall. For now, this 
is unconditional. Making it still use the libcall when optimizing for size
would be a good adjustment.

llvm-svn: 85675
 2009-10-31 19:38:01 +00:00
Benjamin Kramer
60dac7de40 Add missing colons for FileCheck. 
llvm-svn: 85674
 2009-10-31 19:22:24 +00:00
Jim Grosbach
78a5bcfa02 Convert to FileCheck 
llvm-svn: 85673
 2009-10-31 19:06:53 +00:00
Rafael Espindola
d4fadd76da This fixes functions like 
void f (int a1, int a2, int a3, int a4, int a5,...)

In ARMTargetLowering::LowerFormalArguments if the function has 4 or
more regular arguments we used to set VarArgsFrameIndex using an
offset of 0, which is only correct if the function has exactly 4
regular arguments.

llvm-svn: 85590
 2009-10-30 14:33:14 +00:00
Evan Cheng
1babe43881 Use fconsts and fconstd to materialize small fp constants. 
llvm-svn: 85362
 2009-10-28 01:44:26 +00:00
Rafael Espindola
9cafe9e468 Add missing testcase. 
llvm-svn: 85266
 2009-10-27 17:59:03 +00:00
Bob Wilson
cc098c98de Fix the rest of the ARM failures by converting them to FileCheck. 
llvm-svn: 85208
 2009-10-27 06:16:45 +00:00
Bob Wilson
5753a34ebb Fix some more failures by converting to FileCheck. 
llvm-svn: 85207
 2009-10-27 05:50:28 +00:00
Bob Wilson
37191c825b Convert to FileCheck, fixing failure due to tab change in the process. 
llvm-svn: 85204
 2009-10-27 05:30:47 +00:00
Evan Cheng
1c169777ca Update tests. 
llvm-svn: 85050
 2009-10-25 07:53:48 +00:00
Bob Wilson
8f4f73da55 Revert 84843. Evan, this was breaking some of the if-conversion tests. 
llvm-svn: 84868
 2009-10-22 16:52:21 +00:00
Evan Cheng
2edd1efa46 Move if-conversion before post-regalloc scheduling so the predicated instruction get scheduled properly. 
llvm-svn: 84843
 2009-10-22 06:48:32 +00:00
Evan Cheng
8fdd1661fa Don't generate sbfx / ubfx with negative lsb field. Patch by David Conrad. 
llvm-svn: 84813
 2009-10-22 00:40:00 +00:00
Evan Cheng
275a09e55d Match more patterns to movt. 
llvm-svn: 84751
 2009-10-21 08:15:52 +00:00
Anton Korobeynikov
7b6fe9f251 Fix invalid for vector types fneg(bitconvert(x)) => bitconvert(x ^ sign) 
transform.

llvm-svn: 84683
 2009-10-20 21:37:45 +00:00
Chris Lattner
b9bbaf7f4d convert to filecheck syntax and make a lot more aggressive. 
llvm-svn: 84517
 2009-10-19 18:27:56 +00:00
Chris Lattner
6fd5bc3ba0 rename test 
llvm-svn: 84515
 2009-10-19 18:18:07 +00:00
Evan Cheng
b1580b5c48 Enable post-alloc scheduling for all ARM variants except for Thumb1. 
llvm-svn: 84249
 2009-10-16 06:11:08 +00:00
Bob Wilson
d66a3fd73b Revise ARM inline assembly memory operands to require the memory address to 
be in a register.  The previous use of ARM address mode 2 was completely
arbitrary and inappropriate for Thumb.  Radar 7137468.

llvm-svn: 84022
 2009-10-13 20:50:28 +00:00
Sandeep Patel
1584038783 Add ARMv6T2 SBFX/UBFX instructions. Approved by Anton Korobeynikov. 
llvm-svn: 84009
 2009-10-13 18:59:48 +00:00
Benjamin Kramer
34c117d8b7 Eliminate some redundant llvm-as calls. 
llvm-svn: 83837
 2009-10-12 09:31:55 +00:00
Dan Gohman
b535009219 Update this test; the code is the same but it gets counted as one 
fewer remat.

llvm-svn: 83690
 2009-10-09 23:31:04 +00:00
Bob Wilson
011e458c11 Merge a bunch of NEON tests into larger files so they run faster. 
llvm-svn: 83667
 2009-10-09 20:20:54 +00:00
Bob Wilson
de71518edb Convert some ARM tests with lots of greps to use FileCheck. 
llvm-svn: 83651
 2009-10-09 17:20:46 +00:00
Bob Wilson
d48cacb92f Commit one last NEON test to use FileCheck. That's all of them now! 
llvm-svn: 83617
 2009-10-09 05:31:56 +00:00
Bob Wilson
a8746e6bd1 Convert more NEON tests to use FileCheck. 
llvm-svn: 83616
 2009-10-09 05:14:48 +00:00
Bob Wilson
8092fef09a Add codegen support for NEON vst4lane intrinsics with 128-bit vectors. 
llvm-svn: 83600
 2009-10-09 00:01:36 +00:00
Bob Wilson
979cb24a81 Add codegen support for NEON vst3lane intrinsics with 128-bit vectors. 
llvm-svn: 83598
 2009-10-08 23:51:31 +00:00
Bob Wilson
233992bc56 Add codegen support for NEON vst2lane intrinsics with 128-bit vectors. 
llvm-svn: 83596
 2009-10-08 23:38:24 +00:00
Bob Wilson
395adfabef Convert more NEON tests to use FileCheck. 
llvm-svn: 83595
 2009-10-08 23:33:03 +00:00
Bob Wilson
5b96a53ffe Add codegen support for NEON vld4lane intrinsics with 128-bit vectors. 
Also fix some copy-and-paste errors in previous changes.

llvm-svn: 83590
 2009-10-08 22:53:57 +00:00
Bob Wilson
1fe8b7e27c Convert more NEON tests to use FileCheck. 
llvm-svn: 83587
 2009-10-08 22:33:53 +00:00
Bob Wilson
7209d78713 Add codegen support for NEON vld3lane intrinsics with 128-bit vectors. 
llvm-svn: 83585
 2009-10-08 22:27:33 +00:00
Anton Korobeynikov
f9c811c948 Use lower16 / upper16 imm modifiers to asmprint 32-bit imms splitted via movt/movw pair. 
llvm-svn: 83572
 2009-10-08 20:43:22 +00:00
Bob Wilson
3a55fe2105 Add codegen support for NEON vld2lane intrinsics with 128-bit vectors. 
llvm-svn: 83568
 2009-10-08 18:56:10 +00:00
Bob Wilson
225627ec81 Convert more NEON tests to use FileCheck. 
llvm-svn: 83528
 2009-10-08 06:02:10 +00:00
Bob Wilson
276bdabb9a Add codegen support for NEON vst4 intrinsics with <1 x i64> vectors. 
llvm-svn: 83526
 2009-10-08 05:18:18 +00:00
Bob Wilson
8aa1d328b5 Add codegen support for NEON vst3 intrinsics with <1 x i64> vectors. 
llvm-svn: 83518
 2009-10-08 00:28:28 +00:00
Bob Wilson
958e4ae815 Add codegen support for NEON vst2 intrinsics with <1 x i64> vectors. 
llvm-svn: 83513
 2009-10-08 00:21:01 +00:00
Bob Wilson
729cd181a2 Add codegen support for NEON vld4 intrinsics with <1 x i64> vectors. 
llvm-svn: 83508
 2009-10-07 23:54:04 +00:00
Bob Wilson
c7baa2832f Convert more NEON tests to use FileCheck. 
llvm-svn: 83507
 2009-10-07 23:47:21 +00:00
Bob Wilson
3cbf156518 Add codegen support for NEON vld3 intrinsics with <1 x i64> vectors. 
llvm-svn: 83506
 2009-10-07 23:39:57 +00:00
Bob Wilson
0ffa9679a5 Add codegen support for NEON vld2 intrinsics with <1 x i64> vectors. 
llvm-svn: 83502
 2009-10-07 22:57:01 +00:00
Bob Wilson
97bab9ef32 Convert more NEON tests to use FileCheck. 
llvm-svn: 83497
 2009-10-07 22:30:19 +00:00
Bob Wilson
a367eb439c Convert test to FileCheck. 
llvm-svn: 83487
 2009-10-07 20:51:42 +00:00
Bob Wilson
cee91108da Add codegen support for NEON vst4 intrinsics with 128-bit vectors. 
llvm-svn: 83486
 2009-10-07 20:49:18 +00:00
Bob Wilson
af14187764 Add codegen support for NEON vst3 intrinsics with 128-bit vectors. 
llvm-svn: 83484
 2009-10-07 20:30:08 +00:00
Bob Wilson
62a3e55cea Add codegen support for NEON vst2 intrinsics with 128-bit vectors. 
llvm-svn: 83482
 2009-10-07 18:47:39 +00:00
Bob Wilson
9bb47b3e5d Add codegen support for NEON vld4 intrinsics with 128-bit vectors. 
llvm-svn: 83479
 2009-10-07 18:09:32 +00:00
Bob Wilson
b38401ccef Add codegen support for NEON vld3 intrinsics with 128-bit vectors. 
llvm-svn: 83471
 2009-10-07 17:24:55 +00:00
Bob Wilson
39328dad67 Add tests for vld2 of 128-bit vectors. 
llvm-svn: 83468
 2009-10-07 17:19:13 +00:00
Bob Wilson
636d635cc1 Update NEON struct names to match llvm-gcc changes. 
(This is not required for correctness but might help with sanity.)

llvm-svn: 83415
 2009-10-06 21:16:19 +00:00
Evan Cheng
d93fbb28ed Fix tests. 
llvm-svn: 83241
 2009-10-02 06:53:57 +00:00
Evan Cheng
d6e64a4cfd Move load / store multiple before post-alloc scheduling. 
llvm-svn: 83236
 2009-10-02 04:57:15 +00:00
David Goodwin
a4b73e486e Remove neonfp attribute and instead set default based on CPU string. Add -arm-use-neon-fp to override the default. 
llvm-svn: 83218
 2009-10-01 22:19:57 +00:00
David Goodwin
d0edce4c0d Restore the -post-RA-scheduler flag as an override for the target specification. Remove -mattr for setting PostRAScheduler enable and instead use CPU string. 
llvm-svn: 83215
 2009-10-01 21:46:35 +00:00
David Goodwin
a282690f82 Remove -post-RA-schedule flag and add a TargetSubtarget method to enable post-register-allocation scheduling. By default it is off. For ARM, enable/disable with -mattr=+/-postrasched. Enable by default for cortex-a8. 
llvm-svn: 83122
 2009-09-30 00:10:16 +00:00
David Goodwin
34aa421e3a Post-RA regressions. 
llvm-svn: 83075
 2009-09-29 17:10:26 +00:00
Evan Cheng
d2bf81c7af Fix PR4687. Pre ARMv5te does not support ldrd / strd. Patch by John Tytgat. 
llvm-svn: 83058
 2009-09-29 07:07:30 +00:00
Evan Cheng
ddc8678b00 Coalescer should not delete extract_subreg, insert_subreg, and subreg_to_reg of 
physical registers. This is especially critical for the later two since they
start the live interval of a super-register. e.g.
%DO<def> = INSERT_SUBREG %D0<undef>, %S0<kill>, 1
If this instruction is eliminated, the register scavenger will not be happy as
D0 is not defined previously.
This fixes PR5055.

llvm-svn: 82968
 2009-09-28 05:28:43 +00:00
Anton Korobeynikov
189ce11684 Use movt/movw pair to materialize 32 bit constants on ARMv6T2+. 
This should be better than single load from constpool.

llvm-svn: 82948
 2009-09-27 23:52:58 +00:00
Evan Cheng
eafd25a098 Remove this test. 
llvm-svn: 82869
 2009-09-26 18:51:37 +00:00
Daniel Dunbar
923dc62615 "Update" tests for -disable-if-conversion removal. I think branch.ll should just 
be removed, but I XFAIL'd it for now.

llvm-svn: 82847
 2009-09-26 05:29:36 +00:00
Evan Cheng
0b55bde4b3 Convert test to filecheck. 
llvm-svn: 82835
 2009-09-26 02:41:17 +00:00
Evan Cheng
ac17fbc5fe Flip -disable-post-RA-scheduler to -post-RA-scheduler. 
llvm-svn: 82803
 2009-09-25 21:38:11 +00:00
Dan Gohman
0ac693a89e Improve MachineMemOperand handling. 
- Allocate MachineMemOperands and MachineMemOperand lists in MachineFunctions.
   This eliminates MachineInstr's std::list member and allows the data to be
   created by isel and live for the remainder of codegen, avoiding a lot of
   copying and unnecessary translation. This also shrinks MemSDNode.
 - Delete MemOperandSDNode. Introduce MachineSDNode which has dedicated
   fields for MachineMemOperands.
 - Change MemSDNode to have a MachineMemOperand member instead of its own
   fields with the same information. This introduces some redundancy, but
   it's more consistent with what MachineInstr will eventually want.
 - Ignore alignment when searching for redundant loads for CSE, but remember
   the greatest alignment.

Target-specific code which previously used MemOperandSDNodes with generic
SDNodes now use MemIntrinsicSDNodes, with opcodes in a designated range
so that the SelectionDAG framework knows that MachineMemOperand information
is available.

llvm-svn: 82794
 2009-09-25 20:36:54 +00:00
Bob Wilson
94e29af5ac pr4926: ARM requires the stack pointer to be aligned, even for leaf functions. 
For the AAPCS ABI, SP must always be 4-byte aligned, and at any "public
interface" it must be 8-byte aligned.  For the older ARM APCS ABI, the stack
alignment is just always 4 bytes.  For X86, we currently align SP at
entry to a function (e.g., to 16 bytes for Darwin), but no stack alignment
is needed at other times, such as for a leaf function.

After discussing this with Dan, I decided to go with the approach of adding
a new "TransientStackAlignment" field to TargetFrameInfo.  This value
specifies the stack alignment that must be maintained even in between calls.
It defaults to 1 except for ARM, where it is 4.  (Some other targets may
also want to set this if they have similar stack requirements. It's not
currently required for PPC because it sets targetHandlesStackFrameRounding
and handles the alignment in target-specific code.) The existing StackAlignment
value specifies the alignment upon entry to a function, which is how we've
been using it anyway.

llvm-svn: 82767
 2009-09-25 14:41:49 +00:00
Bob Wilson
4cb29f6864 Convert to FileCheck. 
llvm-svn: 82710
 2009-09-24 20:23:02 +00:00
Evan Cheng
e9267f10c7 Fix PR5024 with a big hammer: disable the double-def assertion in the scavenger. 
LiveVariables add implicit kills to correctly track partial register kills. This works well enough and is fairly accurate. But coalescer can make it impossible to maintain these markers. e.g.

        BL <ga:sss1>, %R0<kill,undef>, %S0<kill>, %R0<imp-def>, %R1<imp-def,dead>, %R2<imp-def,dead>, %R3<imp-def,dead>, %R12<imp-def,dead>, %LR<imp-def,dead>, %D0<imp-def>, ...
...
	%reg1031<def> = FLDS <cp#1>, 0, 14, %reg0, Mem:LD4[ConstantPool]
...
   	%S0<def> = FCPYS %reg1031<kill>, 14, %reg0, %D0<imp-use,kill>

When reg1031 and S0 are coalesced, the copy (FCPYS) will be eliminated the the implicit-kill of D0 is lost. In this case it's possible to move the marker to the FLDS. But in many cases, this is not possible. Suppose

	%reg1031<def> = FOO <cp#1>, %D0<imp-def>
...
   	%S0<def> = FCPYS %reg1031<kill>, 14, %reg0, %D0<imp-use,kill>

When FCPYS goes away, the definition of S0 is the "FOO" instruction. However, transferring the D0 implicit-kill to FOO doesn't work since it is the def of D0 itself. We need to fix this in another time by introducing a "kill" pseudo instruction to track liveness.

Disabling the assertion is not ideal, but machine verifier is doing that job now. It's important to know double-def is not a miscomputation since it means a register should be free but it's not tracked as free. It's a performance issue instead.

llvm-svn: 82677
 2009-09-24 02:27:09 +00:00
Evan Cheng
863ed2677b Fix PR5024. LiveVariables physical register defs should *commit* only after all 
of the defs are processed.
Also fix a implicit_def propagation bug: a implicit_def of a physical register
should be applied to uses of the sub-registers.

llvm-svn: 82616
 2009-09-23 06:28:31 +00:00
Evan Cheng
97c8597450 Fix PR5024. LiveVariables::FindLastPartialDef should return a set of sub-registers that were defined by the last partial def, not just a single sub-register. 
llvm-svn: 82535
 2009-09-22 08:34:46 +00:00
Evan Cheng
07d521ed99 Fix a pasto. Also simplify for Bill's benefit. 
llvm-svn: 82505
 2009-09-22 01:48:19 +00:00
Evan Cheng
a6d602a5c1 Clean up spill weight computation. Also some changes to give loop induction 
variable increment / decrement slighter high priority. 

This has major impact on some micro-benchmarks. On MultiSource/Applications
and spec tests, it's a minor win. It also reduce 256.bzip instruction count
by 8%, 55 on 164.gzip on i386 / Darwin.

llvm-svn: 82485
 2009-09-21 21:12:25 +00:00
Evan Cheng
3edb8b18a5 Fix PR4986. "r1024 = insert_subreg r1024, undef, 2" cannot be turned in an implicit_def. Instead, it's an identity copy so it should be eliminated. Also make sure to update livevariable kill information. 
llvm-svn: 82436
 2009-09-21 04:32:32 +00:00
Bob Wilson
9bcea11785 Convert more tests to FileCheck. 
llvm-svn: 81915
 2009-09-15 20:58:02 +00:00
Sandeep Patel
7727a68464 Fix superreg use in ARMAsmPrinter. Approved by Anton Korobeynikov. 
llvm-svn: 81878
 2009-09-15 17:53:11 +00:00
Anton Korobeynikov
fa4c7562d5 Define proper subreg sets for arm - this should fix bunch of subtle problems 
with subreg - superreg mapping and also fix PR4965.

llvm-svn: 81657
 2009-09-13 00:59:43 +00:00
Dan Gohman
8e55f0f55b Remove an unnecessary -f. 
llvm-svn: 81546
 2009-09-11 18:41:06 +00:00
Dan Gohman
f2c290dfa6 Convert more tests to avoid llvm-as. 
llvm-svn: 81545
 2009-09-11 18:36:27 +00:00
Bob Wilson
7b39f31422 Don't swap the operands of a subtraction when trying to create a 
post-decrement load/store.

llvm-svn: 81464
 2009-09-10 22:09:31 +00:00
Bob Wilson
877a857b4b Fix pr4939: Change FPCCToARMCC to translate SETOLE to ARMCC::LS. 
See the bug report for details.

llvm-svn: 81397
 2009-09-09 23:14:54 +00:00
Dan Gohman
142428ce64 Eliminate more uses of llvm-as and llvm-dis. 
llvm-svn: 81293
 2009-09-09 00:09:15 +00:00
Anton Korobeynikov
2b6ef7724e Unbreak getOnesVector() / getZeroVector() to use valid ARM extended imm's. 
llvm-svn: 81262
 2009-09-08 22:51:43 +00:00
Anton Korobeynikov
0b3a620d60 Add NEON 'laned' operations. This fixes another bunch of gcc testsuite fails and 
makes the code faster.

llvm-svn: 81220
 2009-09-08 15:22:32 +00:00
Daniel Dunbar
2a64e85835 Remove stale greps. 
llvm-svn: 80986
 2009-09-04 05:07:52 +00:00
Bob Wilson
25410ac604 Convert tests to FileCheck. 
llvm-svn: 80983
 2009-09-04 04:07:19 +00:00
Bob Wilson
9e02907942 Convert a test to FileCheck. 
llvm-svn: 80975
 2009-09-04 00:32:31 +00:00
Evan Cheng
41e87f2f13 Reference to hidden symbols do not have to go through non-lazy pointer in non-pic mode. rdar://7187172. 
llvm-svn: 80904
 2009-09-03 07:04:02 +00:00
Anton Korobeynikov
7125d63acf More missed vdup patterns 
llvm-svn: 80838
 2009-09-02 21:21:28 +00:00
Bob Wilson
6972a16bbc Add support for generating code for vst{234}lane intrinsics. 
llvm-svn: 80707
 2009-09-01 18:51:56 +00:00
Bob Wilson
75b2b04e1e Fix incorrect declarations of intrinsics in this test. 
llvm-svn: 80705
 2009-09-01 18:50:43 +00:00
Bob Wilson
d638cc8869 Add test for vld{234}_lane instructions. 
llvm-svn: 80658
 2009-09-01 04:27:10 +00:00
Bob Wilson
03f5a5bfff Fix pr4843: When an instruction has multiple destination registers that are 
tied to different source registers, the TwoAddressInstructionPass needs to
be smarter.  Change it to check before replacing a source register whether
that source register is tied to a different destination register, and if so,
defer handling it until a subsequent iteration.

llvm-svn: 80654
 2009-09-01 04:18:40 +00:00
Jim Grosbach
4e0e9a4870 SJLJ is arm/darwin only for now. force the triple for the test 
llvm-svn: 80651
 2009-09-01 02:34:49 +00:00
Jim Grosbach
9a220088ac Clean up LSDA name generation and use for SJLJ exception handling. This 
makes an eggregious hack somewhat more palatable. Bringing the LSDA forward
and making it a GV available for reference would be even better, but is
beyond the scope of what I'm looking to solve at this point.

Objective C++ code could generate function names that broke the previous
scheme. This fixes that.

llvm-svn: 80649
 2009-09-01 01:57:56 +00:00
David Goodwin
0fc3764297 Don't mark a register live at an undef use. 
llvm-svn: 80621
 2009-08-31 20:47:02 +00:00
Anton Korobeynikov
17529667db Add missed pattern 
llvm-svn: 80502
 2009-08-30 19:06:39 +00:00
Anton Korobeynikov
a261afbf14 EXTRACT_VECTOR_ELEMENT can have result type different from element type. 
Remove the assertion and generalize the code for ARM NEON stuff.

llvm-svn: 80498
 2009-08-30 17:14:54 +00:00
Anton Korobeynikov
b2e6f5eed4 Do not assert on too wide splats we don't support. 
llvm-svn: 80409
 2009-08-29 00:08:18 +00:00
Anton Korobeynikov
9fd6082c10 Add missed extract_element pattern 
llvm-svn: 80408
 2009-08-28 23:41:26 +00:00
Evan Cheng
d7a07ab112 Let Darwin linker auto-synthesize stubs and lazy-pointers. This deletes a bunch of nasty code in ARM asm printer. 
llvm-svn: 80404
 2009-08-28 23:18:09 +00:00
Evan Cheng
2d5d3700e9 v4, v5 does not support sxtb / sxth. 
llvm-svn: 80322
 2009-08-28 00:31:43 +00:00
Anton Korobeynikov
cb0fdc4505 scalar_to_vector is fully legal now (implemented as subreg accesses) 
llvm-svn: 80249
 2009-08-27 16:04:47 +00:00
Anton Korobeynikov
e17a92c545 Ok, sometimes it's profitable to turn scalar_to_vector stuff into subreg access. 
Add a testcase.

llvm-svn: 80246
 2009-08-27 14:51:42 +00:00