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Commit Graph

151750 Commits

Author SHA1 Message Date
Simon Pilgrim
0c7889542c [X86][AVX512] Add lowering of vXi32/vXi64 ISD::ROTL/ISD::ROTR
Add support for lowering to ISD::ROTL/ISD::ROTR, including rotate by immediate

Differential Revision: https://reviews.llvm.org/D35463

llvm-svn: 308177
2017-07-17 14:11:30 +00:00
Simon Pilgrim
9727c3ed67 Fixed line endings. NFCI.
llvm-svn: 308175
2017-07-17 13:58:20 +00:00
Javed Absar
960387bcc3 [CodeGen] Add begin-end iterators to MachineInstr
Convert iteration over operands to range-loop.

Reviewed by: @rovka, @echristo
Differential Revision: https://reviews.llvm.org/D35419

llvm-svn: 308173
2017-07-17 13:15:26 +00:00
Alex Bradbury
38338cb800 [YAMLTraits] Add filename support to yaml::Input
Summary:
The current yaml::Input constructor takes a StringRef of data as its
first parameter, discarding any filename information that may have been
present when a YAML file was opened. Add an alterate yaml::Input
constructor that takes a MemoryBufferRef, which can have a filename
associated with it. This leads to clearer diagnostic messages.

Sponsored By: DARPA, AFRL

Reviewed By: arphaman

Differential Revision: https://reviews.llvm.org/D35398

Patch by: Jonathan Anderson (trombonehero)

llvm-svn: 308172
2017-07-17 11:41:30 +00:00
Simon Pilgrim
caf38eacce [X86][AVX] Fix typo in vector rotate tests
Was preventing rotate matching

llvm-svn: 308171
2017-07-17 10:35:51 +00:00
Simon Pilgrim
0809022d97 [X86][AVX512] Add constant splat vector rotate tests for D35463
llvm-svn: 308169
2017-07-17 10:09:48 +00:00
Simon Pilgrim
eb4ff6ddfe [X86][AVX512] Regenerate shift tests
llvm-svn: 308168
2017-07-17 09:53:45 +00:00
Simon Pilgrim
994cf2550f Remove unnecessary cast. NFCI.
llvm-svn: 308166
2017-07-17 09:35:03 +00:00
Craig Topper
e4819634a9 [X86] Use MSVC's __cpuidex intrinsic instead of inline assembly in getHostCPUName/getHostCPUFeatures for 32-bit builds too.
We're already using it in 64-bit builds because 64-bit MSVC doesn't support inline assembly.

As far as I know we were using inline assembly because at the time the code was added we had to support MSVC 2008 pre-SP1 while the intrinsic was added to MSVC in SP1. Now that we don't have to support that we should be able to just use the intrinsic.

llvm-svn: 308163
2017-07-17 05:16:16 +00:00
NAKAMURA Takumi
d4f88a2953 Analysis/MemorySSA.cpp: Prune unused "llvm/Transforms/Scalar.h".
llvm-svn: 308162
2017-07-17 04:31:26 +00:00
NAKAMURA Takumi
9ae52cdd82 IR/Core.cpp: Prune unused "llvm/Bitcode/BitcodeReader.h".
llvm-svn: 308161
2017-07-17 04:31:23 +00:00
NAKAMURA Takumi
9ee9169f87 Support/Path.cpp: Prune unused "llvm/BinaryFormat".
llvm-svn: 308160
2017-07-17 04:31:20 +00:00
Mandeep Singh Grang
1eee50f5a9 [COFF, ARM64] Add initial relocation types
Reviewers: compnerd, ruiu, rnk

Reviewed By: compnerd

Subscribers: mstorsjo, aemerson, javed.absar, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D34857

llvm-svn: 308154
2017-07-17 00:05:32 +00:00
Dylan McKay
35d369fdd0 [AVR] Add/remove XFAILs to get the backend passing Generic CodeGen tests
A few tests have since been fixed, and a few since now fail.

llvm-svn: 308151
2017-07-16 23:33:50 +00:00
Andrew Zhogin
5e9e3f7cd4 [DAGCombiner] Recognise vector rotations with non-splat constants
Fixes PR33691.

Differential revision: https://reviews.llvm.org/D35381

llvm-svn: 308150
2017-07-16 23:11:45 +00:00
Dylan McKay
e228272ebd [AVR] Fix a typo in the tests
llvm-svn: 308148
2017-07-16 22:31:07 +00:00
Konstantin Zhuravlyov
12b4051c8d AMDGPU: Fix amdgpu-flat-work-group-size/amdgpu-waves-per-eu check
Differential Revision: https://reviews.llvm.org/D35433

llvm-svn: 308147
2017-07-16 19:38:47 +00:00
Simon Pilgrim
931bcda64f [X86][AVX512] Add 512-bit vector rotate tests
llvm-svn: 308146
2017-07-16 19:26:49 +00:00
Konstantin Zhuravlyov
72fb813b49 AMDGPU: Remove duplicate print outs from .AMDGPU.csdata
Differential Revision: https://reviews.llvm.org/D35428

llvm-svn: 308145
2017-07-16 19:24:08 +00:00
Davide Italiano
cafe7229d5 [InstCombine] Don't violate dominance when replacing instructions.
Differential Revision:  https://reviews.llvm.org/D35376

llvm-svn: 308144
2017-07-16 18:56:30 +00:00
Simon Pilgrim
780d5afaef Strip trailing whitespace. NFCI
llvm-svn: 308143
2017-07-16 18:37:23 +00:00
Amjad Aboud
dec4b2327f [X86] X86::CMOV to Branch heuristic based optimization.
LLVM compiler recognizes opportunities to transform a branch into IR select instruction(s) - later it will be lowered into X86::CMOV instruction, assuming no other optimization eliminated the SelectInst.
However, it is not always profitable to emit X86::CMOV instruction. For example, branch is preferable over an X86::CMOV instruction when:
1. Branch is well predicted
2. Condition operand is expensive, compared to True-value and the False-value operands

In CodeGenPrepare pass there is a shallow optimization that tries to convert SelectInst into branch, but it is not enough.
This commit, implements machine optimization pass that converts X86::CMOV instruction(s) into branch, based on a conservative heuristic.

Differential Revision: https://reviews.llvm.org/D34769

llvm-svn: 308142
2017-07-16 17:39:56 +00:00
Jakub Kuderski
c153f3743a Apply explicit instantiation workaround to DominanceFrontier
This is a workaround for the same explicit instantiation bug
as in DominatorTreeBase.

llvm-svn: 308141
2017-07-16 17:29:19 +00:00
Jakub Kuderski
8500538bd3 [Dominators] Workaround explicit instantiation bug.
Some platforms have problems with emmiting constructors when class
templates get explicitly instantiated.
This patch fixes the bug reported in D35315 by replacing `= default`
with an empty constructor body.

llvm-svn: 308140
2017-07-16 17:01:40 +00:00
Simon Pilgrim
5285a49ef8 [X86] Add F16C scheduling tests
llvm-svn: 308138
2017-07-16 14:34:18 +00:00
Simon Pilgrim
677676e52f [X86] Add POPCNT scheduling tests
llvm-svn: 308137
2017-07-16 14:22:39 +00:00
Simon Pilgrim
14a8665e4f [X86] Add BMI2 scheduling tests
llvm-svn: 308136
2017-07-16 14:09:15 +00:00
Simon Pilgrim
ccd3d05139 [X86] Add BMI1 scheduling tests
llvm-svn: 308135
2017-07-16 13:59:44 +00:00
Simon Pilgrim
228e9507d2 [X86] Add LZCNT scheduling tests
llvm-svn: 308133
2017-07-16 13:40:44 +00:00
Simon Pilgrim
49eaba61d6 [X86][SSE4A] Add EXTRQ/INSERTQ values to BTVER2 scheduling model
llvm-svn: 308132
2017-07-16 12:06:06 +00:00
Simon Pilgrim
03051514f2 [X86][AVX] Regenerate tests with constant broadcast comments
llvm-svn: 308131
2017-07-16 11:43:16 +00:00
Simon Pilgrim
09bd00be13 [X86][AVX] Regenerate vector tzcnt tests with constant broadcast comments
llvm-svn: 308130
2017-07-16 11:40:23 +00:00
Simon Pilgrim
0ad8d9774f [X86][AVX] Regenerate vector idiv tests with constant broadcast comments
llvm-svn: 308129
2017-07-16 11:38:14 +00:00
Simon Pilgrim
71e142fc8a [X86][AVX] Regenerate combine tests with constant broadcast comments
llvm-svn: 308128
2017-07-16 11:36:11 +00:00
Hiroshi Inoue
fefa37bba8 fix typos in comments; NFC
llvm-svn: 308127
2017-07-16 08:11:56 +00:00
Hiroshi Inoue
a45f824308 fix typos in comments; NFC
llvm-svn: 308126
2017-07-16 07:48:48 +00:00
Craig Topper
eaeca194ba [InstSimplify] Use commutable matchers to simplify some code. NFC
llvm-svn: 308125
2017-07-16 06:57:41 +00:00
Craig Topper
b974b7eddc [InstCombine] Move (0 - x) & 1 --> x & 1 to SimplifyDemandedUseBits.
This removes a dedicated matcher and allows us to support more than just an AND masking the lower bit.

llvm-svn: 308124
2017-07-16 05:37:58 +00:00
Teresa Johnson
f69a2918e5 Fix bot failures from r308114
Finally figured out that some bots were failing from r308114
with the message:
  llvm-lto2: LTO::run failed: No available targets are compatible with this triple.
after adding in some other checking that finally caused this to show up
in the FileCheck output.

Added "REQUIRES: x86-registered-target" which should fix it.

llvm-svn: 308119
2017-07-16 00:28:22 +00:00
Teresa Johnson
52d5345e4a Attempt 2 to debug bot failures
Modify checks from r308114 even more, to see if I can narrow down
why some bots are still failing.

llvm-svn: 308116
2017-07-16 00:01:16 +00:00
Teresa Johnson
a0079c6978 Attempt to debug bot failures
Simplifying checks from r308114, to see if I can narrow down why some
bots are still failing.

llvm-svn: 308115
2017-07-15 23:31:32 +00:00
Teresa Johnson
12fb10233b Restore with fix "[ThinLTO] Ensure we always select the same function copy to import"
This restores r308078/r308079 with a fix for bot non-determinisim (make
sure we run llvm-lto in single threaded mode so the debug output doesn't get
interleaved).

llvm-svn: 308114
2017-07-15 22:58:06 +00:00
Craig Topper
1d8169119e [IR] Implement Constant::isNegativeZeroValue/isZeroValue/isAllOnesValue/isOneValue/isMinSignedValue for ConstantDataVector without going through getElementAsConstant
Summary:
Currently these methods call ConstantDataVector::getSplatValue which uses getElementsAsConstant to create a Constant object representing the element value. This method incurs a map lookup to see if we already have created such a Constant before and if not allocates a new Constant object.

This patch changes these methods to use getElementAsAPFloat and getElementAsInteger so we can just examine the data values directly.

Reviewers: spatel, pcc, dexonsmith, bogner, craig.topper

Reviewed By: craig.topper

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D35040

llvm-svn: 308112
2017-07-15 22:06:19 +00:00
Craig Topper
f47536e576 [InstCombine] Improve the expansion in SimplifyUsingDistributiveLaws to handle cases where one side doesn't simplify, but the other side resolves to an identity value
Summary:
If one side simplifies to the identity value for inner opcode, we can replace the value with just the operation that can't be simplified.

I've removed a couple now unneeded special cases in visitAnd and visitOr. There are probably other cases I missed.

Reviewers: spatel, majnemer, hfinkel, dberlin

Reviewed By: spatel

Subscribers: grandinj, llvm-commits, spatel

Differential Revision: https://reviews.llvm.org/D35451

llvm-svn: 308111
2017-07-15 21:49:49 +00:00
Simon Pilgrim
a6d8f025c0 [X86][AVX] Regenerate tests with constant broadcast comments
llvm-svn: 308110
2017-07-15 21:17:35 +00:00
Simon Pilgrim
69d490ee69 [X86][AVX] Regenerate tests with constant broadcast comments
llvm-svn: 308109
2017-07-15 20:28:09 +00:00
Simon Pilgrim
0d29e02027 Strip trailing whitespace. NFCI
llvm-svn: 308108
2017-07-15 19:29:19 +00:00
Reid Kleckner
3f9f99bb89 [CodeView] Dump BuildInfoSym and ProcSym type indices
I need to print the type index in hex so that I can match it in
FileCheck for a test I'm writing.

llvm-svn: 308107
2017-07-15 18:10:39 +00:00
Reid Kleckner
e88825c163 Fix mis-use of std::lower_bound
Binary search in C++ is such a PITA. =/

llvm-svn: 308106
2017-07-15 18:10:15 +00:00
Sanjay Patel
122bdff7b3 [InstCombine] improve (1 << x) & 1 --> zext(x == 0) folding
1. Add a one-use check to prevent increasing instruction count.
2. Generalize the pattern matching to include vector types.

llvm-svn: 308105
2017-07-15 17:26:01 +00:00