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Commit Graph

3228 Commits

Author SHA1 Message Date
Nate Begeman
85cd65b389 Change codegen for setcc to read the bit directly out of the condition
register.  Added support in the .td file for the g5-specific variant
  of cr -> gpr moves that executes faster, but we currently don't
  generate it.

llvm-svn: 21314
2005-04-18 02:43:24 +00:00
Chris Lattner
a1fd64a073 Handle ExternalSymbol operands in the PPC JIT
llvm-svn: 21312
2005-04-18 00:46:10 +00:00
Nate Begeman
ecb5b5c028 Make pattern isel default for ppc
Add new ppc beta option related to using condition registers
Make pattern isel control flag (-enable-pattern-isel) global and tristate
  0 == off
  1 == on
  2 == target default

llvm-svn: 21309
2005-04-15 22:12:16 +00:00
Andrew Lenharth
f091300df2 fix calls
llvm-svn: 21303
2005-04-14 17:34:20 +00:00
Andrew Lenharth
23a5d0bba4 a 21264 fix, and fix the operator precidence on an and -> zap check (should fix hundreds of test cases
llvm-svn: 21302
2005-04-14 16:24:00 +00:00
Duraid Madina
0c40c548c0 print negative 64 bit immediates as negative numbers, makes things a little
easier on the eyes, not that numbers like 18446744073709541376 are bad or
anything

llvm-svn: 21300
2005-04-14 10:08:01 +00:00
Duraid Madina
b8dfae92e9 oops, this stopped us turning movl r4=0xFFFFFFFF;; and rX, r4 into zxt4
llvm-svn: 21299
2005-04-14 10:06:35 +00:00
Nate Begeman
604895b03c Implement multi-way branches through logical ops on condition registers.
This can generate considerably shorter code, reducing the size of crafty
by almost 1%.  Also fix the printing of mcrf.  The code is currently
disabled until it gets a bit more testing, but should work as-is.

llvm-svn: 21298
2005-04-14 09:45:08 +00:00
Duraid Madina
eb4c15b42c we have zextloads, not sextloads!
llvm-svn: 21296
2005-04-14 08:37:32 +00:00
Nate Begeman
b707ec16b4 Add the necessary support to codegen condition register logical ops with
register allocated condition registers.  Make sure that the printed
  output is gas compatible.

llvm-svn: 21295
2005-04-14 03:20:38 +00:00
Nate Begeman
99a9840b56 Start allocating condition registers. Almost all explicit uses of CR0 are
now gone.  Next step is to get rid of the remaining ones and then start
allocating bools to CRs where appropriate.

llvm-svn: 21294
2005-04-13 23:15:44 +00:00
Nate Begeman
ae49d52006 Implement the fold shift X, zext(Y) -> shift X, Y at the target level,
where it is safe to do so.

llvm-svn: 21293
2005-04-13 22:14:14 +00:00
Nate Begeman
20b3399465 Disbale the broken fold of shift + sz[ext] for now
Move the transform for select (a < 0) ? b : 0 into the dag from ppc isel
Enable the dag to fold and (setcc, 1) -> setcc for targets where setcc
  always produces zero or one.

llvm-svn: 21291
2005-04-13 21:23:31 +00:00
Andrew Lenharth
cbf7a52768 WOW, function calls still seem to work after this.
llvm-svn: 21286
2005-04-13 17:17:28 +00:00
Andrew Lenharth
d1fee6d24a prepare for func call optimization
llvm-svn: 21285
2005-04-13 16:19:50 +00:00
Duraid Madina
b9d2d9ac63 * add the shladd instruction
* fold left shifts of 1, 2, 3 or 4 bits into adds

  This doesn't save much now, but should get a serious workout once
  multiplies by constants get converted to shift/add/sub sequences.
  Hold on! :)

llvm-svn: 21282
2005-04-13 06:12:04 +00:00
Andrew Lenharth
ec33ab6a2f add matches for SxADDL and company, as well as simplify the SxADDQ code
llvm-svn: 21281
2005-04-13 05:19:55 +00:00
Duraid Madina
67e553e521 * if ANDing with a constant of the form:
0x00000..00FFF..FF
      ^      ^
      ^      ^
    any number of
    0's followed by
    some number of
    1's

    then we use dep.z to just paste zeros over the input. For the special
    cases where this is zxt1/zxt2/zxt4, we use those instructions instead,
    because we're all about readability!!!
    that's what it's about!! readability!

  *twitch* ;D

llvm-svn: 21279
2005-04-13 04:50:54 +00:00
Andrew Lenharth
510db15268 added all flavors of zap for anding
llvm-svn: 21276
2005-04-13 03:47:03 +00:00
Chris Lattner
85c6a7bed0 Fix some mysteriously missing {}'s which cause the miscompilation of
Olden/mst, Ptrdist/bc, Obsequi, etc.

llvm-svn: 21274
2005-04-13 03:29:53 +00:00
Chris Lattner
8489ac991d remove one more occurance of this that snuck in
llvm-svn: 21271
2005-04-13 02:46:17 +00:00
Chris Lattner
5fdb103328 Remove support for ZERO_EXTEND_INREG. This pessimizes code, genering stuff
like this:

        ldah $1,1($31)
        lda $1,-1($1)
        and $0,$1,$24

instead of this:

        zap $0,252,$24

To get this back, the selector should recognize the ISD::AND case where this
happens and emit the appropriate ZAP instruction.

llvm-svn: 21270
2005-04-13 02:43:40 +00:00
Chris Lattner
a2e92e69da Remove special handling of ZERO_EXTEND_INREG. This pessimizes code, causing
things like this:

       mov r9 = 65535;;
       and r8 = r8, r9;;

To be emitted instead of:

        zxt2 r8 = r8;;

To get this back, the selector for ISD::AND should recognize this case.

llvm-svn: 21269
2005-04-13 02:41:52 +00:00
Chris Lattner
26c7c9150a Elimate handling of ZERO_EXTEND_INREG. This causes the PPC backend to emit
andi instructions instead of rlwinm instructions for zero extend, but they
seem like they would take the same time.

llvm-svn: 21268
2005-04-13 02:40:26 +00:00
Chris Lattner
f25fefd9cf Z_E_I is gone
llvm-svn: 21267
2005-04-13 02:39:05 +00:00
Nate Begeman
a56527ea5f Fold shift by size larger than type size to undef
Make llvm undef values generate ISD::UNDEF nodes

llvm-svn: 21261
2005-04-12 23:12:17 +00:00
Nate Begeman
79c8b8fd1c Implement setcc op, -1 sequences
Remove dead setcc op, 0 sequences
Coming later: generalization of op, imm

llvm-svn: 21260
2005-04-12 21:22:28 +00:00
Duraid Madina
39fcec1541 * OK, after changing to use liveIn/liveOut instead of IDEFs,
to avoid redundant mov out3=r44 type instructions, we need to
tell the register allocator the truth about out? registers.

FIXME: unfortunately, since the list of allocatable registers is immutable,
we can't simply 'delete r127' from the allocation order, say, if 'out0' is
used. The only correct thing we can do is have a linear order of regs:

out7, out6 ... out2, out1, out0, r32, r33, r34 ... r126, r127

and slide a 'window' of 96 registers along this line, depending on how many
of the out? regs a function actually uses. The only downside of this is
that the out? registers will be allocated _first_, which makes the
resulting assembly ugly. :( Note this in the README. Hope this gets fixed
soon. :) (note the 3rd person speech there)

llvm-svn: 21252
2005-04-12 18:42:59 +00:00
Andrew Lenharth
174d44f223 Get rid of idefs for arguments (oops)
llvm-svn: 21251
2005-04-12 17:47:57 +00:00
Andrew Lenharth
1b8a8331c9 Get rid of idefs for arguments
llvm-svn: 21250
2005-04-12 17:35:16 +00:00
Chris Lattner
be2dceff48 Put out* into the allocation order, allowing the register allocator to
coallesce moves into outgoing args.

llvm-svn: 21249
2005-04-12 15:12:51 +00:00
Chris Lattner
37712352c0 Make sure to realize that calls use their argument regs
llvm-svn: 21248
2005-04-12 15:12:19 +00:00
Duraid Madina
2821f99f19 stop emitting IDEFs for args - change to using liveIn/liveOut
llvm-svn: 21247
2005-04-12 14:54:44 +00:00
Nate Begeman
f96b42f1b6 Initial support for allocation condition registers
llvm-svn: 21246
2005-04-12 07:04:16 +00:00
Nate Begeman
a154deaaff Implement bitfield clears
Implement divide by negative power of two

llvm-svn: 21240
2005-04-12 00:10:02 +00:00
Nate Begeman
f31b58f145 Update PPC readme. Remove things that are done or aren't ppc specific
llvm-svn: 21232
2005-04-11 20:48:57 +00:00
Chris Lattner
55e620f08d IA64 supports this operation.
llvm-svn: 21228
2005-04-11 18:55:36 +00:00
Chris Lattner
ee715b2abc ORo sets CR0
llvm-svn: 21227
2005-04-11 15:03:48 +00:00
Chris Lattner
7d11f40ee2 Revert the previous patch, which I didn't mean to check in.
llvm-svn: 21226
2005-04-11 15:03:41 +00:00
Chris Lattner
d925c74452 Fix a minor bug (ORo didn't mark that it set CR0).
Refactor how . instructions are handled.  In particular, instead of passing
the RC flag all the way up the inheritance hierarchy, just make a new tblgen
class 'DOT' which can be added to an instruction definition.

For example, instead of this:

-def AND  : XForm_6<31,  28, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
-let Defs = [CR0] in
-def ANDo : XForm_6<31,  28, 1, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
-                   "and. $rA, $rS, $rB">;

We now have this:

+def AND  : XForm_6<31,  28, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
                    "and $rA, $rS, $rB">;

llvm-svn: 21225
2005-04-11 15:01:39 +00:00
Duraid Madina
01aaf77792 hmm, should probably change addImm() to take 64-bit arguments one day anyway.
llvm-svn: 21224
2005-04-11 07:16:39 +00:00
Nate Begeman
783fe2108e Add recording variants of ISD::AND and ISD::OR. This kills almost 1000
(1.5%) instructions in 186.crafty

llvm-svn: 21222
2005-04-11 06:34:10 +00:00
Duraid Madina
d2ae9221c7 assorted fixes:
* clean up immediates (we use 14, 22 and 64 bit immediates now. sane.)
  * fold r0/f0/f1 registers into comparisons against 0/0.0/1.0
  * fix nasty thinko - didn't use two-address form of conditional add
    for extending bools to integers, so occasionally there would be
    garbage in the result. it's amazing how often zeros are just
    sitting around in registers ;) - this should fix a bunch of tests.

llvm-svn: 21221
2005-04-11 05:55:56 +00:00
Nate Begeman
34aa7ec9cb Fix another fixme: factor out the constant fp generation code.
llvm-svn: 21207
2005-04-10 06:06:10 +00:00
Nate Begeman
b6c9b326e3 Fix 64 bit argument loading that straddles the args in regs / args on stack
boundary.

llvm-svn: 21206
2005-04-10 05:53:14 +00:00
Nate Begeman
0a43e95718 Remove unnecessary Implicit Defs. Since r0 is not in allocation, we do not
have to inform the register allocator it might be stepped on.

llvm-svn: 21202
2005-04-10 03:59:42 +00:00
Nate Begeman
f5cedbc812 Make sure that BRCOND branches can be converted into long branches too.
llvm-svn: 21198
2005-04-10 01:48:29 +00:00
Nate Begeman
ab8e705a52 Don't hand ISD::CALL nodes off to SelectExprFP. This fixes siod.
llvm-svn: 21197
2005-04-10 01:14:13 +00:00
Chris Lattner
c1bacbff9d rename getPPCOpcodeForSetCCNumber -> getPPCOpcodeForSetCCOpode to be more
correct.  Remove the EmitComparison retvalue, as it is always the first arg.

Fix a place where we incorrectly passed in the setcc opcode instead of the
setcc number, causing us to miscompile crafty.  Crafty now works!

llvm-svn: 21195
2005-04-10 01:03:31 +00:00
Nate Begeman
a2374d39df fix ISD::BRCONDTWOWAY codegen to not deference the end() iterator
llvm-svn: 21193
2005-04-09 23:35:05 +00:00
Chris Lattner
17c60891c1 Fix CodeGen/Generic/2005-05-09-GlobalInPHI.ll, which was reduced from 254.gap.
This caused the "use before a def" assertion on some programs.

With this patch, 254.gap now passes with the PPC backend.

llvm-svn: 21191
2005-04-09 22:05:17 +00:00
Chris Lattner
b630949c2e do not set the root to null if an argument is dead
llvm-svn: 21188
2005-04-09 21:23:24 +00:00
Nate Begeman
dda6155d19 Add rlwnm instruction for variable rotate
Generate rotate left/right immediate
Generate code for brcondtwoway
Use new livein/liveout functionality

llvm-svn: 21187
2005-04-09 20:09:12 +00:00
Chris Lattner
72b1964108 Fix a crash on 173.applu by asking for a constant bigger than 32-bits.
llvm-svn: 21185
2005-04-09 19:47:21 +00:00
Chris Lattner
c97f9f403f Switch this instruction selector over to using liveins and liveouts, eliminating
implicit defs on entry to the function.  yaay :)

llvm-svn: 21184
2005-04-09 16:32:30 +00:00
Chris Lattner
fd4d6e0847 Use live out sets for return values instead of imp_defs, which is cleaner and faster.
llvm-svn: 21181
2005-04-09 15:23:56 +00:00
Duraid Madina
2d3e52576d ok, the "ia64 has a boatload of registers" joke stopped being funny today ;)
* fix overallocation of integer (stacked) registers: we can't allocate
  registers for local use if they are required as output registers

this fixes 'toast' in the test suite, and all sorts of larger programs
like bzip2 etc.

llvm-svn: 21178
2005-04-09 11:53:00 +00:00
Nate Begeman
98bcb13bfa Optimize FSEL a bit for fneg arguments. This fixes the recently added test
case so that we emit

_test_fneg_sel:
.LBB_test_fneg_sel_0:   ;
        fsel f1, f1, f3, f2
        blr

instead of:

_test_fneg_sel:
.LBB_test_fneg_sel_0:   ;
        fneg f0, f1
        fneg f0, f0
        fsel f1, f0, f3, f2
        blr

llvm-svn: 21177
2005-04-09 09:33:07 +00:00
Chris Lattner
3fde68ea7a Fix CodeGen/SparcV9/2005-05-09-GEP-Crash.ll a crash on some specfp program
lets hope this doesn't break other programs with induced entropy

llvm-svn: 21174
2005-04-09 06:27:14 +00:00
Chris Lattner
39f963f968 This target does not support/want ISD::BRCONDTWOWAY
llvm-svn: 21164
2005-04-09 03:22:37 +00:00
Chris Lattner
c80baf5567 This target does not yet support ISD::BRCONDTWOWAY
llvm-svn: 21163
2005-04-09 03:22:30 +00:00
Nate Begeman
99fb6814bd 64b: Expand S/UREM
32b: No longer pattern match fneg(fsub(fmul)) as fnmsub
     Pattern match fsub a, mul(b, c) as fnmsub
     Pattern match fadd a, mul(b, c) as fmadd
Those changes speed up hydro2d by 2.5%, distray by 6%, and scimark by 8%

llvm-svn: 21161
2005-04-09 03:05:51 +00:00
Nate Begeman
95e1b860a1 Fix 64b shifts
llvm-svn: 21159
2005-04-08 23:45:01 +00:00
Nate Begeman
3fca499b8d Match Mac OS X 64 bit calling conventions
llvm-svn: 21157
2005-04-08 21:26:05 +00:00
Andrew Lenharth
6eff2083b5 collect a few statistics, factor constants (constant loading and mult), fix logic operation pattern matchs, supress FP div when int dividing by a constant
llvm-svn: 21156
2005-04-08 17:28:49 +00:00
Duraid Madina
e7412561bf fix bogus division-by-power-of-2 (was wrong for negative input, adds extr insn)
fix hack in division (clean up frcpa instruction)

llvm-svn: 21153
2005-04-08 10:01:48 +00:00
Nate Begeman
6875356db1 Optimized code sequences for setcc reg, 0
Optimized code sequence for (a < 0) ? b : 0

llvm-svn: 21150
2005-04-07 20:30:01 +00:00
Andrew Lenharth
b1b7ef0979 Alpha zero extends setcc results
llvm-svn: 21149
2005-04-07 20:11:32 +00:00
Chris Lattner
352dd3e579 PowerPC zero extends setcc results
llvm-svn: 21147
2005-04-07 19:41:49 +00:00
Chris Lattner
583dcc66f2 X86 zero extends setcc results
llvm-svn: 21146
2005-04-07 19:41:46 +00:00
Andrew Lenharth
c3e5c42b86 fix a small optimization opertunity and make gcc happy
llvm-svn: 21143
2005-04-07 18:15:28 +00:00
Andrew Lenharth
469244a2b4 fixup magic constant making code. tested by thousands of random divisions.... by 10000. ok, so random divisors would be good too, but this at least fixes some things
llvm-svn: 21140
2005-04-07 17:19:16 +00:00
Andrew Lenharth
61215a78fb lowercase instructions, makes diff happier
llvm-svn: 21139
2005-04-07 17:17:48 +00:00
Andrew Lenharth
3d1228500d It wasn't happy about this either
llvm-svn: 21133
2005-04-07 14:18:13 +00:00
Andrew Lenharth
ce0dcea720 Yea, it wasn't happy
llvm-svn: 21132
2005-04-07 13:55:53 +00:00
Duraid Madina
ab6e2cfaeb teach asmprinter to print s8/s14 operands
llvm-svn: 21131
2005-04-07 12:34:36 +00:00
Duraid Madina
ed8eb83203 codegen immediate forms of add/sub/shift
llvm-svn: 21130
2005-04-07 12:33:38 +00:00
Duraid Madina
5c4a7b68b3 add immediate forms of add, sub, shift
llvm-svn: 21129
2005-04-07 12:32:24 +00:00
Nate Begeman
b890f32ac9 Pattern match bitfield insert, which helps shift long by immediate, among
other things.

llvm-svn: 21127
2005-04-06 23:51:40 +00:00
Nate Begeman
6c5e4c3bb1 Fix some shift bugs
llvm-svn: 21126
2005-04-06 22:42:08 +00:00
Alkis Evlogimenos
242fe17bc4 Make these 64 bit constants so that this compiles on x86-32 as well.
llvm-svn: 21125
2005-04-06 22:09:40 +00:00
Andrew Lenharth
abf46a4f5e added sdiv by 2^k and works for neg divisors also
llvm-svn: 21124
2005-04-06 22:03:13 +00:00
Andrew Lenharth
5c71402202 fix copy/paste errors, and add imm support to SxADDQ and SxSUBQ
llvm-svn: 21121
2005-04-06 20:59:59 +00:00
Chris Lattner
40ee8a062b Fix SingleSource/Regression/C/2005-05-06-LongLongSignedShift.c, we were not
properly sign extending the top of the result of a 64-bit shift right by
a constant > 32.

llvm-svn: 21120
2005-04-06 20:59:35 +00:00
Andrew Lenharth
9f65102f9b Added Nate's div by constant stuff, also scaled operations!
llvm-svn: 21116
2005-04-06 20:25:34 +00:00
Chris Lattner
7c0786dda8 Fix a namespace issue, reported by Vladimir Merzliakov!
llvm-svn: 21115
2005-04-06 19:45:39 +00:00
Duraid Madina
5fa854a7fe steal sampo's div-by-constant-power-of-2 stuff
thanks sampo!!

llvm-svn: 21113
2005-04-06 09:55:17 +00:00
Duraid Madina
1d156293cb add fms instruction
llvm-svn: 21112
2005-04-06 09:54:09 +00:00
Nate Begeman
98251d6a1c Fixed version of optimized integer divide is now fixed. Calculate the
quotient, not the remainder.  Also, make sure to remove the old div operand
from the ExprMap and let SelectExpr insert the new one.

llvm-svn: 21111
2005-04-06 06:44:57 +00:00
Duraid Madina
2db29b8016 lie a bit and say that r1/r12 (GP/SP) _aren't_ callee-save, as we take
care of this ourselves

llvm-svn: 21110
2005-04-06 06:18:36 +00:00
Duraid Madina
62c4de8d62 make sure 'special' registers don't get allocated
llvm-svn: 21109
2005-04-06 06:17:54 +00:00
Chris Lattner
c87ff88efb Add (untested) support for MULHS and MULHU.
llvm-svn: 21107
2005-04-06 04:21:07 +00:00
Chris Lattner
ba7cdbebb1 add signed versions of the extra precision multiplies
llvm-svn: 21106
2005-04-06 04:19:22 +00:00
Nate Begeman
aee0f81849 Turn off the div -> mul optimization until it works correctly 100% of the
time.

llvm-svn: 21105
2005-04-06 03:36:33 +00:00
Nate Begeman
b44597771c Add support for MULHS and MULHU nodes
Have LegalizeDAG handle SREM and UREM for us
Codegen SDIV and UDIV by constant as a multiply by magic constant instead
of integer divide, which is very slow.

llvm-svn: 21104
2005-04-06 00:25:27 +00:00
Andrew Lenharth
613a940af8 added lowerargs support for varargs
llvm-svn: 21101
2005-04-05 20:51:46 +00:00
Nate Begeman
82ff41c342 Behold, rlwinm with certain immediate arguments is printed as the much more
readable slwi or srwi (shift left/right word immediate).

llvm-svn: 21099
2005-04-05 18:19:50 +00:00
Nate Begeman
581553fd21 Fix cut & paste errors (32->64), and codegen float->int more optimally.
llvm-svn: 21098
2005-04-05 17:32:30 +00:00
Tanya Lattner
4d8f553a82 Updated to use dep analyzer.
llvm-svn: 21097
2005-04-05 16:36:44 +00:00
Nate Begeman
152dbbe856 Remove 64 bit simple ISel, it never worked correctly
Add initial (buggy) implementation of 64 bit pattern ISel

llvm-svn: 21096
2005-04-05 08:51:15 +00:00
Nate Begeman
a18a26f47c Back out the previous change to SelectBranchCC, since there are cases it
could miscompile.  A correct solution will be found in the near future.

llvm-svn: 21095
2005-04-05 04:32:16 +00:00
Nate Begeman
358dee806e Rename canUseAsImmediateForOpcode to getImmediateForOpcode to better
indicate that it is not a boolean function.
Properly emit the pseudo instruction for conditional branch, so that we
  can fix up conditional branches whose displacements are too large.
Reserve the right amount of opcode space for said pseudo instructions.

llvm-svn: 21094
2005-04-05 04:22:58 +00:00
Nate Begeman
ede4abc899 Implement SDIV by power of 2 as srawi/addze rather than load imm, divw
llvm-svn: 21091
2005-04-05 00:15:08 +00:00
Nate Begeman
00002553ba Pattern match fp mul-add, mul-sub, neg-mul-add, and neg-mul-sub
llvm-svn: 21090
2005-04-04 23:40:36 +00:00
Nate Begeman
682fd51f9c Add support for multiply-add, multiply-sub, and their negated versions
llvm-svn: 21089
2005-04-04 23:01:51 +00:00
Nate Begeman
d9af5c4fc5 Make sure that arg regs used by the call instruction are marked as such, so
that regalloc doesn't cleverly reuse early arg regs loading later arg regs.
This fixes almost all outstanding failures in the pattern isel.

llvm-svn: 21086
2005-04-04 22:17:48 +00:00
Nate Begeman
ce13bceb2a Remove unnecessary register copy now that regalloc is fixed
llvm-svn: 21085
2005-04-04 21:48:13 +00:00
Nate Begeman
bde3612ce3 i1 loads should also be from the low byte of the argument word.
llvm-svn: 21077
2005-04-04 09:09:00 +00:00
Nate Begeman
77427b1e77 Fix i64 return, fix CopyFromReg
llvm-svn: 21076
2005-04-04 06:52:38 +00:00
Duraid Madina
920aea2fa7 fix SREM/UREM, which gave incorrect results for x%y if x was zero. This is
an ugly hack, but it seems to work. I should fix this properly and add a test
as well.

fixes multisource/obsequi (maybe others)

llvm-svn: 21075
2005-04-04 05:05:52 +00:00
Duraid Madina
d896a18d33 add implicit use op
llvm-svn: 21074
2005-04-04 04:50:57 +00:00
Nate Begeman
b2e5a962ff Full varargs support. All of UnitTests now passes
llvm-svn: 21070
2005-04-03 23:11:17 +00:00
Nate Begeman
1a5aaf6009 Pass the correct value for the chain to the store
llvm-svn: 21066
2005-04-03 22:22:56 +00:00
Nate Begeman
82d17d0e70 Fix SHL_PARTS
Start implementation of integer varargs

llvm-svn: 21065
2005-04-03 22:13:27 +00:00
Andrew Lenharth
320fff1cbe is this simpler? I think it is simpler.
llvm-svn: 21064
2005-04-03 20:35:21 +00:00
Andrew Lenharth
4be5502eb4 fix 101 regressions
llvm-svn: 21063
2005-04-03 18:24:50 +00:00
Duraid Madina
bfbfb0e4c7 .bss is no problem here.
llvm-svn: 21061
2005-04-03 14:52:01 +00:00
Nate Begeman
127bd62534 Keeping up with the Joneses.
Implement not, nor, nand, and eqv

llvm-svn: 21060
2005-04-03 11:20:20 +00:00
Andrew Lenharth
c16ede8779 Select optimization
llvm-svn: 21051
2005-04-02 22:32:39 +00:00
Andrew Lenharth
bd19c1d25f Try several things. 1) drop /i from FP ops 2) factor out FP to Int moves and provide 21264 support for those 3) match not 4) match ornot andnot xornot
llvm-svn: 21046
2005-04-02 21:06:51 +00:00
Andrew Lenharth
08e5b4f996 FNEG/FABS/UNDEF
llvm-svn: 21029
2005-04-02 19:11:07 +00:00
Andrew Lenharth
04fd317736 FNEG/FABS
llvm-svn: 21028
2005-04-02 19:04:58 +00:00
Duraid Madina
63f75bdf49 ia64 asmprinter fixes:
- turn off assembler's autoalignment
  - set FunctionAddrPrefix/Suffix so that .data8 entries pointing to
    functions have their value wrapped in @fptr(), so that a function
    descriptor will be materialized for that function.

llvm-svn: 21025
2005-04-02 12:30:47 +00:00
Duraid Madina
5367cc3b49 support IDEF, fnegabs (thanks sampo)
llvm-svn: 21023
2005-04-02 10:33:53 +00:00
Duraid Madina
81675e4031 add fnegabs op
llvm-svn: 21022
2005-04-02 10:06:27 +00:00
Nate Begeman
402c04ff16 Set shift amount to Extend
Implement ISD::FABS and ISD::FNEG nodes
Implement SHL_PARTS, SRL_PARTS, and SRA_PARTS
Generate PowerPC 'fneg', 'fabs', and 'fnabs' instructions

llvm-svn: 21018
2005-04-02 05:59:34 +00:00
Chris Lattner
8f30d63c1a add support for FABS and FNEG
llvm-svn: 21015
2005-04-02 05:30:17 +00:00
Duraid Madina
333132da85 add support FNEG and FABS
llvm-svn: 21012
2005-04-02 05:18:38 +00:00
Chris Lattner
a5d4718875 This target doesn't support fabs/fneg yet.
llvm-svn: 21010
2005-04-02 05:03:24 +00:00
Chris Lattner
71434aa2dd add an fabs instr
llvm-svn: 21006
2005-04-02 04:31:56 +00:00
Chris Lattner
8ee783d9f0 Add support for 64-bit shifts.
llvm-svn: 21005
2005-04-02 04:01:14 +00:00
Nate Begeman
8d60ca616f Fix i64 returns
Generate PowerPC 'subfic' instruction when appropriate

llvm-svn: 20995
2005-04-02 00:42:16 +00:00
Chris Lattner
67da3fdb70 Add support for ISD::UNDEF to the X86 be
llvm-svn: 20990
2005-04-01 22:46:45 +00:00
Nate Begeman
4034852ba9 Add ISD::UNDEF node
Teach the SelectionDAG code how to expand and promote it
Have PPC32 LowerCallTo generate ISD::UNDEF for int arg regs used up by fp
  arguments, but not shadowing their value.  This allows us to do the right
  thing with both fixed and vararg floating point arguments.

llvm-svn: 20988
2005-04-01 22:34:39 +00:00
Chris Lattner
375f5e6ed5 Fix another PATypeHolder error, contributed by Bill Wendling!
llvm-svn: 20983
2005-04-01 15:41:30 +00:00
Duraid Madina
48ef32d6d3 repair mindless SELECT waste.
llvm-svn: 20982
2005-04-01 10:35:00 +00:00
Nate Begeman
244b36582a Fix Olden/bh, CR0 was being set in the wrong order
LowerCallTo and ISD::CALL are going to need to be modified, regs are being
set in the wrong order.

llvm-svn: 20981
2005-04-01 08:57:43 +00:00
Nate Begeman
f3ead25b68 Also apply Chris's fix to FP select and SETCC
llvm-svn: 20979
2005-04-01 07:21:30 +00:00
Chris Lattner
0cd0036523 Move the selection of the arms of the select operation up to the conditional
part to make sure we get the side effects and to avoid confusing the CFG.

llvm-svn: 20977
2005-04-01 07:10:02 +00:00
Nate Begeman
e82a2d7373 Fix stores to global addresses
Fix calls with no arguments

llvm-svn: 20975
2005-04-01 05:57:17 +00:00
Nate Begeman
9d224ae29b Support indexed loads and stores. This drops Shootout/matrix time from
18.8 to 14.8 seconds.  The Pattern ISel is now often faster than the
Simple ISel, esp. on memory intensive code.

llvm-svn: 20973
2005-04-01 04:45:11 +00:00
Nate Begeman
af7c6366d7 Implement FP_TO_SINT and FP_TO_UINT
llvm-svn: 20972
2005-04-01 02:59:27 +00:00
Nate Begeman
552f6f5f4e Add support for adding 0.0 and -0.0 to the constant pool, since we lie and
say that we support them, for the purposes of generating fsel instructions.

llvm-svn: 20970
2005-04-01 01:08:07 +00:00
Nate Begeman
18b3394f4d Factor out common code, support FP comparison in folded SetCC
llvm-svn: 20969
2005-04-01 00:32:34 +00:00
Nate Begeman
fc89059914 fsel generation for f32 and f64 select
generate compare immediate for integer compare with constant
fold setcc into branch
fold setcc into select

Code generation quality for Shootout is now on par with the Simple ISel

llvm-svn: 20968
2005-03-31 23:55:40 +00:00
Andrew Lenharth
1ba016ab6f make fp div trick dependend on flag
llvm-svn: 20967
2005-03-31 22:02:25 +00:00
Andrew Lenharth
7db3834ecf PCMarker support for DAG and Alpha
llvm-svn: 20965
2005-03-31 21:24:06 +00:00
Duraid Madina
47fed18416 Assorted fixes:
* Stop being pessimistic about output register allocation
  * Start to handle function descriptors: compute target GPs and so on
  when doing indirect calls etc. Not there yet, though. For the moment,
  we try to use _indirect_ branches wherever possible, to stress test
  function descriptors.
  * FP divide-by-zero should work now
  * add varargs (it doesn't work, though)

At this point, all of SingleSource passes (modulo C++ tests that are due
to issues with the CFE, see note in the README.) Much of MultiSource also
passes although there's still a ton of bugs around. Something for me to
work on tomorrow, then. :)

llvm-svn: 20960
2005-03-31 12:31:11 +00:00
Duraid Madina
f2d1865c74 * declare local common symbols as such (.lcomm, not merely .common)
* begin great adventure into correct function descriptor materialization

llvm-svn: 20956
2005-03-31 07:40:24 +00:00
Duraid Madina
03efd3bea9 daintyness
llvm-svn: 20955
2005-03-31 07:36:43 +00:00
Duraid Madina
11ff0a2a5f add what we need to fudge a 'floating point conditional move', this is
used to get FP div-by-zero working properly (shunt the right answer
depending on how frcpa sets its predicate output)

llvm-svn: 20954
2005-03-31 07:32:32 +00:00
Nate Begeman
17ff2b3a87 Pass the correct values to the chain argument for node construction during
LowerCallTo.
Handle ISD::ADD in SelectAddr, allowing us to have nonzero immediates for
loads and stores, amazing!

llvm-svn: 20946
2005-03-31 02:05:53 +00:00
Nate Begeman
de4aac1374 Rewrite LowerCallTo and Select(ISD::CALL) to properly handle float varargs
Tell the SelectionDAG ISel to expand SEXTLOAD of i1 and i8, rather than
  complicate the code in ISD::SEXTLOAD to do it by hand
Combine the FP and Int ISD::LOAD codegen
Generate better code for constant pool loads

As a result, all of Shootout, and likely many other programs are now
working.

llvm-svn: 20945
2005-03-31 00:15:26 +00:00
Nate Begeman
9c5480beeb Fix calls whose arguments fit entirely in registers to not break the Chain.
Implement SINT_TO_FP and UINT_TO_FP
Remove some dead code from the simple ISel

llvm-svn: 20944
2005-03-30 19:38:35 +00:00
Andrew Lenharth
91bd9033c6 yea, fine Duraid
llvm-svn: 20942
2005-03-30 18:22:52 +00:00
Nate Begeman
c877844625 Fix frame index code to generate legal PowerPC instructions. About half of
Shootout now works.

llvm-svn: 20940
2005-03-30 02:23:08 +00:00
Nate Begeman
ec87399dac Fix external symbol printing in the AsmPrinter. Tell the ISel that we
don't support things like memcpy directly.  This allows a handful of the
Shootout programs to work, yay!

llvm-svn: 20939
2005-03-30 01:45:43 +00:00
Chris Lattner
46c4246df1 don't depend on the cfg being set up yet
llvm-svn: 20936
2005-03-30 01:10:00 +00:00
Nate Begeman
8eddad3985 Fix BranchCC (it's still dumb), and implement FP select (also dumb)
llvm-svn: 20935
2005-03-29 22:48:55 +00:00
Nate Begeman
43b127ca0a Implement integer select and i1 sign extend
llvm-svn: 20934
2005-03-29 22:24:51 +00:00
Nate Begeman
d5d90ec76b Implement SetCC, fix ZERO_EXTEND_INREG
llvm-svn: 20933
2005-03-29 21:54:38 +00:00
Tanya Lattner
bc14e623e3 Compare dependence analysis with llvm instructions versus machine instrutions. the problem with using machine instructions and alias analysis is that aa does not handle tmp instructions.
llvm-svn: 20931
2005-03-29 20:35:10 +00:00
Tanya Lattner
7edde71619 Dependence analyzer that just determines dependences within a loop for loads and stores using alias analysis.
llvm-svn: 20930
2005-03-29 20:33:42 +00:00
Andrew Lenharth
21c4590f96 Fix up some types and constants
llvm-svn: 20928
2005-03-29 19:24:04 +00:00
Chris Lattner
3759d20b0f fix a warning in the optimized build
llvm-svn: 20920
2005-03-29 15:13:27 +00:00
Nate Begeman
62e458272f Implement div, rem, and frameindex
llvm-svn: 20907
2005-03-29 00:03:27 +00:00
Nate Begeman
734a61f057 Pattern ISel: fix argument loading for i64s (thanks chris)
Simple  ISel: fix i64 subtract

llvm-svn: 20903
2005-03-28 23:08:54 +00:00
Nate Begeman
32d1caae6d Remove fake instruction 'subc' (mnemonic for subfc).
More pattern isel updates

llvm-svn: 20902
2005-03-28 22:28:37 +00:00
Nate Begeman
2ab66f55b6 Implement proper loads and zero-extends of all types
llvm-svn: 20897
2005-03-28 19:36:43 +00:00
Duraid Madina
7b5f67baf9 Emit .global @function and .global @object entries so the Intel ias
assembler may be used; identify LLVM output as such.

llvm-svn: 20892
2005-03-28 15:21:43 +00:00
Nate Begeman
6b0fbf811f Fix that pesky floats in integer regs problem by assigning the f32 type to
the correct register class.  Also remove the loading of float data into int
regs part of varargs; it will need to be implemented differently later.

llvm-svn: 20857
2005-03-26 08:25:22 +00:00
Nate Begeman
31d175d1e5 Get closer to having varargs working. There's still something strange
going on with copies between floating point and integer register files
being generated.  Once that is solved, varargs will be done.

llvm-svn: 20856
2005-03-26 07:46:36 +00:00
Nate Begeman
69742e6ea1 Make 64bit args and float args work correct with calls. Thanks to Chris
for explaining EXTRACT_ELEMENT to me.

llvm-svn: 20847
2005-03-26 02:17:46 +00:00
Nate Begeman
f821401825 Change interface to LowerCallTo to take a boolean isVarArg argument.
llvm-svn: 20842
2005-03-26 01:29:23 +00:00
Nate Begeman
d3b5925b38 Next round of pattern isel changes, mostly dealing with calls.
llvm-svn: 20841
2005-03-26 01:28:53 +00:00
Nate Begeman
4106e81966 Correct a documention link
llvm-svn: 20840
2005-03-26 01:28:05 +00:00
Nate Begeman
ba1cd37734 Support global addresses and fix call returns. Varargs still aren't
handled correctly for floating point arguments, or more than 8 arguemnts.
This does however, allow hello world to run.

llvm-svn: 20832
2005-03-25 08:34:25 +00:00
Nate Begeman
6b11098886 Implement next round of Pattern ISel fixes
1. void returns
2. multiplies
3. calls

llvm-svn: 20822
2005-03-24 23:35:30 +00:00
Nate Begeman
613e54d5f0 Fix an incorrect argument being passed to BuildMI for indirect calls.
llvm-svn: 20821
2005-03-24 23:34:38 +00:00
Nate Begeman
4584ca0554 Commit Gabor Greif's patch to use iterators in lowering intrinsics.
llvm-svn: 20816
2005-03-24 20:07:16 +00:00
Chris Lattner
ad07b1bc54 eliminate dead variables, patch contributed by Gabor Greif!
llvm-svn: 20812
2005-03-24 17:32:20 +00:00
Nate Begeman
833c1d0994 Implement more of the PPC32 Pattern ISel:
1) dynamic stack alloc
2) loads
3) shifts
4) subtract
5) immediate form of add, and, or, xor
6) change flag from -pattern-isel to -enable-ppc-pattern-isel

Remove dead arguments from getGlobalBaseReg in the simple ISel

llvm-svn: 20810
2005-03-24 06:28:42 +00:00
Chris Lattner
a42c4a0874 Fix silly "no newline at end of file" warning
llvm-svn: 20809
2005-03-24 06:16:18 +00:00
Chris Lattner
56f3525a1d Fix compilation errors, patch contributed by the fabulous Bill Wendling!
llvm-svn: 20808
2005-03-24 05:13:53 +00:00
Chris Lattner
2e2035aa72 fix a compilation error, patch contributed by Bill Wendling!
llvm-svn: 20807
2005-03-24 05:12:48 +00:00
Nate Begeman
0e77845b7e Addition of the PPC32 Pattern ISel. While it is far from complete, it will
be brought up to parity with the current simple ISel in the coming days.
Currently, -pattern-isel is required to trigger it.

llvm-svn: 20805
2005-03-24 04:41:43 +00:00
Nate Begeman
175a9f1cc6 Remove comments that are now meaningless from the pattern ISels, at Chris's
request.

llvm-svn: 20804
2005-03-24 04:39:54 +00:00
Andrew Lenharth
b1bd2e2900 don't lie to the register allocator
llvm-svn: 20784
2005-03-23 15:20:01 +00:00
Tanya Lattner
d7b8fb8263 Added alias analysis.
Fixed many many bugs.
This now works on almost all Singlesource , and most of MultiSource.

llvm-svn: 20780
2005-03-23 01:47:20 +00:00
Andrew Lenharth
61312ca088 hum, it is good to use real instructions
llvm-svn: 20769
2005-03-22 16:42:52 +00:00
Andrew Lenharth
5bd65ee784 two things: 1)evilness reduction patch, reduces the number of instructions hiding in the small jump CC moving code. 2)implement div of small data types by FP DIV (also reduces evilness and should speed things up)
llvm-svn: 20756
2005-03-22 00:24:07 +00:00
Misha Brukman
04d6d0666d We may be adding functions to the Module during initialization, so
conservatively, it's modified

llvm-svn: 20735
2005-03-21 19:22:14 +00:00
Tanya Lattner
156e5a6897 Make this method non-const. Making it const causes the const version of
getIGroup to be called instead of the non-const one.  These two methods
have (??) different behavior, so this change fixes bugs.

llvm-svn: 20724
2005-03-21 06:07:43 +00:00
Chris Lattner
f53c9e2578 Fix the 3 regressions last night, due to my buggy patch from yesterday.
llvm-svn: 20689
2005-03-19 17:35:11 +00:00
Alkis Evlogimenos
d8f23f17f0 Stop using deprecated interface.
llvm-svn: 20679
2005-03-19 09:22:17 +00:00
Chris Lattner
35084f46a3 remove use of getPrev() and getNext() on ilist nodes.
llvm-svn: 20673
2005-03-18 16:12:37 +00:00
Duraid Madina
ad26d89f4a typo/denial
llvm-svn: 20663
2005-03-17 20:23:27 +00:00
Duraid Madina
341917d75b clean up warnings when building in release mode
llvm-svn: 20658
2005-03-17 19:00:40 +00:00
Duraid Madina
0b84eec44b OK, IA64 is statically linked into llc
llvm-svn: 20655
2005-03-17 18:37:05 +00:00
Duraid Madina
08bd58412a build the IA64 target as a .so for now
llvm-svn: 20654
2005-03-17 18:29:04 +00:00