Evan Cheng
bc4588c439
Re-commit 117518 and 117519 now that ARM MC test failures are out of the way.
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llvm-svn: 117531
2010-10-28 06:47:08 +00:00
Evan Cheng
fdc80a0316
Revert 117518 and 117519 for now. They changed scheduling and cause MC tests to fail. Ugh.
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llvm-svn: 117520
2010-10-28 02:00:25 +00:00
Evan Cheng
5c358e02ea
- Assign load / store with shifter op address modes the right itinerary classes.
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- For now, loads of [r, r] addressing mode is the same as the
[r, r lsl/lsr/asr #] variants. ARMBaseInstrInfo::getOperandLatency() should
identify the former case and reduce the output latency by 1.
- Also identify [r, r << 2] case. This special form of shifter addressing mode
is "free".
llvm-svn: 117519
2010-10-28 01:49:06 +00:00
Dale Johannesen
b78530f9b0
Fix pastos in handling of AVX cvttsd2si, PR8491.
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Bruno, please review, but I'm pretty sure this is right.
Patch by Alex Mac!
llvm-svn: 117514
2010-10-28 00:35:54 +00:00
Owen Anderson
e75f7c5419
Add correct NEON encodings for vtbl and vtbx.
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llvm-svn: 117513
2010-10-28 00:18:46 +00:00
Owen Anderson
008116cb71
Add correct NEON encodings for vext, vtrn, vuzp, and vzip.
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llvm-svn: 117512
2010-10-27 23:56:39 +00:00
Bob Wilson
2f8b69b196
Fix compiler warnings about signed/unsigned comparisons.
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llvm-svn: 117511
2010-10-27 23:49:00 +00:00
Evan Cheng
44d2802e1d
Shifter ops are not always free. Do not fold them (especially to form
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complex load / store addressing mode) when they have higher cost and
when they have more than one use.
llvm-svn: 117509
2010-10-27 23:41:30 +00:00
Jim Grosbach
86ecfda983
Refactor ARM STR/STRB instruction patterns into STR{B}i12 and STR{B}rs, like
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the LDR instructions have. This makes the literal/register forms of the
instructions explicit and allows us to assign scheduling itineraries
appropriately. rdar://8477752
llvm-svn: 117505
2010-10-27 23:12:14 +00:00
Owen Anderson
9437a20a72
Provide correct encodings for NEON vcvt, which has its own special immediate encoding
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for specifying fractional bits for fixed point conversions.
llvm-svn: 117501
2010-10-27 22:49:00 +00:00
Jim Grosbach
1d5b71b3cc
Trailing whitespace
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llvm-svn: 117496
2010-10-27 21:39:08 +00:00
Owen Anderson
d28d229ded
Provide correct encodings for the get_lane and set_lane variants of vmov.
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llvm-svn: 117495
2010-10-27 21:28:09 +00:00
Kevin Enderby
a53cc6a764
Added the x86 instruction ud2b (2nd official undefined instruction).
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llvm-svn: 117485
2010-10-27 20:46:49 +00:00
Jim Grosbach
db7ba38ca4
JIT imm12 encoding for constant pool entry references.
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llvm-svn: 117483
2010-10-27 20:39:40 +00:00
Bob Wilson
cdc8dff3ac
SelectionDAG shuffle nodes do not allow operands with different numbers of
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elements than the result vector type. So, when an instruction like:
%8 = shufflevector <2 x float> %4, <2 x float> %7, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
is translated to a DAG, each operand is changed to a concat_vectors node that appends 2 undef elements. That is:
shuffle [a,b], [c,d] is changed to:
shuffle [a,b,u,u], [c,d,u,u]
That's probably the right thing for x86 but for NEON, we'd much rather have:
shuffle [a,b,c,d], undef
Teach the DAG combiner how to do that transformation for ARM. Radar 8597007.
llvm-svn: 117482
2010-10-27 20:38:28 +00:00
Jim Grosbach
0df1207e99
ARM JIT fix for LDRi12 and company.
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llvm-svn: 117478
2010-10-27 19:55:59 +00:00
Owen Anderson
7c46fcfee4
Provide correct NEON encodings for vdup.
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llvm-svn: 117475
2010-10-27 19:25:54 +00:00
Michael J. Spencer
5518dda87e
x86-Win32: Switch ftol2 calling convention from stdcall to C.
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llvm-svn: 117474
2010-10-27 18:52:38 +00:00
Jim Grosbach
5d4415c6b0
The new LDR* instruction patterns should handle the necessary encoding of
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operands in the TableGen'erated bits, so we don't need to do the additional
magic explicitly.
llvm-svn: 117461
2010-10-27 17:52:51 +00:00
Owen Anderson
c8757eb137
Add correct NEON encodings for vsli and vsri.
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llvm-svn: 117459
2010-10-27 17:40:08 +00:00
Owen Anderson
e64b7187a9
Add correct NEON encodings for vsra and vrsra.
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llvm-svn: 117458
2010-10-27 17:29:29 +00:00
Jim Grosbach
09eab01a37
The immediate operands of an LDRi12 instruction doesn't need the addrmode2
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encoding tricks. Handle the 'imm doesn't fit in the insn' case.
llvm-svn: 117454
2010-10-27 16:50:31 +00:00
Kevin Enderby
74a2614673
Yet another tweak to X86 instructions to add ud2a as an alias to ud2
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(still to add ud2b).
llvm-svn: 117435
2010-10-27 03:01:02 +00:00
Kevin Enderby
d22f3b9de7
Another tweak to X86 instructions to add the missing flex instruction (without
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the wait prefix).
llvm-svn: 117434
2010-10-27 02:53:04 +00:00
Kevin Enderby
e812b356cc
Tweaks to X86 instructions to allow the 'w' suffix in places it makes
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sense, when the instruction takes the 16-bit ax register or m16 memory
location. These changes to llvm-mc matches what the darwin assembler
allows for these instructions. Done differently than in r117031 that
caused a valgrind error which was later reverted.
llvm-svn: 117433
2010-10-27 02:32:19 +00:00
Jim Grosbach
5ccda16fe2
LDRi12 machine instructions handle negative offset operands normally (simple
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integer values), not with the addrmode2 encoding.
llvm-svn: 117429
2010-10-27 01:19:41 +00:00
Kevin Enderby
d5235bb45c
Added some aliases to the fcomip and fucompi Intel instructions. So that llvm-mc
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will accept versions that the darwin assembler allows. Forms ending in "pi" and
forms without all the operands.
llvm-svn: 117427
2010-10-27 00:59:28 +00:00
Jim Grosbach
6453c7cdf9
One more spot where the new arm mode LDR instruction representation
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doesn't need the additional addrmode2 register operand. Missed it the first
time around.
llvm-svn: 117421
2010-10-27 00:38:16 +00:00
Wesley Peck
854507453a
Adding disassembler to the MicroBlaze backend.
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llvm-svn: 117420
2010-10-27 00:23:01 +00:00
Jim Grosbach
4d4caf1384
Split ARM::LDRB into LDRBi12 and LDRBrs. Adjust accordingly. Continuing on
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rdar://8477752.
llvm-svn: 117419
2010-10-27 00:19:44 +00:00
Jim Grosbach
625e128d29
Since I parameterized this bit, I should probably actually use said parameter.
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llvm-svn: 117418
2010-10-26 23:58:04 +00:00
Dale Johannesen
e7f07349e4
Use a MemIntrinsicSDNode for ISD::PREFETCH, which touches
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memory, so a MachineMemOperand is useful (not propagated
into the MachineInstr yet). No functional change except
for dump output.
llvm-svn: 117413
2010-10-26 23:11:10 +00:00
Owen Anderson
1dc05f20e2
Add correct NEON encodings for vqshl, vqshrn, vqshrun, vqrshl, vqshrn, and vqrshrun.
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llvm-svn: 117411
2010-10-26 22:50:46 +00:00
Jim Grosbach
30f6744f05
First part of refactoring ARM addrmode2 (load/store) instructions to be more
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explicit about the operands. Split out the different variants into separate
instructions. This gives us the ability to, among other things, assign
different scheduling itineraries to the variants. rdar://8477752.
llvm-svn: 117409
2010-10-26 22:37:02 +00:00
Owen Anderson
55c0bad37d
Correct NEON encodings for vshrn, vrshl, vrshr, vrshrn.
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llvm-svn: 117402
2010-10-26 21:58:41 +00:00
Owen Anderson
570a4cdc45
Simplify classes for shift instructions, which are never commutable.
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llvm-svn: 117398
2010-10-26 21:13:59 +00:00
Owen Anderson
0cecbd810e
Provide correct NEON encodings for vshl, register and immediate forms.
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llvm-svn: 117394
2010-10-26 20:56:57 +00:00
Jim Grosbach
04cd5e5841
Grammar.
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llvm-svn: 117388
2010-10-26 19:34:41 +00:00
Jim Grosbach
db5b1d93c2
Nuke extraneous comment. It's applicable elsewhere, but not in this func.
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llvm-svn: 117387
2010-10-26 19:22:23 +00:00
Owen Anderson
d8e5d26a56
Add correct NEON encoding for vpadal.
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llvm-svn: 117380
2010-10-26 18:18:03 +00:00
Rafael Espindola
adaf2ea5c6
handle X86::EH_RETURN64 and X86::EH_RETURN.
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llvm-svn: 117378
2010-10-26 18:09:55 +00:00
Owen Anderson
b7618a821f
Add NEON encodings for vmov and vmvn of immediates.
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llvm-svn: 117374
2010-10-26 17:40:54 +00:00
Rafael Espindola
e38790534e
Implement some relaxations for arithmetic instructions. The limitation
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on RIP relative relocations looks artificial, but this is a superset of
what we were able to do before.
llvm-svn: 117364
2010-10-26 14:09:12 +00:00
Kalle Raiskila
64680cd5b8
Change v64 datalayout in SPU.
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The SPU ABI does not mention v64, and all examples
in C suggest v128 are treated similarily to arrays,
we use array alignment for v64 too. This makes the
alignment of e.g. [2 x <2 x i32>] behave "intuitively"
and similar to as if the elements were e.g. i32s.
This also makes an "unaligned store" test to be
aligned, with different (but functionally equivalent)
code generated.
llvm-svn: 117360
2010-10-26 10:45:47 +00:00
Evan Cheng
324e678bb7
Use instruction itinerary to determine what instructions are 'cheap'.
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llvm-svn: 117348
2010-10-26 02:08:50 +00:00
Evan Cheng
59acb7e4cf
NEON vmov's are in Neon domain.
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llvm-svn: 117347
2010-10-26 02:03:05 +00:00
Bob Wilson
abe62128b5
Tidy up redundant check.
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llvm-svn: 117331
2010-10-26 00:02:19 +00:00
Rafael Espindola
5fecad6a27
Produce the headers directly in the Finish method. This allows us to use
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the existing streamer methods that are endian safe.
llvm-svn: 117323
2010-10-25 22:26:55 +00:00
Dale Johannesen
2566d39d07
An stdcall function calling a non-stdcall function
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cannot use tailcall. PR 8461.
llvm-svn: 117322
2010-10-25 22:17:05 +00:00
Owen Anderson
e5e0dcd665
Add correct encodings for NEON vabal.
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llvm-svn: 117315
2010-10-25 21:29:04 +00:00