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7088 Commits

Author SHA1 Message Date
Rafael Espindola
55f7a5057d Add support for the 'H' modifier. 
llvm-svn: 122667
 2011-01-01 20:58:46 +00:00
Oscar Fuentes
a63d0dbfbf Add to the list of cmake files the object file, not the asm file. This 
is necessary for executing the custom command that runs the
assember. Fixes PR8877.

llvm-svn: 122649
 2010-12-31 20:15:37 +00:00
Nick Lewycky
5cb84ee2cf Add another non-commutable instruction that gas accepts commuted forms for. 
Fixes PR8861.

llvm-svn: 122641
 2010-12-30 22:10:49 +00:00
NAKAMURA Takumi
2160b3953b CMake: Add disabling optimization on MSVC8 and MSVC10 as workaround for some files in Target/ARM and Target/X86. 
llvm-svn: 122623
 2010-12-29 03:59:27 +00:00
Rafael Espindola
e7e67fce10 Add support for the same encodings of the personality function that gnu as 
supports.

llvm-svn: 122577
 2010-12-27 00:36:05 +00:00
Chris Lattner
a6f2b8316f fix some sort of weird pasto 
llvm-svn: 122560
 2010-12-26 12:05:11 +00:00
Chris Lattner
eec079a470 add a note 
llvm-svn: 122559
 2010-12-26 03:53:31 +00:00
Evan Cheng
ea28d16e36 Code clean up. No functionality change. 
llvm-svn: 122528
 2010-12-23 23:54:17 +00:00
Chris Lattner
01e8c46349 Flag -> Glue, the ongoing saga 
llvm-svn: 122513
 2010-12-23 18:28:41 +00:00
Benjamin Kramer
b21118c91b Remove some obsolete README items, add a new one off the top of my head. 
llvm-svn: 122495
 2010-12-23 15:07:02 +00:00
Benjamin Kramer
d8387aa9bd X86: Lower a select directly to a setcc_carry if possible. 
int test(unsigned long a, unsigned long b) { return -(a < b); }
compiles to
  _test:                              ## @test
    cmpq  %rsi, %rdi                  ## encoding: [0x48,0x39,0xf7]
    sbbl  %eax, %eax                  ## encoding: [0x19,0xc0]
    ret                               ## encoding: [0xc3]
instead of
  _test:                              ## @test
    xorl  %ecx, %ecx                  ## encoding: [0x31,0xc9]
    cmpq  %rsi, %rdi                  ## encoding: [0x48,0x39,0xf7]
    movl  $-1, %eax                   ## encoding: [0xb8,0xff,0xff,0xff,0xff]
    cmovael %ecx, %eax                ## encoding: [0x0f,0x43,0xc1]
    ret                               ## encoding: [0xc3]

llvm-svn: 122451
 2010-12-22 23:09:28 +00:00
Benjamin Kramer
369872edfc Add some x86 specific dagcombines for conditional increments. 
(add Y, (sete  X, 0)) -> cmp X, 1; adc  0, Y
(add Y, (setne X, 0)) -> cmp X, 1; sbb -1, Y
(sub (sete  X, 0), Y) -> cmp X, 1; sbb  0, Y
(sub (setne X, 0), Y) -> cmp X, 1; adc -1, Y

for
  unsigned foo(unsigned a, unsigned b) {
    if (a == 0) b++;
    return b;
  }
we now get:
  foo:
    cmpl  $1, %edi
    movl  %esi, %eax
    adcl  $0, %eax
    ret
instead of:
  foo:
    testl %edi, %edi
    sete  %al
    movzbl  %al, %eax
    addl  %esi, %eax
    ret

llvm-svn: 122364
 2010-12-21 21:41:44 +00:00
Chris Lattner
65c5243bd6 rename MVT::Flag to MVT::Glue. "Flag" is a terrible name for 
something that just glues two nodes together, even if it is
sometimes used for flags.

llvm-svn: 122310
 2010-12-21 02:38:05 +00:00
Nate Begeman
c7dfecb10e Implement feedback from Bruno on making pblendvb an x86-specific ISD node in addition to being an intrinsic, and convert 
lowering to use it.  Hopefully the pattern fragment is doing the right thing with XMM0, looks correct in testing.

llvm-svn: 122277
 2010-12-20 22:04:24 +00:00
Daniel Dunbar
5580eff1f8 Add header... 
llvm-svn: 122247
 2010-12-20 15:45:51 +00:00
Daniel Dunbar
f1deaf06a9 X86/MC/Mach-O: Split out createX86MachObjectWriter(). 
llvm-svn: 122246
 2010-12-20 15:07:39 +00:00
Chris Lattner
bee7320c3c now that addc/adde are gone, "ADDC" in the X86 backend uses EFLAGS results, 
the same as setcc.  Optimize ADDC(0,0,FLAGS) -> SET_CARRY(FLAGS).  This is
a step towards finishing off PR5443.  In the testcase in that bug we now  get:

	movq	%rdi, %rax
	addq	%rsi, %rax
	sbbq	%rcx, %rcx
	testb	$1, %cl
	setne	%dl
	ret

instead of:

	movq	%rdi, %rax
	addq	%rsi, %rax
	movl	$0, %ecx
	adcq	$0, %rcx
	testq	%rcx, %rcx
	setne	%dl
	ret

llvm-svn: 122219
 2010-12-20 01:37:09 +00:00
Chris Lattner
2d4e17d195 We lower setb to sbb with the hope that the and will go away, when it 
doesn't, match it back to setb.

On a 64-bit version of the testcase before we'd get:

	movq	%rdi, %rax
	addq	%rsi, %rax
	sbbb	%dl, %dl
	andb	$1, %dl
	ret

now we get:

	movq	%rdi, %rax
	addq	%rsi, %rax
	setb	%dl
	ret

llvm-svn: 122217
 2010-12-20 01:16:03 +00:00
Chris Lattner
16ea7f257f use for loop over types. 
llvm-svn: 122214
 2010-12-20 01:03:27 +00:00
Chris Lattner
8b1f76cad6 Change the X86 backend to stop using the evil ADDC/ADDE/SUBC/SUBE nodes (which 
their carry depenedencies with MVT::Flag operands) and use clean and beautiful
EFLAGS dependences instead.

We do this by changing the modelling of SBB/ADC to have EFLAGS input and outputs
(which is what requires the previous scheduler change) and change X86 ISelLowering
to custom lower ADDC and friends down to X86ISD::ADD/ADC/SUB/SBB nodes.

With the previous series of changes, this causes no changes in the testsuite, woo.

llvm-svn: 122213
 2010-12-20 00:59:46 +00:00
Mon P Wang
d3adab7a64 Prevents PerformShuffleCombine from creating a node with an illegal type after legalize types 
has run, e.g., prevent creating an i64 node from a v2i64 when i64 is not a legal type.

llvm-svn: 122206
 2010-12-19 23:55:53 +00:00
Chris Lattner
297259f6f1 improve the setcc -> setcc_carry optimization to happen more 
consistently by moving it out of lowering into dag combine.

Add some missing patterns for matching away extended versions of setcc_c.

llvm-svn: 122201
 2010-12-19 22:08:31 +00:00
Chris Lattner
1f31c7fa15 simplify some code to just reuse a setcc if we can instead of 
going through the CSE maps to get it.

llvm-svn: 122196
 2010-12-19 21:23:48 +00:00
Chris Lattner
2d59eef5fd now that generic vector types aren't selected onto MMX operations, 
we don't need -disable-mmx anymore.

llvm-svn: 122189
 2010-12-19 20:19:20 +00:00
Chris Lattner
30438e63c8 reduce copy/paste programming with the power of for loops. 
llvm-svn: 122187
 2010-12-19 20:07:10 +00:00
Chris Lattner
29475c23d0 X86 supports i8/i16 overflow ops (except i8 multiplies), we should 
generate them.  

Now we compile:

define zeroext i8 @X(i8 signext %a, i8 signext %b) nounwind ssp {
entry:
  %0 = tail call %0 @llvm.sadd.with.overflow.i8(i8 %a, i8 %b)
  %cmp = extractvalue %0 %0, 1
  br i1 %cmp, label %if.then, label %if.end

into:

_X:                                     ## @X
## BB#0:                                ## %entry
	subl	$12, %esp
	movb	16(%esp), %al
	addb	20(%esp), %al
	jo	LBB0_2

Before we were generating:

_X:                                     ## @X
## BB#0:                                ## %entry
	pushl	%ebp
	movl	%esp, %ebp
	subl	$8, %esp
	movb	12(%ebp), %al
	testb	%al, %al
	setge	%cl
	movb	8(%ebp), %dl
	testb	%dl, %dl
	setge	%ah
	cmpb	%cl, %ah
	sete	%cl
	addb	%al, %dl
	testb	%dl, %dl
	setge	%al
	cmpb	%al, %ah
	setne	%al
	andb	%cl, %al
	testb	%al, %al
	jne	LBB0_2

llvm-svn: 122186
 2010-12-19 20:03:11 +00:00
Rafael Espindola
7f9be9e112 Remove the MCObjectFormat class. 
llvm-svn: 122147
 2010-12-18 05:37:28 +00:00
Rafael Espindola
9a4bfd7755 Move some data to the TargetWriter. 
llvm-svn: 122134
 2010-12-18 03:27:34 +00:00
Rafael Espindola
ba05bec626 Relax push instructions. 
llvm-svn: 122121
 2010-12-18 01:01:34 +00:00
Nate Begeman
ef5f3c0fa7 Add support for matching psign & plendvb to the x86 target 
Remove unnecessary pandn patterns, 'vnot' patfrag looks through bitcasts

llvm-svn: 122098
 2010-12-17 22:55:37 +00:00
Rafael Espindola
b9ca29bc1c Stub out explicit MCELFObjectTargetWriter interface. 
llvm-svn: 122067
 2010-12-17 17:45:22 +00:00
Rafael Espindola
38e6fdfd1d Move createELFObjectWriter to its own header. 
llvm-svn: 122064
 2010-12-17 16:59:53 +00:00
Daniel Dunbar
6979fc1057 MC/Mach-O: On second thought, use a custom hook for enabling aggressive 
IsSymbolRefDifferenceFullyResolved, it turns out this does change behavior on
enough cases for x86-32 that I would rather wait a bit on it.
 - In practice, we will want to change this eventually because it only means we
   generate less relocations (it also eliminates the need for the horrible
   '.set' hack that Darwin requires in some places).

llvm-svn: 122042
 2010-12-17 05:50:29 +00:00
Daniel Dunbar
6d4a3e98f3 MC/Target: Remove HasScatteredSymbols target hook variable, which has been 
superceded and was effectively dead.

llvm-svn: 122024
 2010-12-17 02:06:08 +00:00
Rafael Espindola
3ee4530406 Make pushq produce signed relocations. 
llvm-svn: 122005
 2010-12-16 22:50:01 +00:00
Daniel Dunbar
2277f06687 MC/Mach-O: Lift some MachObjectWriter arguments into the target specific 
interface.

llvm-svn: 121981
 2010-12-16 17:21:02 +00:00
Daniel Dunbar
5fee4f6862 MC/Mach-O: Stub out explicit MCMachObjectTargetWriter interface. 
llvm-svn: 121973
 2010-12-16 16:09:19 +00:00
Daniel Dunbar
636e690f58 MC/Mach-O: Move createMachObjectWriter into MCMachObjectWriter.h. 
llvm-svn: 121971
 2010-12-16 16:08:33 +00:00
Daniel Dunbar
fc14f1e5f6 MC: Move target specific fixup info descriptors to TargetAsmBackend instead of 
the MCCodeEmitter, which seems like a better organization.
 - Also, cleaned up some magic constants while in the area.

llvm-svn: 121953
 2010-12-16 03:20:06 +00:00
Evan Cheng
72dca1ee17 Only rr forms of ADD*_DB are commutable. 
llvm-svn: 121908
 2010-12-15 22:57:36 +00:00
Evan Cheng
190ff7fa88 Disable auto-detection of AVX support since AVX codegen support is not ready. 
llvm-svn: 121677
 2010-12-13 04:23:53 +00:00
Benjamin Kramer
5a1721f4ac Factor the (x & 2^n) ? 2^m : 0 instcombine into its own method and generalize it 
to catch cases where n != m with a shift.

llvm-svn: 121608
 2010-12-11 09:42:59 +00:00
Rafael Espindola
0e665e502d Fixed version of 121434 with no new memory leaks. 
llvm-svn: 121471
 2010-12-10 07:39:47 +00:00
Rafael Espindola
011e168728 Revert my previous patch to make the valgrind bots happy. 
llvm-svn: 121461
 2010-12-10 04:01:09 +00:00
Nate Begeman
8c00ecd290 Add some missing predicates. 
llvm-svn: 121445
 2010-12-10 00:54:26 +00:00
Nate Begeman
cb6d1c8193 Formalize the notion that AVX and SSE are non-overlapping extensions from the compiler's point of view. Per email discussion, we either want to always use VEX-prefixed instructions or never use them, and are taking "HasAVX" to mean "Always use VEX". Passing -mattr=-avx,+sse42 should serve to restore legacy SSE support when desirable. 
llvm-svn: 121439
 2010-12-10 00:26:57 +00:00
Rafael Espindola
03ad1e8f1f Initial support for the cfi directives. This is just enough to get 
f:
        .cfi_startproc
        nop
        .cfi_endproc

assembled (on ELF).

llvm-svn: 121434
 2010-12-09 23:48:29 +00:00
Nate Begeman
4a62a3e229 Add support for AVX to materialize +0.0 when doing scalar FP. 
llvm-svn: 121415
 2010-12-09 21:43:51 +00:00
Eric Christopher
0e40452eb0 Rewrite the darwin tlv support to use a chain and return to copying 
the output to the correct register. Fixes a hidden problem uncovered
by the last patch where we'd try to DAG combine our MVT::Other node
oddly.

llvm-svn: 121358
 2010-12-09 06:25:53 +00:00
Eric Christopher
64e662fce9 Stop confusing people, it's not really a chain, or a tumor. 
llvm-svn: 121340
 2010-12-09 00:57:19 +00:00
Eric Christopher
0100a8fda4 Remove extraneous copy from DAG conversion for darwin tls. This was 
popping up at O0 when it wasn't folded and the fast allocator would
complain.

llvm-svn: 121330
 2010-12-09 00:27:58 +00:00
Eric Christopher
cc8a622ca4 Add rsp to the uses for the same reason as 32-bit. 
llvm-svn: 121328
 2010-12-09 00:26:41 +00:00
Kevin Enderby
988dab6b5c Allow a slash, '/', as a prefix separator for X86. rdar://8741045 
llvm-svn: 121320
 2010-12-08 23:57:59 +00:00
NAKAMURA Takumi
7947c9770a lib/Target/X86/X86MCAsmInfo.cpp: [PR8741] On Win64, specify explicit PrivateGlobalPrefix as ".L". 
Or, global symbols @Lxxxx might be treated as temporal symbol by MCSymbol.

llvm-svn: 121103
 2010-12-07 02:43:45 +00:00
Rafael Espindola
65c25aef87 Remove the instruction fragment to data fragment lowering since it was causing 
freed data to be read. I will open a bug to track it being reenabled.

llvm-svn: 121028
 2010-12-06 19:08:48 +00:00
Rafael Espindola
3e954d16f4 Second try at making direct object emission produce the same results 
as llc + llvm-mc. This time ELF is not changed and I tested that llvm-gcc
bootstrap on darwin10 using darwin9's assembler and linker.

llvm-svn: 121006
 2010-12-06 17:27:56 +00:00
Chris Lattner
e30adfb732 Teach X86ISelLowering that the second result of X86ISD::UMUL is a flags 
result.  This allows us to compile:

void *test12(long count) {
      return new int[count];
}

into:

test12:
	movl	$4, %ecx
	movq	%rdi, %rax
	mulq	%rcx
	movq	$-1, %rdi
	cmovnoq	%rax, %rdi
	jmp	__Znam                  ## TAILCALL

instead of:

test12:
	movl	$4, %ecx
	movq	%rdi, %rax
	mulq	%rcx
	seto	%cl
	testb	%cl, %cl
	movq	$-1, %rdi
	cmoveq	%rax, %rdi
	jmp	__Znam

Of course it would be even better if the regalloc inverted the cmov to 'cmovoq',
which would eliminate the need for the 'movq %rdi, %rax'.

llvm-svn: 120936
 2010-12-05 07:49:54 +00:00
Chris Lattner
76601e7a99 it turns out that when ".with.overflow" intrinsics were added to the X86 
backend that they were all implemented except umul.  This one fell back
to the default implementation that did a hi/lo multiply and compared the
top.  Fix this to check the overflow flag that the 'mul' instruction
sets, so we can avoid an explicit test.  Now we compile:

void *func(long count) {
      return new int[count];
}

into:

__Z4funcl:                              ## @_Z4funcl
	movl	$4, %ecx                ## encoding: [0xb9,0x04,0x00,0x00,0x00]
	movq	%rdi, %rax              ## encoding: [0x48,0x89,0xf8]
	mulq	%rcx                    ## encoding: [0x48,0xf7,0xe1]
	seto	%cl                     ## encoding: [0x0f,0x90,0xc1]
	testb	%cl, %cl                ## encoding: [0x84,0xc9]
	movq	$-1, %rdi               ## encoding: [0x48,0xc7,0xc7,0xff,0xff,0xff,0xff]
	cmoveq	%rax, %rdi              ## encoding: [0x48,0x0f,0x44,0xf8]
	jmp	__Znam                  ## TAILCALL

instead of:

__Z4funcl:                              ## @_Z4funcl
	movl	$4, %ecx                ## encoding: [0xb9,0x04,0x00,0x00,0x00]
	movq	%rdi, %rax              ## encoding: [0x48,0x89,0xf8]
	mulq	%rcx                    ## encoding: [0x48,0xf7,0xe1]
	testq	%rdx, %rdx              ## encoding: [0x48,0x85,0xd2]
	movq	$-1, %rdi               ## encoding: [0x48,0xc7,0xc7,0xff,0xff,0xff,0xff]
	cmoveq	%rax, %rdi              ## encoding: [0x48,0x0f,0x44,0xf8]
	jmp	__Znam                  ## TAILCALL

Other than the silly seto+test, this is using the o bit directly, so it's going in the right
direction.

llvm-svn: 120935
 2010-12-05 07:30:36 +00:00
Chris Lattner
16bafb2414 generalize the previous check to handle -1 on either side of the 
select, inserting a not to compensate.  Add a missing isZero check
that I lost somehow.

This improves codegen of:

void *func(long count) {
      return new int[count];
}

from:

__Z4funcl:                              ## @_Z4funcl
	movl	$4, %ecx                ## encoding: [0xb9,0x04,0x00,0x00,0x00]
	movq	%rdi, %rax              ## encoding: [0x48,0x89,0xf8]
	mulq	%rcx                    ## encoding: [0x48,0xf7,0xe1]
	testq	%rdx, %rdx              ## encoding: [0x48,0x85,0xd2]
	movq	$-1, %rdi               ## encoding: [0x48,0xc7,0xc7,0xff,0xff,0xff,0xff]
	cmoveq	%rax, %rdi              ## encoding: [0x48,0x0f,0x44,0xf8]
	jmp	__Znam                  ## TAILCALL
                                        ## encoding: [0xeb,A]

to:

__Z4funcl:                              ## @_Z4funcl
	movl	$4, %ecx                ## encoding: [0xb9,0x04,0x00,0x00,0x00]
	movq	%rdi, %rax              ## encoding: [0x48,0x89,0xf8]
	mulq	%rcx                    ## encoding: [0x48,0xf7,0xe1]
	cmpq	$1, %rdx                ## encoding: [0x48,0x83,0xfa,0x01]
	sbbq	%rdi, %rdi              ## encoding: [0x48,0x19,0xff]
	notq	%rdi                    ## encoding: [0x48,0xf7,0xd7]
	orq	%rax, %rdi              ## encoding: [0x48,0x09,0xc7]
	jmp	__Znam                  ## TAILCALL
                                        ## encoding: [0xeb,A]

llvm-svn: 120932
 2010-12-05 02:00:51 +00:00
Chris Lattner
474ed0aa9b Improve an integer select optimization in two ways: 
1. generalize 
    (select (x == 0), -1, 0) -> (sign_bit (x - 1))
to:
    (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y

2. Handle the identical pattern that happens with !=:
   (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y

cmov is often high latency and can't fold immediates or
memory operands.  For example for (x == 0) ? -1 : 1, before 
we got:

< 	testb	%sil, %sil
< 	movl	$-1, %ecx
< 	movl	$1, %eax
< 	cmovel	%ecx, %eax

now we get:

> 	cmpb	$1, %sil
> 	sbbl	%eax, %eax
> 	orl	$1, %eax

llvm-svn: 120929
 2010-12-05 01:23:24 +00:00
Bill Wendling
2b53c0830d Initialize HasPOPCNT. 
llvm-svn: 120923
 2010-12-04 23:57:24 +00:00
Benjamin Kramer
851691ddb2 Add patterns for the x86 popcnt instruction. 
- Also adds a new POPCNT subtarget feature that is currently enabled if the target
  supports SSE4.2 (nehalem) or SSE4A (barcelona).

llvm-svn: 120917
 2010-12-04 20:32:23 +00:00
Benjamin Kramer
77faee6ba1 Simplify code. No functionality change. 
llvm-svn: 120907
 2010-12-04 14:22:24 +00:00
Rafael Espindola
9215947c83 There are two reasons why we might want to use 
foo = a - b
.long foo
instead of just
.long a - b

First, on darwin9 64 bits the assembler produces the wrong result. Second,
if "a" is the end of the section all darwin assemblers (9, 10 and mc) will not
consider a - b to be a constant but will if the dummy foo is created.

Split how we handle these cases. The first one is something MC should take care
of. The second one has to be handled by the caller.

llvm-svn: 120889
 2010-12-04 03:21:47 +00:00
Nate Begeman
d4310b6d7c Revert this change since it breaks a couple of the AVX tests. 
I'm unclear if the tests are actually correct or not, but reverting for now.

llvm-svn: 120847
 2010-12-03 22:29:15 +00:00
Nate Begeman
deb26223bd Scalar f32/f64 are also subregs of ymm regs 
llvm-svn: 120844
 2010-12-03 21:54:39 +00:00
Nate Begeman
3911dcfd71 Remove SSE1-4 disable when AVX is enabled. While this may be useful for development, 
it completely breaks scalar fp in xmm regs when AVX is enabled.

llvm-svn: 120843
 2010-12-03 21:54:14 +00:00
Devang Patel
409a5ff824 Revert r120580. 
llvm-svn: 120630
 2010-12-02 00:22:29 +00:00
Evan Cheng
4118b24aca Fix and re-enable tail call optimization of expanded libcalls. 
llvm-svn: 120622
 2010-12-01 22:59:46 +00:00
Devang Patel
e68cb5a5cf Disable debug info for x86-darwin9 and earlier until PR 8715 and radar 8709290 are fixed. 
llvm-svn: 120580
 2010-12-01 16:59:34 +00:00
Duncan Sands
cd4f56b8e2 I don't think it makes any sense to assert that the target supports SSE3 here. 
The user (i.e. whoever generated a call to the intrinsic in the first place) is
essentially asking for a particular instruction to be placed in the assembler.
If that instruction won't execute on the target machine, that's their problem
not ours.  Two buildbots with processors that don't support SSE3 were barfing
on the apm.ll test in CodeGen/X86 because of this assertion.

llvm-svn: 120574
 2010-12-01 12:58:13 +00:00
Evan Cheng
84162760b7 Speculatively disable x86 portion of r120501 to appease the x86_64 buildbot. 
llvm-svn: 120549
 2010-12-01 03:27:20 +00:00
Evan Cheng
f7e586d749 Enable sibling call optimization of libcalls which are expanded during 
legalization time. Since at legalization time there is no mapping from
SDNode back to the corresponding LLVM instruction and the return
SDNode is target specific, this requires a target hook to check for
eligibility. Only x86 and ARM support this form of sibcall optimization
right now.
rdar://8707777

llvm-svn: 120501
 2010-11-30 23:55:39 +00:00
Eric Christopher
3a1c712e47 Move X86InstrFPStack.td over to PseudoI as well. 
llvm-svn: 120470
 2010-11-30 21:57:32 +00:00
Eric Christopher
b15c993a73 Migrate X86InstrControl.td to use PseudoI and fix a couple of 80-col violations 
while I'm in there.

llvm-svn: 120466
 2010-11-30 21:37:36 +00:00
Eric Christopher
1a99e7ebdb Fix some grammar in comments I noticed. 
llvm-svn: 120416
 2010-11-30 09:11:54 +00:00
Eric Christopher
d8e045d29e This defaults to GenericDomain. 
llvm-svn: 120415
 2010-11-30 09:11:07 +00:00
Eric Christopher
6a21ceab5c Implement a PseudoI class and transfer the sse instructions over to use 
it.

llvm-svn: 120412
 2010-11-30 08:57:23 +00:00
Eric Christopher
73365ae8b6 Fix insertion point in pcmp expander. 
While I'm there, clean up too many \n even for me.

llvm-svn: 120411
 2010-11-30 08:20:21 +00:00
Eric Christopher
2170738538 Fix some cleanups from my last patch. 
llvm-svn: 120410
 2010-11-30 08:10:28 +00:00
Eric Christopher
f27f0b5234 Rewrite mwait and monitor support and custom lower arguments. 
Fixes PR8573.

llvm-svn: 120404
 2010-11-30 07:20:12 +00:00
Michael J. Spencer
d5ec932c3a Merge System into Support. 
llvm-svn: 120298
 2010-11-29 18:16:10 +00:00
Rafael Espindola
9287c4b38f Move lowering of TLS_addr32 and TLS_addr64 to X86MCInstLower. 
llvm-svn: 120263
 2010-11-28 21:16:39 +00:00
Chris Lattner
a11c5c5c32 fix PR8686, accepting a 'b' suffix at the end of all the setcc 
instructions.  I choose to handle this with an asmparser hack,
though it could be handled by changing all the instruction definitions
to allow be "setneb" instead of "setne".  The asm parser hack is
better in this case, because we want the disassembler to produce
setne, not setneb.

llvm-svn: 120260
 2010-11-28 20:23:50 +00:00
Rafael Espindola
f77005db2b Define generic 1, 2 and 4 byte pc relative relocations. They are common 
and at least the 4 byte one will be needed to implement the .cfi_* directives.

llvm-svn: 120240
 2010-11-28 14:17:56 +00:00
Anton Korobeynikov
598465c605 Move more PEI-related hooks to TFI 
llvm-svn: 120229
 2010-11-27 23:05:25 +00:00
Anton Korobeynikov
c87f68e32e Move callee-saved regs spills / reloads to TFI 
llvm-svn: 120228
 2010-11-27 23:05:03 +00:00
Rafael Espindola
45cd9713f2 Lower TLS_addr32 and TLS_addr64. 
llvm-svn: 120225
 2010-11-27 20:43:02 +00:00
Rafael Espindola
6f5680f4a0 Implement the data16 prefix. 
llvm-svn: 120224
 2010-11-27 20:29:45 +00:00
Daniel Dunbar
bcc15fb05d MC/Mach-O: Switch to using MachOFormat.h. 
- I'm leaving MachO.h, because I believe it has external consumers, but I would really like to eliminate it (we have stylistic disagreements with one another).

llvm-svn: 120187
 2010-11-27 04:38:36 +00:00
Rafael Espindola
0641196380 Remove the unused TheTarget member. 
llvm-svn: 120168
 2010-11-26 04:24:21 +00:00
Rafael Espindola
e3dc1c951c Use multiple 0x66 prefixes so that all nops up to 15 bytes are a single instruction. 
llvm-svn: 120147
 2010-11-25 17:14:16 +00:00
Rafael Espindola
72c8de703d Implement the rex64 prefix. 
llvm-svn: 120017
 2010-11-23 11:23:24 +00:00
Rafael Espindola
6f069fc35f Produce a relocation for pcrel absolute values. Based on a patch by David Meyer. 
llvm-svn: 120006
 2010-11-23 07:20:12 +00:00
Wesley Peck
d589353ad0 Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. 
llvm-svn: 119990
 2010-11-23 03:31:01 +00:00
Rafael Espindola
492580fa9a Remove duplicated constants. Thanks to Jason for noticing it. 
llvm-svn: 119985
 2010-11-22 21:49:05 +00:00
Chris Lattner
dd03f96698 apparently tailcalls are better on darwin/x86-64 than on linux? 
llvm-svn: 119947
 2010-11-21 18:59:20 +00:00
Chris Lattner
4aaa7fbb98 implement PR8524, apparently mainline gas accepts movq as an alias for movd 
when transfering between i64 gprs and mmx regs.

llvm-svn: 119931
 2010-11-21 08:18:57 +00:00
Anton Korobeynikov
ff8c52bd51 Move some more hooks to TargetFrameInfo 
llvm-svn: 119904
 2010-11-20 15:59:32 +00:00
Duncan Sands
028cf0619e On X86, MEMBARRIER, MFENCE, SFENCE, LFENCE are not target memory intrinsics, 
so don't claim they are.  They are allocated using DAG.getNode, so attempts
to access MemSDNode fields results in reading off the end of the allocated
memory.  This fixes crashes with "llc -debug" due to debug code trying to
print MemSDNode fields for these barrier nodes (since the crashes are not
deterministic, use valgrind to see this).  Add some nasty checking to try
to catch this kind of thing in the future.

llvm-svn: 119901
 2010-11-20 11:25:00 +00:00
Anton Korobeynikov
ce676f96e1 Move getInitialFrameState() to TargetFrameInfo 
llvm-svn: 119754
 2010-11-18 23:25:52 +00:00
Anton Korobeynikov
269e7d3be1 Move hasFP() and few related hooks to TargetFrameInfo. 
llvm-svn: 119740
 2010-11-18 21:19:35 +00:00
Chris Lattner
c85f76f7da trivial QoI improvement. On this invalid input: 
sahf	movl	344(%rdi),%r14d
we used to produce:

t.s:2:1: error: unexpected token in argument list

^

we now produce:
t.s:1:11: error: unexpected token in argument list
sahf	movl	344(%rdi),%r14d
    	    	^

rdar://8581401

llvm-svn: 119676
 2010-11-18 02:53:02 +00:00
Rafael Espindola
7fc5cd0a58 make isVirtualSection a virtual method on MCSection. Chris' suggestion. 
llvm-svn: 119547
 2010-11-17 20:03:54 +00:00
Dan Gohman
348c3f8197 Reapply r118917. With pseudo-instruction expansion moved to 
a different pass, the complicated interaction between cmov expansion
and fast isel is no longer a concern.

llvm-svn: 119400
 2010-11-16 22:43:23 +00:00
Oscar Fuentes
690d065e70 Fix assembling X86CompilationCallback_Win64.asm on VS 10. 
Patch by Louis Zhuang!

llvm-svn: 119394
 2010-11-16 22:07:47 +00:00
Rafael Espindola
53a8ae85b7 Change the 11 byte nop to be a single instruction. 
llvm-svn: 119286
 2010-11-15 23:10:30 +00:00
Chris Lattner
b2daeac125 add fields to the .td files unconditionally, simplifying tblgen a bit. 
Switch the ARM backend to use 'let' instead of 'set' with this change.

llvm-svn: 119120
 2010-11-15 05:19:05 +00:00
Chris Lattner
9a0a840839 add targetoperand flags for jump tables, constant pool and block address 
nodes to indicate when ha16/lo16 modifiers should be used.  This lets
us pass PowerPC/indirectbr.ll.

The one annoying thing about this patch is that the MCSymbolExpr isn't
expressive enough to represent ha16(label1-label2) which we need on
PowerPC.  I have a terrible hack in the meantime, but this will have
to be revisited at some point.

Last major conversion item left is global variable references.

llvm-svn: 119105
 2010-11-15 02:46:57 +00:00
Anton Korobeynikov
794259aec0 Attempt to unbreak cmake-based builds 
llvm-svn: 119098
 2010-11-15 00:48:12 +00:00
Anton Korobeynikov
76c52dcf44 First step of huge frame-related refactoring: move emit{Prologue,Epilogue} out of TargetRegisterInfo to TargetFrameInfo, which is definitely much better suitable place 
llvm-svn: 119097
 2010-11-15 00:06:54 +00:00
Chris Lattner
b347be831c tidy up, no functionality change. 
llvm-svn: 119092
 2010-11-14 23:32:42 +00:00
Chris Lattner
51168d6510 move the pic base symbol stuff up to MachineFunction 
since it is trivial and will be shared between ppc and x86.
This substantially simplifies the X86 backend also.

llvm-svn: 119089
 2010-11-14 22:48:15 +00:00
Chris Lattner
09ea2ce78f simplify getPICBaseSymbol a bit. 
llvm-svn: 119088
 2010-11-14 22:37:11 +00:00
Chris Lattner
3e3e29381e random acts of tidiness. 
llvm-svn: 119049
 2010-11-14 18:09:50 +00:00
Peter Collingbourne
4ec6b2dbe7 Recognise 32-bit ror-based bswap implementation used by uclibc 
llvm-svn: 119007
 2010-11-13 19:54:30 +00:00
Peter Collingbourne
6c3094234e Support ; as asm separator 
llvm-svn: 119006
 2010-11-13 19:54:23 +00:00
Daniel Dunbar
2ba9f79194 MC: Simplify Mach-O and ELF object writer implementations. 
- What was I thinking?????

llvm-svn: 118992
 2010-11-13 07:33:40 +00:00
Dan Gohman
a4aa69cf2a Revert r118917, which is implicated in the llvm-gcc-i386-linux-selfhost failure. 
llvm-svn: 118954
 2010-11-13 00:31:40 +00:00
Dan Gohman
8b86287a06 When the definition of an address value is in a different block 
from the user of the address, fall back to just using the
address in a register instead of bailing out of fast-isel
altogether.

llvm-svn: 118917
 2010-11-12 19:14:00 +00:00
Chris Lattner
2a70c4e38a accept lret as an alias for lretl, fixing the reopened part of PR8592 
llvm-svn: 118916
 2010-11-12 18:54:56 +00:00
Chris Lattner
612039e538 implement PR8592: empirically "lretq" is a "lret" with a rex.w prefix. 
llvm-svn: 118903
 2010-11-12 17:41:20 +00:00
Chris Lattner
bcdb696f6c tidy up. 
llvm-svn: 118896
 2010-11-12 17:24:29 +00:00
Dale Johannesen
659061fcd3 Remove possibly useful info from comment, per Chris. 
llvm-svn: 118865
 2010-11-12 00:43:18 +00:00
Rafael Espindola
5766346831 Remove some explicit arguments to getELFSection. This is 
a leftover from the removal of isExplicit.

llvm-svn: 118774
 2010-11-11 03:40:25 +00:00
Bruno Cardoso Lopes
9f9f796756 Fix PR8211 
llvm-svn: 118445
 2010-11-08 21:24:59 +00:00
Chris Lattner
24ba201941 implement aliases for div/idiv that have an explicit A register operand, 
implementing rdar://8431864

llvm-svn: 118364
 2010-11-06 22:41:18 +00:00
Chris Lattner
25f31dcc8f add aliases for movs between seg registers and mem. There are multiple 
different forms of this instruction (movw/movl/movq) which we reported
as being ambiguous.  Since they all do the same thing, gas just picks the
one with the shortest encoding.  Follow its lead here.

This implements rdar://8208615

llvm-svn: 118362
 2010-11-06 22:35:34 +00:00
Chris Lattner
5cd42cb6f4 move the "sh[lr]d op,op" -> "shld $1, op,op" aliases to the .td file. 
llvm-svn: 118361
 2010-11-06 22:25:39 +00:00
Chris Lattner
95add4d79a work-in-progress 
llvm-svn: 118358
 2010-11-06 22:05:43 +00:00
Chris Lattner
0d6d870628 go to great lengths to work around a GAS bug my previous patch 
exposed:

GAS doesn't accept "fcomip %st(1)", it requires "fcomip %st(1), %st(0)"
even though st(0) is implicit in all other fp stack instructions.

Fortunately, there is an alias for fcomip named "fcompi" and gas does
accept the default argument for the alias (boggle!).

As such, switch the canonical form of this instruction to "pi" instead
of "ip".  This makes the code generator and disassembler generate pi,
avoiding the gas bug.

llvm-svn: 118356
 2010-11-06 21:37:06 +00:00
Chris Lattner
bbd318b76a rework the rotate-by-1 instructions to be defined like the 
shift-by-1 instructions, where the asmstring doesn't contain
the implicit 1.  It turns out that a bunch of these rotate
instructions were completely broken because they used 1 
instead of $1.

This fixes assembly mismatches on "rclb	$1, %bl" and friends,
where we used to generate the 3 byte form, we now generate the
proper 2-byte form.

llvm-svn: 118355
 2010-11-06 21:23:40 +00:00
Chris Lattner
af1f50772a change the fp comparison instructions to not have %st0 explicitly 
listed in its asm string, for consistency with the other similar
instructions.

llvm-svn: 118354
 2010-11-06 20:55:09 +00:00
Chris Lattner
b64f8e10ab move the plethora of fp stack aliases to the .td file. 
llvm-svn: 118353
 2010-11-06 20:47:38 +00:00
Chris Lattner
4834890f0a add (and document) the ability for alias results to have 
fixed physical registers.  Start moving fp comparison
aliases to the .td file (which default to using %st1 if
nothing is specified).

llvm-svn: 118352
 2010-11-06 19:57:21 +00:00
Chris Lattner
c0e756dc47 generalize alias support to allow the result of an alias to 
add fixed immediate values.  Move the aad and aam aliases to
use this, and document it.

llvm-svn: 118350
 2010-11-06 19:25:43 +00:00
Chris Lattner
a7c7312e55 move fnstsw aliases to .td file, fix typo 
llvm-svn: 118349
 2010-11-06 18:58:32 +00:00
Chris Lattner
b686fb93c7 move in/out aliases to the .td files. 
llvm-svn: 118348
 2010-11-06 18:52:40 +00:00
Chris Lattner
6b905e3a10 move sldt, imul, and movabsq aliases from c++ to .td file. 
llvm-svn: 118347
 2010-11-06 18:44:26 +00:00
Chris Lattner
1beb2b3fc5 correct suffix matching to search for s/l/t suffixes on 
floating point stack instructions instead of looking for b/w/l/q.

This fixes issues where we'd accidentally match fistp to fistpl,
when it is in fact an ambiguous instruction.

This changes the behavior of llvm-mc to reject fstp, which was the
correct fix for rdar://8456389:
t.s:1:1: error: ambiguous instructions require an explicit suffix (could be 'fstps', 'fstpl', or 'fstpt')
fstp	(%rax)

it also causes us to correctly reject fistp and fist, which addresses
PR8528:

t.s:2:1: error: ambiguous instructions require an explicit suffix (could be 'fistps', or 'fistpl')
fistp (%rax)
^
t.s:3:1: error: ambiguous instructions require an explicit suffix (could be 'fists', or 'fistl')
fist (%rax)
^

Thanks to Ismail Donmez for tracking down the issue here!

llvm-svn: 118346
 2010-11-06 18:28:02 +00:00
Chris Lattner
637f4910c3 fix a bug where we had an implicit assumption that the 
result instruction operand numbering matched the result pattern.

Fixing this allows us to move the xchg/test aliases to the .td file.

llvm-svn: 118334
 2010-11-06 08:20:59 +00:00
Chris Lattner
4fd3b4ad94 move the lcall/ljmp aliases to the .td file. 
llvm-svn: 118332
 2010-11-06 07:48:45 +00:00
Chris Lattner
66c868f386 move the "movsd -> movsl" alias to the .td files, 
tidy up the movsx and movzx aliases.

llvm-svn: 118331
 2010-11-06 07:34:58 +00:00
Chris Lattner
ec0ef3385d fix some bugs in the alias support, unblocking changing of "clr" aliases 
from c++ hacks to proper .td InstAlias definitions.  Change them!

llvm-svn: 118330
 2010-11-06 07:31:43 +00:00
Chris Lattner
5d1361e9ed Reimplement BuildResultOperands to be in terms of the result instruction's 
operand list instead of the operand list redundantly declared on the alias
or instruction.

With this change, we finally remove the ins/outs list on the alias.  Before:
  def : InstAlias<(outs GR16:$dst), (ins GR8 :$src),
                  "movsx $src, $dst",
                  (MOVSX16rr8W GR16:$dst, GR8:$src)>;
After:
  def : InstAlias<"movsx $src, $dst",
                  (MOVSX16rr8W GR16:$dst, GR8:$src)>;

This also makes the alias mechanism more general and powerful, which will
be exploited in subsequent patches.

llvm-svn: 118329
 2010-11-06 07:14:44 +00:00
Jim Grosbach
a85416eb77 Allow targets to specify the MachO CPUType/CPUSubtype information. 
llvm-svn: 118288
 2010-11-05 18:48:58 +00:00
Duncan Sands
1af5c00d3c When passing a huge parameter using the byval mechanism, a long 
sequence of loads and stores was being generated to perform the
copy on the x86 targets if the parameter was less than 4 byte
aligned, causing llc to use up vast amounts of memory and time.
Use a "rep movs" form instead.  PR7170.

llvm-svn: 118260
 2010-11-04 21:16:46 +00:00
Duncan Sands
3bf2a701a5 In the calling convention logic, ValVT is always a legal type, 
and as such can be represented by an MVT - the more complicated
EVT is not needed.  Use MVT for ValVT everywhere.

llvm-svn: 118245
 2010-11-04 10:49:57 +00:00
Duncan Sands
41edf30895 Simplify uses of MVT and EVT. An MVT can be compared directly 
with a SimpleValueType, while an EVT supports equality and
inequality comparisons with SimpleValueType.

llvm-svn: 118169
 2010-11-03 12:17:33 +00:00
Duncan Sands
f6e5e02c9b Inside the calling convention logic LocVT is always a simple 
value type, so there is no point in passing it around using
an EVT.  Use the simpler MVT everywhere.  Rather than trying
to propagate this information maximally in all the code that
using the calling convention stuff, I chose to do a mainly
low impact change instead.

llvm-svn: 118167
 2010-11-03 11:35:31 +00:00
Chris Lattner
f94c2b782a rearrange a bit. 
llvm-svn: 117967
 2010-11-01 23:07:52 +00:00
Chris Lattner
b0ac93cf15 use our fancy new MnemonicAlias mechanism to remove a bunch of hacks 
from X86AsmParser.cpp

llvm-svn: 117952
 2010-11-01 21:06:34 +00:00
Chris Lattner
d595d1f4d7 "mov[zs]x (mem), GR16" are not ambiguous: the mem 
must be 8 bits.  Support this memory form.

llvm-svn: 117902
 2010-11-01 05:41:10 +00:00
Chris Lattner
81d051481e Implement enough of the missing instalias support to get 
aliases installed and working.  They now work when the
matched pattern and the result instruction have exactly
the same operand list.

This is now enough for us to define proper aliases for
movzx and movsx, implementing rdar://8017633 and PR7459.

Note that we do not accept instructions like:
  movzx 0(%rsp), %rsi

GAS accepts this instruction, but it doesn't make any
sense because we don't know the size of the memory
operand.  It could be 8/16/32 bits.

llvm-svn: 117901
 2010-11-01 05:34:34 +00:00
Chris Lattner
0a4807eefc make the asm matcher emitter reject instructions that have comments 
in their asmstring.  Fix the two x86 "NOREX" instructions that have them.
If these comments are important, the instlowering stuff can print them.

llvm-svn: 117897
 2010-11-01 04:44:29 +00:00
Chris Lattner
9da275f86b reject instructions that contain a \n in their asmstring. Mark 
various X86 and ARM instructions that are bitten by this as isCodeGenOnly,
as they are.

llvm-svn: 117884
 2010-11-01 00:46:16 +00:00
Chris Lattner
a4c36d0efe fix the !eq operator in tblgen to return a bit instead of an int. 
Use this to make the X86 and ARM targets set isCodeGenOnly=1 
automatically for their instructions that have Format=Pseudo,
resolving a hack in tblgen.

llvm-svn: 117862
 2010-10-31 19:22:57 +00:00
Chris Lattner
5d088218e5 two changes: make the asmmatcher generator ignore ARM pseudos properly, 
and make it a hard error for instructions to not have an asm string.
These instructions should be marked isCodeGenOnly.

llvm-svn: 117861
 2010-10-31 19:15:18 +00:00
Chris Lattner
8aaac91ca4 sketch out the planned instruction alias mechanism, add some comments about 
how the push/pop mnemonic aliases are wrong.

llvm-svn: 117857
 2010-10-31 18:43:46 +00:00
Duncan Sands
92f33ea784 Factorize the duplicated logic for choosing the right argument 
calling convention out of the fast and normal ISel files, and
into the calling convention TD file.

llvm-svn: 117856
 2010-10-31 13:21:44 +00:00
Duncan Sands
0f49c49476 Remove CCAssignFnForRet from X86 FastISel in favour of RetCC_X86, 
which has the same logic specified in the CallingConv TD file.
This brings FastISel in line with the standard X86 ISel.

llvm-svn: 117855
 2010-10-31 13:02:38 +00:00
Chris Lattner
49227ad505 Resolve a terrible hack in tblgen: instead of hardcoding 
"In32BitMode" and "In64BitMode" into tblgen, allow any
predicate that inherits from AssemblerPredicate.

llvm-svn: 117831
 2010-10-30 19:38:20 +00:00
Chris Lattner
15e92ddd01 Implement (and document!) support for MnemonicAlias's to have Requires 
directives, allowing things like this:

def : MnemonicAlias<"pop", "popl">, Requires<[In32BitMode]>;
def : MnemonicAlias<"pop", "popq">, Requires<[In64BitMode]>;

Move the rest of the X86 MnemonicAliases over to the .td file.

llvm-svn: 117830
 2010-10-30 19:23:13 +00:00
Chris Lattner
441672d7cb really zap alias. 
llvm-svn: 117824
 2010-10-30 18:23:25 +00:00
Chris Lattner
ba9271be5b move fcompi alias to .td file and zap some useless code. 
llvm-svn: 117823
 2010-10-30 18:22:53 +00:00
Chris Lattner
1b3b2e113f move rep aliases to td file 
llvm-svn: 117822
 2010-10-30 18:17:33 +00:00
Chris Lattner
49f977366f move sal aliases to .td file. 
llvm-svn: 117821
 2010-10-30 18:14:54 +00:00
Chris Lattner
54892b4d8d fix an encoding mismatch where "sal %eax, 1" was not using the short encoding 
for shl.  Caught by inspection.

llvm-svn: 117820
 2010-10-30 18:13:10 +00:00
Chris Lattner
38179edecd move a bunch more aliases from .cpp -> .td file. 
llvm-svn: 117819
 2010-10-30 18:07:17 +00:00
Chris Lattner
ac7f4957b1 move cmov aliases to .td file. 
llvm-svn: 117818
 2010-10-30 17:56:50 +00:00
Chris Lattner
acec7b7d46 move setcc and jcc aliases from .cpp to .td 
llvm-svn: 117817
 2010-10-30 17:51:45 +00:00
Chris Lattner
e90ff8dcb6 move some code. 
llvm-svn: 117816
 2010-10-30 17:38:55 +00:00
Chris Lattner
7c61e4bca2 implement (and document!) the first kind of MC assembler alias, which 
just remaps one mnemonic to another.  Convert a few of the X86 aliases
from .cpp to .td code.

llvm-svn: 117815
 2010-10-30 17:36:36 +00:00
Jim Grosbach
951667ac39 Clean up comments. 
llvm-svn: 117785
 2010-10-30 13:48:28 +00:00
Chris Lattner
45c679522d stay out of the reserved namespace 
llvm-svn: 117773
 2010-10-30 04:57:14 +00:00
John Thompson
6115a7f1d4 Inline asm multiple alternative constraints development phase 2 - improved basic logic, added initial platform support. 
llvm-svn: 117667
 2010-10-29 17:29:13 +00:00
Dale Johannesen
b78530f9b0 Fix pastos in handling of AVX cvttsd2si, PR8491. 
Bruno, please review, but I'm pretty sure this is right.
Patch by Alex Mac!

llvm-svn: 117514
 2010-10-28 00:35:54 +00:00
Kevin Enderby
a53cc6a764 Added the x86 instruction ud2b (2nd official undefined instruction). 
llvm-svn: 117485
 2010-10-27 20:46:49 +00:00
Michael J. Spencer
5518dda87e x86-Win32: Switch ftol2 calling convention from stdcall to C. 
llvm-svn: 117474
 2010-10-27 18:52:38 +00:00
Kevin Enderby
74a2614673 Yet another tweak to X86 instructions to add ud2a as an alias to ud2 
(still to add ud2b).

llvm-svn: 117435
 2010-10-27 03:01:02 +00:00
Kevin Enderby
d22f3b9de7 Another tweak to X86 instructions to add the missing flex instruction (without 
the wait prefix).

llvm-svn: 117434
 2010-10-27 02:53:04 +00:00
Kevin Enderby
e812b356cc Tweaks to X86 instructions to allow the 'w' suffix in places it makes 
sense, when the instruction takes the 16-bit ax register or m16 memory
location.  These changes to llvm-mc matches what the darwin assembler
allows for these instructions.  Done differently than in r117031 that
caused a valgrind error which was later reverted.

llvm-svn: 117433
 2010-10-27 02:32:19 +00:00
Kevin Enderby
d5235bb45c Added some aliases to the fcomip and fucompi Intel instructions. So that llvm-mc 
will accept versions that the darwin assembler allows.  Forms ending in "pi" and
forms without all the operands.

llvm-svn: 117427
 2010-10-27 00:59:28 +00:00
Dale Johannesen
e7f07349e4 Use a MemIntrinsicSDNode for ISD::PREFETCH, which touches 
memory, so a MachineMemOperand is useful (not propagated
into the MachineInstr yet).  No functional change except
for dump output.

llvm-svn: 117413
 2010-10-26 23:11:10 +00:00
Rafael Espindola
adaf2ea5c6 handle X86::EH_RETURN64 and X86::EH_RETURN. 
llvm-svn: 117378
 2010-10-26 18:09:55 +00:00
Rafael Espindola
e38790534e Implement some relaxations for arithmetic instructions. The limitation 
on RIP relative relocations looks artificial, but this is a superset of
what we were able to do before.

llvm-svn: 117364
 2010-10-26 14:09:12 +00:00
Dale Johannesen
2566d39d07 An stdcall function calling a non-stdcall function 
cannot use tailcall.  PR 8461.

llvm-svn: 117322
 2010-10-25 22:17:05 +00:00
Rafael Espindola
c6e7790c4b Add X86::reloc_global_offset_table and use it to have a single place where 
we check for _GLOBAL_OFFSET_TABLE_.

llvm-svn: 117241
 2010-10-24 17:35:42 +00:00
Benjamin Kramer
ed68a7877c Make the disassembler tables const so they end up in read-only memory. 
llvm-svn: 117206
 2010-10-23 09:10:44 +00:00
Michael J. Spencer
87c8212d41 X86: Emit _fltused instead of __fltused on Windows x64. 
llvm-svn: 117205
 2010-10-23 09:06:59 +00:00
Chandler Carruth
ea67aaa252 Remove a define which is never referenced. 
llvm-svn: 117202
 2010-10-23 08:25:16 +00:00
Chandler Carruth
7799a873bb Switch attribute macros to use 'LLVM_' as a prefix. We retain the old names 
until other LLVM projects using these are cleaned up.

llvm-svn: 117200
 2010-10-23 08:10:43 +00:00
Wesley Peck
488027efa3 Making the e_machine configurable by the target backend in ELFObjectWriter. 
llvm-svn: 117099
 2010-10-22 15:52:49 +00:00
Andrew Trick
b9e8700beb Reverting r117031 to cleanup valgrind errors. 
It doesn't look like anything is wrong with the checkin,
but the new test cases expose a mem bug in AsmParser.

llvm-svn: 117087
 2010-10-22 03:58:29 +00:00
Sean Callanan
9a40554de4 Fixed handling of immediate operand sizes, which 
weren't properly reflecting the OperandSize attribute
of the instruction leading to improper decoding of
certain instructions with the 66H prefix.  Also added
a test case for this.

llvm-svn: 117084
 2010-10-22 01:24:11 +00:00
Kevin Enderby
c63105a064 More tweaks to X86 instructions to allow the 'w' suffix in places it makes 
sense, when the instruction takes the 16-bit ax register or m16 memory
location.  These changes to llvm-mc matches what the darwin assembler allows
for these instructions.  Also added the missing flex (without the wait prefix)
and ud2a as an alias to ud2 (still to add ud2b).

llvm-svn: 117031
 2010-10-21 17:16:46 +00:00
Duncan Sands
0c166168a0 Remove some variables that are never really used 
(gcc-4.6 warns about these).

llvm-svn: 117021
 2010-10-21 16:03:28 +00:00
Duncan Sands
8c5f243aa0 Add parentheses to pacify gcc, which warns otherwise. 
llvm-svn: 117020
 2010-10-21 16:02:12 +00:00
Michael J. Spencer
5a68d7ce94 X86: Add alloca probing to dynamic alloca on Windows. Fixes PR8424. 
llvm-svn: 116984
 2010-10-21 01:41:01 +00:00
Michael J. Spencer
b9cffadc06 CodeGen-Windows: Only emit _fltused if a VarArg function is called with floating point args. 
This should be the minimum set of functions that could possibly need it.

llvm-svn: 116978
 2010-10-21 00:08:21 +00:00
Michael J. Spencer
54b462089f Fix Whitespace. 
llvm-svn: 116972
 2010-10-20 23:40:27 +00:00
Dale Johannesen
58fe3193a6 Remove Synthesizable from the Type system; as MMX vector 
types are no longer Legal on X86, we don't need it.
No functional change.  8499854.

llvm-svn: 116947
 2010-10-20 21:32:10 +00:00
Rafael Espindola
0a50bbaee1 Handle _GLOBAL_OFFSET_TABLE_ correctly. 
llvm-svn: 116932
 2010-10-20 16:46:08 +00:00
Evan Cheng
1c8dafd12a Re-enable register pressure aware machine licm with fixes. Hoist() may have 
erased the instruction during LICM so UpdateRegPressureAfter() should not
reference it afterwards.

llvm-svn: 116845
 2010-10-19 18:58:51 +00:00
Daniel Dunbar
6ff550c84d Revert r116781 "- Add a hook for target to determine whether an instruction def 
is", which breaks some nightly tests.

llvm-svn: 116816
 2010-10-19 17:14:24 +00:00
Michael J. Spencer
e528f2588f X86: Add MS-CRT libcalls. 
llvm-svn: 116801
 2010-10-19 07:32:52 +00:00
Michael J. Spencer
cd6be63d05 Fix Whitespace. 
llvm-svn: 116800
 2010-10-19 07:32:42 +00:00
Evan Cheng
9c3f6f486e - Add a hook for target to determine whether an instruction def is 
"long latency" enough to hoist even if it may increase spilling. Reloading
  a value from spill slot is often cheaper than performing an expensive
  computation in the loop. For X86, that means machine LICM will hoist
  SQRT, DIV, etc. ARM will be somewhat aggressive with VFP and NEON
  instructions.
- Enable register pressure aware machine LICM by default.

llvm-svn: 116781
 2010-10-19 00:55:07 +00:00
Kevin Enderby
8a3030c6af Added a few tweaks to the Intel Descriptor-table support instructions to allow 
word forms and suffixed versions to match the darwin assembler in 32-bit and
64-bit modes.  This is again for use just with assembly source for llvm-mc .

llvm-svn: 116773
 2010-10-19 00:01:44 +00:00
Rafael Espindola
7cc236c87f Produce ELF::R_386_GOTPC relocations. 
llvm-svn: 116728
 2010-10-18 18:36:12 +00:00
Kevin Enderby
cb18d38b76 Added a handful of x86-32 instructions that were missing so that llvm-mc would 
be more complete.  These are only expected to be used by llvm-mc with assembly
source so there is no pattern, [], in the .td files.  Most are being added to
X86InstrInfo.td as Chris suggested and only comments about register uses are
added.  Suggestions welcome on the .td changes as I'm not sure on every detail
of the x86 records.  More missing instructions will be coming.

llvm-svn: 116716
 2010-10-18 17:04:36 +00:00
Rafael Espindola
be5c52d2dc Add a MCObjectFormat class so that code common to all targets that use a 
single object format can be shared.

This also adds support for

mov zed+(bar-foo), %eax

on ELF and COFF targets.

llvm-svn: 116675
 2010-10-16 18:23:53 +00:00
Michael J. Spencer
e57b670425 X86-Windows: Emit an undefined global __fltused symbol when targeting Windows 
if any floating point arguments are passed to an external function.

llvm-svn: 116665
 2010-10-16 08:25:41 +00:00
Rafael Espindola
b1ae74bd73 Fix another case where we were preferring instructions with large 
immediates instead of 8 bits ones.

llvm-svn: 116410
 2010-10-13 17:14:25 +00:00
Rafael Espindola
ff7f11c151 Fix PR8365 by adding a more specialized Pat that checks if an 'and' with 
8 bit constants can be used.

llvm-svn: 116403
 2010-10-13 13:31:20 +00:00
Evan Cheng
eefee972cf Turn some fp stackifier assertion into errors to avoid silently generating bad code when assertions are off. rdar://8540457. 
llvm-svn: 116368
 2010-10-12 23:19:28 +00:00
Eric Christopher
303692631e Combine these together - should probably have some text associated 
that says what why what we just asserted is wrong.

llvm-svn: 116333
 2010-10-12 19:44:17 +00:00
Nick Lewycky
a6815ae877 Mark variable 'NoImplicitFloatOps' used only in an assert as used. 
llvm-svn: 116323
 2010-10-12 18:18:03 +00:00
Dan Gohman
d904add908 Initial va_arg support for x86-64. Patch by David Meyer! 
llvm-svn: 116319
 2010-10-12 18:00:49 +00:00
Jakob Stoklund Olesen
499fe39d23 Remove the x86 MOV{32,64}{rr,rm,mr}_TC instructions. 
The reg-reg copies were no longer being generated since copyPhysReg copies
physical registers only.

The loads and stores are not necessary - The TC constraint is imposed by the
TAILJMP and TCRETURN instructions, there should be no need for constrained loads
and stores.

llvm-svn: 116314
 2010-10-12 17:15:00 +00:00
Andrew Trick
5704a15e36 Fixes bug 8297: i386 cmpxchg8b, missing MachineMemOperand 
llvm-svn: 116214
 2010-10-11 19:02:04 +00:00
Michael J. Spencer
08b96a9209 X86: Call ulldiv and ftol2 on Windows instead of their libgcc eqivilents. 
llvm-svn: 116188
 2010-10-11 05:29:15 +00:00
Michael J. Spencer
8f7251a0e9 X86: MinGW should always use libgcc on Windows. 
llvm-svn: 116177
 2010-10-10 23:11:06 +00:00
Michael J. Spencer
b13cb4dd72 X86: Call _alldiv instead of __divdi3 on Windows (excluding cygwin). 
llvm-svn: 116174
 2010-10-10 22:04:34 +00:00
Michael J. Spencer
ae56350c76 Fix Whitespace. 
llvm-svn: 116173
 2010-10-10 22:04:20 +00:00
Michael J. Spencer
1c60bd155b Fix Whitespace. 
llvm-svn: 116149
 2010-10-09 11:00:50 +00:00
Chris Lattner
68ff81a2e6 add jit support for the new psuedo instructions I added for 
the add/or xform.  The JIT isn't mcized yet, boo.

This fixes Olden/voronoi, bh and a ton of other stuff that
uses the jit.

llvm-svn: 116125
 2010-10-08 23:59:27 +00:00
Chris Lattner
2176ca6377 machine a mutable machineinstr down into emitInstruction. 
llvm-svn: 116124
 2010-10-08 23:54:01 +00:00
Cameron Esfahani
664317d6cd Recommit 116056, now with the missing file... 
llvm-svn: 116083
 2010-10-08 19:24:18 +00:00
Andrew Trick
0d8a3d67e0 reverting 116056: win64_params.ll may need to be conditionalized? 
llvm-svn: 116063
 2010-10-08 17:22:42 +00:00
Cameron Esfahani
a9f8bb1356 Small patch to restore home register stack space allocation for the Win64 case. Add test case. This code eventually needs to be tighter, since it's always allocating it, even in leaf routines. 
llvm-svn: 116056
 2010-10-08 10:31:30 +00:00
Chris Lattner
244e13f439 fix a subtle bug I introduced in my refactoring, where we stopped preferring 
the i8 versions of instructions in some cases.  In test6, we started 
generating:

	cmpq	$0, -8(%rsp)            ## encoding: [0x48,0x81,0x7c,0x24,0xf8,0x00,0x00,0x00,0x00]
                                        ## <MCInst #478 CMP64mi32
                                        ##  <MCOperand Reg:114>
                                        ##  <MCOperand Imm:1>
                                        ##  <MCOperand Reg:0>
                                        ##  <MCOperand Imm:-8>
                                        ##  <MCOperand Reg:0>
                                        ##  <MCOperand Imm:0>>

instead of:

	cmpq	$0, -8(%rsp)            ## encoding: [0x48,0x83,0x7c,0x24,0xf8,0x00]
                                        ## <MCInst #479 CMP64mi8
                                        ##  <MCOperand Reg:114>
                                        ##  <MCOperand Imm:1>
                                        ##  <MCOperand Reg:0>
                                        ##  <MCOperand Imm:-8>
                                        ##  <MCOperand Reg:0>
                                        ##  <MCOperand Imm:0>>

Fix this and add some comments.

llvm-svn: 116053
 2010-10-08 05:12:14 +00:00
Chris Lattner
82ce325f16 reapply: Use the new TB_NOT_REVERSABLE flag instead of special 
reapply: reimplement the second half of the or/add optimization.  We should now

with no changes.  Turns out that one missing "Defs = [EFLAGS]" can upset things
a bit.

llvm-svn: 116040
 2010-10-08 03:57:25 +00:00
Chris Lattner
fbdd285dd6 reapply the patch reverted in r116033: 
"Reimplement (part of) the or -> add optimization.  Matching 'or' into 'add'"

With a critical fix: the add pseudos clobber EFLAGS.

llvm-svn: 116039
 2010-10-08 03:54:52 +00:00
Daniel Dunbar
d3b6b8bf2b Revert "Reimplement (part of) the or -> add optimization. Matching 'or' into 
'add'", which seems to have broken just about everything.

llvm-svn: 116033
 2010-10-08 02:07:32 +00:00
Daniel Dunbar
59848f6703 Revert "Use the new TB_NOT_REVERSABLE flag instead of special ", which depends 
on r116007, which I am about to revert.

llvm-svn: 116032
 2010-10-08 02:07:29 +00:00
Daniel Dunbar
983fae5a86 Revert "reimplement the second half of the or/add optimization. We should now", 
which depends on r116007, which I am about to revert.

llvm-svn: 116031
 2010-10-08 02:07:26 +00:00
Chris Lattner
7577cb7b49 reimplement the second half of the or/add optimization. We should now 
only end up emitting LEA instead of OR.  If we aren't able to promote
something into an LEA, we should never be emitting it as an ADD.

Add some testcases that we emit "or" in cases where we used to produce
an "add".

llvm-svn: 116026
 2010-10-08 01:05:10 +00:00
Chris Lattner
d62e94b465 Use the new TB_NOT_REVERSABLE flag instead of special 
casing FsMOVAPDrr/FsMOVAPSrr.

llvm-svn: 116016
 2010-10-08 00:03:02 +00:00
Chris Lattner
72e7e84c3f simplify some map operations. 
llvm-svn: 116014
 2010-10-07 23:57:02 +00:00
Chris Lattner
d8f05bf65e Reimplement (part of) the or -> add optimization. Matching 'or' into 'add' 
is general goodness because it allows ORs to be converted to LEA to avoid
inserting copies.  However, this is bad because it makes the generated .s
file less obvious and gives valgrind heartburn (tons of false positives in
bitfield code).

While the general fix should be in valgrind, we can at least try to avoid
emitting ADD instructions that *don't* get promoted to LEA.  This is more
work because it requires introducing pseudo instructions to represents
"add that knows the bits are disjoint", but hey, people really love valgrind.

This fixes this testcase:
https://bugs.kde.org/show_bug.cgi?id=242137#c20

the add r/i cases are coming next.

llvm-svn: 116007
 2010-10-07 23:36:18 +00:00
Chris Lattner
2212441ff7 Reduce casting in various tables by defining the table 
with the right types.

llvm-svn: 116001
 2010-10-07 23:08:41 +00:00
Chris Lattner
17850b2677 simplify code: don't build up vector only to assert it is empty. 
llvm-svn: 115997
 2010-10-07 22:26:19 +00:00
Chris Lattner
16aa36001d convert test to use the existing classes that the multipatterns 
use.  Since TEST is completely different than all other binops,
don't define a multipattern for it.

This completes factorization of binops.

llvm-svn: 115982
 2010-10-07 21:31:03 +00:00
Chris Lattner
bd89233607 convert cmp to use a multipattern 
llvm-svn: 115978
 2010-10-07 20:56:25 +00:00
Evan Cheng
7c89d70f27 Canonicalize X86ISD::MOVDDUP nodes to v2f64 to make sure all cases match. Also eliminate unneeded isel patterns. rdar://8520311 
llvm-svn: 115977
 2010-10-07 20:50:20 +00:00
Chris Lattner
4b9e6fd743 reduce redundancy between pattern copies. 
llvm-svn: 115968
 2010-10-07 20:14:23 +00:00
Chris Lattner
41b3817cbd the opcode for BinOpMI/BinOpMI8 is always the same, remove the argument. 
llvm-svn: 115967
 2010-10-07 20:06:24 +00:00
Chris Lattner
d7f7dc04f5 convert adc/sbb to a multipattern. Because the adde/sube nodes 
are not defined as returning EFLAGS (like add_flag and friends),
the entire multipattern and several of the subclasses need to be
cloned.

This could be handled through better instantiation support in tblgen,
but it isn't meta enough.

llvm-svn: 115964
 2010-10-07 20:01:55 +00:00
Jakob Stoklund Olesen
7f38b44415 Fix obvious mistake pointed out by Michael Spencer. 
llvm-svn: 115952
 2010-10-07 18:47:10 +00:00
Chris Lattner
f0d9834e08 add support for isConvertibleToThreeAddress to ArithBinOpEFLAGS, 
allowing us to convert ADD over.  deletes 160 lines of .td file.

llvm-svn: 115897
 2010-10-07 01:37:01 +00:00
Chris Lattner
dea1395cfe Fix a few issues in ArithBinOpEFLAGS that made it specific to and. 
Start using ArithBinOpEFLAGS for OR, XOR, and SUB.

This removes 500 lines from the .td file.  Now AND/OR/XOR/SUB are all
defined exactly the same way instead of being close relatives.

llvm-svn: 115896
 2010-10-07 01:26:27 +00:00
Chris Lattner
f1f5df212b Convert 'and' to single instance of a multipattern 
which instantiates the 34 versions of and all in one
swoop.  The BaseOpc/BaseOpc2/BaseOpc4 stuff should not
be required, but tblgen's feeble brain explodes when I
use Or4<BaseOpc>.V in the multipattern.

No change in the generated .inc files.

llvm-svn: 115893
 2010-10-07 01:10:20 +00:00
Chris Lattner
a2b51bb341 add a new BinOpAI class to represent the immediate form that directly acts on EAX. 
This does change the generated .inc files to include the implicit use/def of eax.
Since these instructions are only generated by the assembler and disassembler it
doesn't actually matter though.

llvm-svn: 115885
 2010-10-07 00:43:39 +00:00
Chris Lattner
0df71280d1 add a bunch of classes for other common patterns. 
As usual, no change in generated .inc files.

llvm-svn: 115882
 2010-10-07 00:35:28 +00:00
Chris Lattner
9b3a494cdb Define a new BinOpRI8 class and use it to define the imm8 versions of and. 
llvm-svn: 115880
 2010-10-07 00:12:45 +00:00
Jakob Stoklund Olesen
5e329859cd Constrain the offset register to a *_NOSP register class when inserting LEA 
instructions.

This unbreaks the machine code verifier and fixes PR8317.

llvm-svn: 115879
 2010-10-07 00:07:26 +00:00
Chris Lattner
b520abade4 add the pattern operator to match to X86TypeInfo, use this to 
convert AND64ri32 to use BinOpRI.

llvm-svn: 115878
 2010-10-07 00:01:39 +00:00
Jakob Stoklund Olesen
8c1eafb4cb Properly handle GR32_NOSP in X86RegisterInfo::getMatchingSuperRegClass. 
This function looks like it is about ready to be generated by TebleGen.

llvm-svn: 115876
 2010-10-06 23:56:46 +00:00
Chris Lattner
30c9a175a3 enhance X86TypeInfo to include information about the encoding and 
operand kind for immediates.  Use these to define a new BinOpRI
class and switch AND8/16/32ri over to it.  AND64ri32 needs some
more refactoring before it can make the switcheroo.

llvm-svn: 115752
 2010-10-06 05:55:42 +00:00
Chris Lattner
e9e2d51853 add a class for _REV nodes. 
llvm-svn: 115748
 2010-10-06 05:35:22 +00:00
Chris Lattner
88ccb4e6b5 sink more intelligence into the ITy base class. Now it knows 
that i8 operations are even and i16,i32,i64 operations have a
low opcode bit set (they are odd).

llvm-svn: 115747
 2010-10-06 05:28:38 +00:00
Chris Lattner
96dd50c055 refactor things a bit, now the REX_W and OpSize prefix bytes are inferred from the type info. 
llvm-svn: 115745
 2010-10-06 05:20:57 +00:00
Chris Lattner
7956e6b995 with tblgen suitably extended, we can now get the load node from typeinfo. 
llvm-svn: 115744
 2010-10-06 04:58:43 +00:00
Chris Lattner
5b3e46bd6b lets go all meta and define new X86 type wrappers that declare the associated 
gunk that goes along with an MVT (e.g. reg class, preferred load operation,
memory operand)

llvm-svn: 115727
 2010-10-06 00:45:24 +00:00
Chris Lattner
e979874e3f introduce a new BinOpRM class and use it to factor AND*rm. This points out 
that I need a heavier handed approach to get ultimate factorization.

llvm-svn: 115726
 2010-10-06 00:30:49 +00:00
Chris Lattner
84846b71af remove the !nameconcat tblgen feature. It "shorthand" and only used in 4 places 
where !cast is just as short.

llvm-svn: 115722
 2010-10-06 00:19:21 +00:00
Chris Lattner
12274b9845 allow !strconcat to take more than two operands to eliminate 
!strconcat(!strconcat(!strconcat(!strconcat

Simplify some x86 td files to use it.

llvm-svn: 115719
 2010-10-05 23:58:18 +00:00
Chris Lattner
dd8227d488 associate the instruction suffix letter with the integer gpr 
register class, and use this to simplify use of BinOpRR.

llvm-svn: 115716
 2010-10-05 23:43:04 +00:00
Chris Lattner
dd4c597e38 introduce a new BinOpRR class, and convert 4 and instructions to use it. 
llvm-svn: 115715
 2010-10-05 23:32:05 +00:00
Chris Lattner
ef2e024af8 Move cmov pseudo instructions to InstrCompiler, 
convert all the rest of the cmovs to the multiclass,
with good results:

 X86InstrCMovSetCC.td |  598 +--------------------------------------------------
 X86InstrCompiler.td  |   61 +++++
 2 files changed, 77 insertions(+), 582 deletions(-)

llvm-svn: 115707
 2010-10-05 23:09:10 +00:00
Chris Lattner
195a9c3877 Use #NAME# to have the CMOV multiclass define things with the same names as before 
(e.g. CMOVBE16rr instead of CMOVBErr16).

llvm-svn: 115705
 2010-10-05 23:00:14 +00:00
Chris Lattner
3357066875 enhance tblgen to support anonymous defm's, use this to 
simplify the X86 CMOVmr's.

llvm-svn: 115702
 2010-10-05 22:51:56 +00:00
Chris Lattner
b2ac22f0a4 convert cmov mr patterns to use a multipattern. Death to redundancy 
and verbosity

llvm-svn: 115701
 2010-10-05 22:42:54 +00:00
Chris Lattner
c3c03dfeff switch CMOVBE to the multipattern: 
21 insertions(+), 53 deletions(-)

Moar change coming before I switch the rest.

llvm-svn: 115697
 2010-10-05 22:23:58 +00:00
Chris Lattner
5673933e30 fix a bug I introduced in r115669, which ended up with MOV64mr_TC 
not getting marked as mayStore.  This fixes llvm-gcc bootstrap.

llvm-svn: 115693
 2010-10-05 22:16:48 +00:00
Chris Lattner
a5c35bed7b add a multiclass for cmov's, but don't start using it yet. 
llvm-svn: 115692
 2010-10-05 22:01:02 +00:00
Chris Lattner
7065387c35 use a multipattern to define setcc instructions: 
X86InstrCMovSetCC.td |  200 ++++++---------------------------------------------
 1 file changed, 27 insertions(+), 173 deletions(-)

llvm-svn: 115689
 2010-10-05 21:34:29 +00:00
Chris Lattner
fa6f058b70 move SETB pseudos into the same place in InstrCompiler.td 
llvm-svn: 115686
 2010-10-05 21:18:04 +00:00
Chris Lattner
ca34143ddd Replace a gross hack (the MOV64ri_alt instruction) with a slightly less 
gross hack (having the asmmatcher handle the alias).

llvm-svn: 115685
 2010-10-05 21:09:45 +00:00
Chris Lattner
5d7d5a81eb distribute the rest of the contents of X86Instr64bit.td out to 
the right places.  X86Instr64bit.td now dies, long live x86-64!

llvm-svn: 115669
 2010-10-05 20:49:15 +00:00
Chris Lattner
c06e348ff8 move the rest of the simple 64-bit arithmetic into InstrArithmetic.td 
llvm-svn: 115663
 2010-10-05 20:35:37 +00:00
Chris Lattner
80ffcbd80a continue moving 64-bit stuff into X86InstrArithmetic.td 
llvm-svn: 115660
 2010-10-05 20:23:31 +00:00
Chris Lattner
aae0403342 move 64-bit add and adc to InstrArithmetic. 
llvm-svn: 115632
 2010-10-05 16:59:08 +00:00
Chris Lattner
f5f0742885 rewrote two addr constraints so that they are only set, not set and then nestedly cleared. 
llvm-svn: 115631
 2010-10-05 16:52:25 +00:00
Chris Lattner
cdf60fcc21 split the 32-bit integer arithmetic instructions out to their own file. 
llvm-svn: 115627
 2010-10-05 16:39:12 +00:00
Chris Lattner
4cf3aff9c1 integrate the 64-bit shifts into X86InstrShiftRotate.td. Enough for tonight. 
llvm-svn: 115608
 2010-10-05 07:13:35 +00:00
Chris Lattner
3d1c1ff4c2 move 32-bit shift and rotates out to their own file. 
llvm-svn: 115607
 2010-10-05 07:00:12 +00:00
Chris Lattner
40954218dd add new file 
llvm-svn: 115606
 2010-10-05 06:52:35 +00:00
Chris Lattner
1c0cbe9571 move sign and zero extensions out to their own file. 
llvm-svn: 115605
 2010-10-05 06:52:26 +00:00
Chris Lattner
12a0f5c3bd move some instructions from Instr64Bit -> InstrInfo. 
bswap32 doesn't read eflags.

llvm-svn: 115604
 2010-10-05 06:47:35 +00:00
Chris Lattner
9317bf2ed5 move CMOV_FR32 and friends to InstrCompiler, since they are 
pseudo instructions.

Move POPCNT to InstrSSE since they are SSE4 instructions.

llvm-svn: 115603
 2010-10-05 06:41:40 +00:00
Chris Lattner
d96f3fe646 move various pattern matching support goop out of X86Instr64Bit, to live 
with the 32-bit stuff.

llvm-svn: 115602
 2010-10-05 06:37:31 +00:00
Chris Lattner
7451cc0f59 split conditional moves and setcc's out to their own file. 
llvm-svn: 115601
 2010-10-05 06:33:16 +00:00
Chris Lattner
7114e187e1 move string pseudo instructions to InstrCompiler consolidate 64-bit and 32-bit together. 
llvm-svn: 115600
 2010-10-05 06:27:48 +00:00
Chris Lattner
e63d763713 move the atomic pseudo instructions out to X86InstrCompiler.td 
llvm-svn: 115599
 2010-10-05 06:22:35 +00:00
Chris Lattner
a2e5444bb4 move more pseudo instructions out to X86InstrCompiler.td 
llvm-svn: 115598
 2010-10-05 06:10:16 +00:00
Chris Lattner
383d15c9d8 move VMX instructions out to their own file. 
llvm-svn: 115597
 2010-10-05 06:06:53 +00:00
Chris Lattner
5f59acddbc continue moving stuff out to X86InstrSystem.td. Move 
control flow stuff out to X86InstrControl.td.  Move
some compiler pseudo instructions and Pat<> patterns
out to X86InstrCompiler.td

llvm-svn: 115596
 2010-10-05 06:04:14 +00:00
Chris Lattner
db65ba5acf refactor .td files a bit, moving system instructions out to X86InstrSystem.td 
llvm-svn: 115591
 2010-10-05 05:32:15 +00:00