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Commit Graph

288 Commits

Author SHA1 Message Date
Jyotsna Verma
a3587dd6bb Hexagon: Use multiclass for Jump instructions.
llvm-svn: 180885
2013-05-01 21:37:34 +00:00
Jyotsna Verma
d290020e45 Hexagon: Clear isKill flag on the predicate register in
PredicateInstruction function.

llvm-svn: 180884
2013-05-01 21:27:30 +00:00
Jyotsna Verma
4a5d195942 Hexagon: Use multiclass for combine and STri[bhwd]_shl_V4 instructions.
llvm-svn: 180145
2013-04-23 21:17:40 +00:00
Jyotsna Verma
d985cbcb4e Hexagon: Define relations for GP-relative instructions.
No functionality change.

llvm-svn: 180144
2013-04-23 21:05:55 +00:00
Jyotsna Verma
624f2e0434 Hexagon: Remove assembler mapped instruction definitions.
llvm-svn: 180133
2013-04-23 19:15:55 +00:00
Jyotsna Verma
20903a7aba Hexagon: Remove duplicate instructions to handle global/immediate values
for absolute/absolute-set addressing modes.

llvm-svn: 180120
2013-04-23 17:11:46 +00:00
Tim Northover
d12b2f24c8 Remove unused MEMBARRIER DAG node; it's been replaced by ATOMIC_FENCE.
llvm-svn: 179939
2013-04-20 12:32:17 +00:00
Michael Liao
3b258b6b24 ArrayRefize getMachineNode(). No functionality change.
llvm-svn: 179901
2013-04-19 22:22:57 +00:00
Jyotsna Verma
f365070e16 Hexagon: Set isPredicatedNew flag on predicate new instructions.
llvm-svn: 179388
2013-04-12 18:01:06 +00:00
Jyotsna Verma
a7ba594fa9 Hexagon: Set isPredicatedFlase flag for all the instructions with negated predication.
llvm-svn: 179387
2013-04-12 17:46:52 +00:00
Jyotsna Verma
c3ebace56c Hexagon: Expand br_cc.
It fixes following tests for Hexagon:

CodeGen/Generic/2003-07-29-BadConstSbyte.ll
CodeGen/Generic/2005-10-21-longlonggtu.ll
CodeGen/Generic/2009-04-28-i128-cmp-crash.ll
CodeGen/Generic/MachineBranchProb.ll
CodeGen/Generic/builtin-expect.ll
CodeGen/Generic/pr12507.ll

llvm-svn: 178794
2013-04-04 21:18:26 +00:00
Duncan Sands
3137dc79c4 Remove unused typedef.
llvm-svn: 178462
2013-04-01 13:46:15 +00:00
Duncan Sands
25d8fd3fd9 There is no longer any need to silence this compiler warning as the warning has
been turned off globally.

llvm-svn: 178451
2013-03-31 17:44:09 +00:00
Jyotsna Verma
91f1858936 Hexagon: Add emitFrameIndexDebugValue function to emit debug information.
llvm-svn: 178368
2013-03-29 21:09:53 +00:00
Jyotsna Verma
c91629764d Hexagon: Disable DwarfUsesInlineInfoSection flag.
llvm-svn: 178345
2013-03-29 15:46:12 +00:00
Jyotsna Verma
912f8ff9d4 Hexagon: Replace switch-case in isDotNewInst with TSFlags.
llvm-svn: 178281
2013-03-28 19:44:04 +00:00
Jyotsna Verma
f28cc49519 Hexagon: Enable SupportDebugInfomation and DwarfInSection flags.
llvm-svn: 178279
2013-03-28 19:34:49 +00:00
Jyotsna Verma
8a524534a6 Hexagon: Use multiclass for gp-relative instructions.
Remove noV4T gp-relative instructions.

llvm-svn: 178246
2013-03-28 16:25:57 +00:00
Tim Northover
d4f188256e Switch to LLVM support function abs64 to keep VS2008 happy.
llvm-svn: 178141
2013-03-27 13:15:08 +00:00
Jyotsna Verma
d52d76ad2e Hexagon: Disable optimizations at O0.
llvm-svn: 178132
2013-03-27 11:14:24 +00:00
Jyotsna Verma
665c66e6ea Hexagon: Use multiclass for aslh, asrh, sxtb, sxth, zxtb and zxth.
llvm-svn: 178032
2013-03-26 15:43:57 +00:00
Jyotsna Verma
63189bde20 Hexagon: Remove HexagonMCInst.h file. It has been replaced with MCTargetDesc/HexagonMCInst.h.
llvm-svn: 178030
2013-03-26 15:34:22 +00:00
Jyotsna Verma
fa7dec4e5b Hexagon: Add and enable memops setbit, clrbit, &,|,+,- for byte, short, and word.
llvm-svn: 177747
2013-03-22 18:41:34 +00:00
Jyotsna Verma
f2d3c71cf4 Hexagon: Removed asserts regarding alignment and offset.
We are warning the user about the alignment, so we should not assert.

llvm-svn: 177103
2013-03-14 19:08:03 +00:00
Jakub Staszak
0e54bb7776 Cleanup #includes.
llvm-svn: 176787
2013-03-10 13:11:23 +00:00
Tom Stellard
fa72758e1d DAGCombiner: Use correct value type for checking legality of BR_CC v3
LegalizeDAG.cpp uses the value of the comparison operands when checking
the legality of BR_CC, so DAGCombiner should do the same.

v2:
  - Expand more BR_CC value types for NVPTX

v3:
  - Expand correct BR_CC value types for Hexagon, Mips, and XCore.

llvm-svn: 176694
2013-03-08 15:36:57 +00:00
Jyotsna Verma
6ba1f8e0d8 Hexagon: Add patterns for zero extended loads from i1->i64.
llvm-svn: 176689
2013-03-08 14:15:15 +00:00
Jyotsna Verma
50e5f420d7 Hexagon: Handle i8, i16 and i1 Var Args.
llvm-svn: 176647
2013-03-07 20:28:34 +00:00
Jyotsna Verma
c3d8f08545 Hexagon: Add support to lower block address.
llvm-svn: 176637
2013-03-07 19:10:28 +00:00
Jyotsna Verma
e27b88fb08 reverting patch 176508.
llvm-svn: 176513
2013-03-05 20:29:23 +00:00
Jyotsna Verma
ef3cf2b345 Hexagon: Add support for lowering block address.
llvm-svn: 176508
2013-03-05 19:37:46 +00:00
Jyotsna Verma
baf7212bfe Hexagon: Expand addc, adde, subc and sube.
llvm-svn: 176505
2013-03-05 19:04:47 +00:00
Jyotsna Verma
ce778f77cd Hexagon: Use MO operand flags to mark constant extended instructions.
llvm-svn: 176500
2013-03-05 18:51:42 +00:00
Jyotsna Verma
c096fbaa7d Hexagon: Add encoding bits to the TFR64 instructions.
Set imMoveImm, isAsCheapAsAMove flags for TFRI instructions.

llvm-svn: 176499
2013-03-05 18:42:28 +00:00
Andrew Trick
bc662b6282 Added FIXME for future Hexagon cleanup.
llvm-svn: 176400
2013-03-02 01:43:08 +00:00
Jyotsna Verma
359daa8ad9 Hexagon: Add constant extender support framework.
llvm-svn: 176358
2013-03-01 17:37:13 +00:00
Andrew Trick
7abe8180da Remove code copied from GenRegisterInfo.inc.
There's no apparent reason this code was copied from generated source
into a .cpp. It sets a bad example for those working on other targets
and trying to understand the register info API.

llvm-svn: 175849
2013-02-22 01:15:08 +00:00
Eli Bendersky
37f247b8d8 Move the eliminateCallFramePseudoInstr method from TargetRegisterInfo
to TargetFrameLowering, where it belongs. Incidentally, this allows us
to delete some duplicated (and slightly different!) code in TRI.

There are potentially other layering problems that can be cleaned up
as a result, or in a similar manner.

The refactoring was OK'd by Anton Korobeynikov on llvmdev.

Note: this touches the target interfaces, so out-of-tree targets may
be affected.

llvm-svn: 175788
2013-02-21 20:05:00 +00:00
Anshuman Dasgupta
810cccb843 Hexagon: Expand cttz, ctlz, and ctpop for now.
llvm-svn: 175783
2013-02-21 19:39:40 +00:00
Jim Grosbach
233487d8a2 Update TargetLowering ivars for name policy.
http://llvm.org/docs/CodingStandards.html#name-types-functions-variables-and-enumerators-properly

ivars should be camel-case and start with an upper-case letter. A few in
TargetLowering were starting with a lower-case letter.

No functional change intended.

llvm-svn: 175667
2013-02-20 21:13:59 +00:00
Jyotsna Verma
84136133e3 Hexagon: Move HexagonMCInst.h to MCTargetDesc/HexagonMCInst.h.
Add HexagonMCInst class which adds various Hexagon VLIW annotations.
In addition, this class also includes some APIs related to the
constant extenders.

llvm-svn: 175634
2013-02-20 16:13:27 +00:00
Jyotsna Verma
3b0f6f5216 Hexagon: Sync TSFlags in MCTargetDesc/HexagonBaseInfo.h with
HexagonInstrFormats.td.

llvm-svn: 175537
2013-02-19 18:18:36 +00:00
Jyotsna Verma
483fcc523c Hexagon: Set appropriate TSFlags to the loads/stores with global address to
support constant extension.

This patch doesn't introduce any functionality changes.

llvm-svn: 175280
2013-02-15 17:52:07 +00:00
Jyotsna Verma
8fb6be0cdc Hexagon: Change insn class to support instruction encoding.
This patch doesn't introduce any functionality changes.
It adds some new fields to the Hexagon instruction classes and
changes their layout to support instruction encoding.

llvm-svn: 175205
2013-02-14 19:57:17 +00:00
Jyotsna Verma
38aab141d7 Hexagon: Use multiclass for absolute addressing mode loads.
This patch doesn't introduce any functionality changes.

llvm-svn: 175187
2013-02-14 18:15:29 +00:00
Anshuman Dasgupta
a6322b9e0a Hexagon: add support for predicate-GPR copies.
llvm-svn: 175102
2013-02-13 22:56:34 +00:00
Jyotsna Verma
a382dbb48f Hexagon: Use absolute addressing mode loads/stores for global+offset
instead of redefining separate instructions for them.

llvm-svn: 175086
2013-02-13 21:38:46 +00:00
Andrew Trick
4cce0af4e9 MIsched: HazardRecognizers are created for each DAG. Free them.
llvm-svn: 175067
2013-02-13 19:22:27 +00:00
Jyotsna Verma
abd979fd30 Hexagon: Add support to generate predicated absolute addressing mode
instructions.

llvm-svn: 174973
2013-02-12 16:06:23 +00:00
Krzysztof Parzyszek
272abb00e0 Extend Hexagon hardware loop generation to handle various additional cases:
- variety of compare instructions,
- loops with no preheader,
- arbitrary lower and upper bounds.

llvm-svn: 174904
2013-02-11 21:37:55 +00:00
Krzysztof Parzyszek
b814fd5e20 Implement HexagonInstrInfo::analyzeCompare.
llvm-svn: 174901
2013-02-11 20:04:29 +00:00
Jyotsna Verma
31124b1816 Hexagon: Use TFR_cond with cmpb.[eq,gt,gtu] to handle
zext( set[ne,eq,gt,ugt] (...) ) type of dag patterns.

llvm-svn: 174429
2013-02-05 19:20:45 +00:00
Jyotsna Verma
774837ab41 Hexagon: Use multiclass for absolute addressing mode stores.
llvm-svn: 174412
2013-02-05 18:15:34 +00:00
Jakob Stoklund Olesen
8dec74fcef Move MRI liveouts to Hexagon return instructions.
llvm-svn: 174407
2013-02-05 18:08:43 +00:00
Jyotsna Verma
56ef42a2ac Hexagon: Add V4 compare instructions. Enable relationship mapping
for the existing instructions.

llvm-svn: 174389
2013-02-05 16:42:24 +00:00
Jyotsna Verma
e97a68f8b5 Hexagon: Add V4 combine instructions and some more Def Pats for V2.
llvm-svn: 174331
2013-02-04 15:52:56 +00:00
Jyotsna Verma
460af8cdc9 Replace LDriu*[bhdw]_indexed_V4 instructions with "def Pats".
llvm-svn: 174193
2013-02-01 16:36:16 +00:00
Jyotsna Verma
3896fefde4 Add appropriate TSFlags to the instructions that must be always extended.
llvm-svn: 174186
2013-02-01 15:54:43 +00:00
Chad Rosier
ebbd4433e6 [PEI] Pass the frame index operand number to the eliminateFrameIndex function.
Each target implementation was needlessly recomputing the index.
Part of rdar://13076458

llvm-svn: 174083
2013-01-31 20:02:54 +00:00
Jyotsna Verma
189807572e Use multiclass for post-increment store instructions.
llvm-svn: 173816
2013-01-29 18:42:41 +00:00
Jyotsna Verma
e8debd87f4 Add constant extender support for MInst type instructions.
llvm-svn: 173813
2013-01-29 18:18:50 +00:00
Evan Cheng
2e2cde560f Teach SDISel to combine fsin / fcos into a fsincos node if the following
conditions are met:
1. They share the same operand and are in the same BB.
2. Both outputs are used.
3. The target has a native instruction that maps to ISD::FSINCOS node or
   the target provides a sincos library call.

Implemented the generic optimization in sdisel and enabled it for
Mac OSX. Also added an additional optimization for x86_64 Mac OSX by
using an alternative entry point __sincos_stret which returns the two
results in xmm0 / xmm1.

rdar://13087969
PR13204

llvm-svn: 173755
2013-01-29 02:32:37 +00:00
Andrew Trick
d1ee804aa3 MIsched: Improve the interface to SchedDFS analysis (subtrees).
Allow the strategy to select SchedDFS. Allow the results of SchedDFS
to affect initialization of the scheduler state.

llvm-svn: 173425
2013-01-25 06:33:57 +00:00
Jyotsna Verma
01c6fabba6 Add indexed load/store instructions for offset validation check.
This patch fixes bug 14902 - http://llvm.org/bugs/show_bug.cgi?id=14902

llvm-svn: 172737
2013-01-17 18:42:37 +00:00
Dmitri Gribenko
fa2aa38684 Improve r172468: const_cast is not needed here
llvm-svn: 172483
2013-01-14 22:18:18 +00:00
David Greene
1365ed4c63 Fix Another Cast
Properly cast code to eliminate cast-away-const errors.

llvm-svn: 172468
2013-01-14 21:04:42 +00:00
Craig Topper
8451536658 Remove more unnecessary # operators with nothing to paste proceeding them.
llvm-svn: 171702
2013-01-07 06:14:20 +00:00
Craig Topper
d8d638d017 Remove # from the beginning and end of def names. The # is a paste operator and should only be used with something to paste on either side.
llvm-svn: 171697
2013-01-07 05:45:56 +00:00
Chandler Carruth
30bd563e01 Switch TargetTransformInfo from an immutable analysis pass that requires
a TargetMachine to construct (and thus isn't always available), to an
analysis group that supports layered implementations much like
AliasAnalysis does. This is a pretty massive change, with a few parts
that I was unable to easily separate (sorry), so I'll walk through it.

The first step of this conversion was to make TargetTransformInfo an
analysis group, and to sink the nonce implementations in
ScalarTargetTransformInfo and VectorTargetTranformInfo into
a NoTargetTransformInfo pass. This allows other passes to add a hard
requirement on TTI, and assume they will always get at least on
implementation.

The TargetTransformInfo analysis group leverages the delegation chaining
trick that AliasAnalysis uses, where the base class for the analysis
group delegates to the previous analysis *pass*, allowing all but tho
NoFoo analysis passes to only implement the parts of the interfaces they
support. It also introduces a new trick where each pass in the group
retains a pointer to the top-most pass that has been initialized. This
allows passes to implement one API in terms of another API and benefit
when some other pass above them in the stack has more precise results
for the second API.

The second step of this conversion is to create a pass that implements
the TargetTransformInfo analysis using the target-independent
abstractions in the code generator. This replaces the
ScalarTargetTransformImpl and VectorTargetTransformImpl classes in
lib/Target with a single pass in lib/CodeGen called
BasicTargetTransformInfo. This class actually provides most of the TTI
functionality, basing it upon the TargetLowering abstraction and other
information in the target independent code generator.

The third step of the conversion adds support to all TargetMachines to
register custom analysis passes. This allows building those passes with
access to TargetLowering or other target-specific classes, and it also
allows each target to customize the set of analysis passes desired in
the pass manager. The baseline LLVMTargetMachine implements this
interface to add the BasicTTI pass to the pass manager, and all of the
tools that want to support target-aware TTI passes call this routine on
whatever target machine they end up with to add the appropriate passes.

The fourth step of the conversion created target-specific TTI analysis
passes for the X86 and ARM backends. These passes contain the custom
logic that was previously in their extensions of the
ScalarTargetTransformInfo and VectorTargetTransformInfo interfaces.
I separated them into their own file, as now all of the interface bits
are private and they just expose a function to create the pass itself.
Then I extended these target machines to set up a custom set of analysis
passes, first adding BasicTTI as a fallback, and then adding their
customized TTI implementations.

The fourth step required logic that was shared between the target
independent layer and the specific targets to move to a different
interface, as they no longer derive from each other. As a consequence,
a helper functions were added to TargetLowering representing the common
logic needed both in the target implementation and the codegen
implementation of the TTI pass. While technically this is the only
change that could have been committed separately, it would have been
a nightmare to extract.

The final step of the conversion was just to delete all the old
boilerplate. This got rid of the ScalarTargetTransformInfo and
VectorTargetTransformInfo classes, all of the support in all of the
targets for producing instances of them, and all of the support in the
tools for manually constructing a pass based around them.

Now that TTI is a relatively normal analysis group, two things become
straightforward. First, we can sink it into lib/Analysis which is a more
natural layer for it to live. Second, clients of this interface can
depend on it *always* being available which will simplify their code and
behavior. These (and other) simplifications will follow in subsequent
commits, this one is clearly big enough.

Finally, I'm very aware that much of the comments and documentation
needs to be updated. As soon as I had this working, and plausibly well
commented, I wanted to get it committed and in front of the build bots.
I'll be doing a few passes over documentation later if it sticks.

Commits to update DragonEgg and Clang will be made presently.

llvm-svn: 171681
2013-01-07 01:37:14 +00:00
Chandler Carruth
4c1f3c24db Move all of the header files which are involved in modelling the LLVM IR
into their new header subdirectory: include/llvm/IR. This matches the
directory structure of lib, and begins to correct a long standing point
of file layout clutter in LLVM.

There are still more header files to move here, but I wanted to handle
them in separate commits to make tracking what files make sense at each
layer easier.

The only really questionable files here are the target intrinsic
tablegen files. But that's a battle I'd rather not fight today.

I've updated both CMake and Makefile build systems (I think, and my
tests think, but I may have missed something).

I've also re-sorted the includes throughout the project. I'll be
committing updates to Clang, DragonEgg, and Polly momentarily.

llvm-svn: 171366
2013-01-02 11:36:10 +00:00
Bill Wendling
35bce31a2e Remove Function::getParamAttributes and use the AttributeSet accessor methods instead.
llvm-svn: 171255
2012-12-30 12:45:13 +00:00
Jakub Staszak
3588dcff13 Delete executive bit on ./lib/Target/Hexagon/HexagonAsmPrinter.h.
llvm-svn: 171225
2012-12-29 15:23:06 +00:00
Jyotsna Verma
d2eb3f84fd Add constant extender support to GP-relative load/store instructions.
llvm-svn: 170672
2012-12-20 06:52:46 +00:00
Jyotsna Verma
cb321ae6c7 Add TSFlags to ALU32 type instructions for constant-extender/Relationship maps.
llvm-svn: 170671
2012-12-20 06:45:39 +00:00
Bill Wendling
56d9c4b832 Rename the 'Attributes' class to 'Attribute'. It's going to represent a single attribute in the future.
llvm-svn: 170502
2012-12-19 07:18:57 +00:00
Jyotsna Verma
7fb1e065a0 Use multiclass for new-value store instructions with MEMri operand.
llvm-svn: 169814
2012-12-11 05:12:25 +00:00
NAKAMURA Takumi
10a9cdfc27 [CMake] Update dependencies to intrinsics_gen corresponding to r169711.
llvm-svn: 169724
2012-12-10 05:27:15 +00:00
Matthew Curtis
596e698b79 In hexagon convertToHardwareLoop, don't deref end() iterator
In particular, check if MachineBasicBlock::iterator is end() before
using it to call getDebugLoc();

See also this thread on llvm-commits:
   http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20121112/155914.html

llvm-svn: 169634
2012-12-07 21:03:15 +00:00
Jyotsna Verma
9995a62d05 Define new-value store instructions with base+immediate addressing mode
using multiclass.

llvm-svn: 169432
2012-12-05 22:02:56 +00:00
Jyotsna Verma
c8d145f6f6 Use multiclass to define store instructions with base+immediate offset
addressing mode and immediate stored value.

llvm-svn: 169408
2012-12-05 19:32:03 +00:00
Matthew Curtis
67b48517cb Fix misplaced closing brace.
llvm-svn: 169404
2012-12-05 19:00:34 +00:00
Jyotsna Verma
52d66f1d1e Define store instructions with base+register offset addressing mode
using multiclass.

llvm-svn: 169314
2012-12-04 21:58:25 +00:00
Jyotsna Verma
ec3f676ca1 Add patterns to define 'combine', 'tstbit', 'ct0/cl0' (count trailing/leading zeros)
instructions.

llvm-svn: 169287
2012-12-04 18:05:01 +00:00
Jyotsna Verma
0dd9064b5a Add constant extender support to ALU32 instructions for V2.
llvm-svn: 169284
2012-12-04 17:12:00 +00:00
Chandler Carruth
a98c778194 Sort includes for all of the .h files under the 'lib' tree. These were
missed in the first pass because the script didn't yet handle include
guards.

Note that the script is now able to handle all of these headers without
manual edits. =]

llvm-svn: 169224
2012-12-04 07:12:27 +00:00
Jyotsna Verma
2878599f9d Move all operand definitions into HexagonOperands.td
llvm-svn: 169213
2012-12-04 05:00:31 +00:00
Jyotsna Verma
5743b854a0 Move generic Hexagon subtarget information into Hexagon.td
llvm-svn: 169212
2012-12-04 04:29:16 +00:00
Jyotsna Verma
e17db34a1c Define store instructions with base+immediate offset addressing mode
using multiclass.

llvm-svn: 169168
2012-12-03 22:26:28 +00:00
Jyotsna Verma
3bea2435da Define load instructions with base+immediate offset addressing mode
using multiclass.

llvm-svn: 169153
2012-12-03 21:13:13 +00:00
Jyotsna Verma
a762d2c7c0 Define unsigned const-ext predicates.
llvm-svn: 169149
2012-12-03 20:39:45 +00:00
Jyotsna Verma
c9aa3a1e1b Removing unnecessary 'else' statement from the predicates defined in HexagonOperards.td.
llvm-svn: 169148
2012-12-03 20:14:38 +00:00
Chandler Carruth
a490793037 Use the new script to sort the includes of every file under lib.
Sooooo many of these had incorrect or strange main module includes.
I have manually inspected all of these, and fixed the main module
include to be the nearest plausible thing I could find. If you own or
care about any of these source files, I encourage you to take some time
and check that these edits were sensible. I can't have broken anything
(I strictly added headers, and reordered them, never removed), but they
may not be the headers you'd really like to identify as containing the
API being implemented.

Many forward declarations and missing includes were added to a header
files to allow them to parse cleanly when included first. The main
module rule does in fact have its merits. =]

llvm-svn: 169131
2012-12-03 16:50:05 +00:00
Jyotsna Verma
deb06efce6 Define signed const-ext predicates.
llvm-svn: 169117
2012-12-03 06:54:50 +00:00
Jyotsna Verma
7b9aa748cb Use multiclass for the load instructions with MEMri operand.
llvm-svn: 169018
2012-11-30 17:31:52 +00:00
Jyotsna Verma
9baa0ebf94 Use multiclass for the store instructions with MEMri operand.
llvm-svn: 168983
2012-11-30 06:10:22 +00:00
Jyotsna Verma
9ec526d755 Use multiclass for the load instructions with 'base + register offset'
addressing mode.

llvm-svn: 168976
2012-11-30 04:19:09 +00:00
Jyotsna Verma
7806a44024 Use multiclass for 'transfer' instructions.
llvm-svn: 168929
2012-11-29 19:35:44 +00:00
Jyotsna Verma
f5ca442d79 Define signed const-ext immediate operands and their predicates.
llvm-svn: 168810
2012-11-28 20:58:14 +00:00
Jyotsna Verma
cac9f4bdf8 Fix comments in HexagonOperands.td.
llvm-svn: 168617
2012-11-26 21:56:51 +00:00
Jyotsna Verma
57c7894ac6 Add new predicates for the immediate operands.
llvm-svn: 168451
2012-11-21 20:05:09 +00:00