Dan Gohman
c860d9c77c
Add AsmPrinter support for emitting a directive to declare that
...
the code being generated does not require an executable stack.
Also, add target-specific code to make use of this on Linux
on x86.
llvm-svn: 50634
2008-05-05 00:28:39 +00:00
Anton Korobeynikov
04c974b1b2
Add General Dynamic TLS model for X86-64. Some parts looks really ugly (look for tlsaddr pattern),
...
but should work. Work is in progress, more models will follow
llvm-svn: 50630
2008-05-04 21:36:32 +00:00
Evan Cheng
a7747df955
Select vector shift with non-immediate i32 shift amount operand by first moving the operand into the right register.
...
llvm-svn: 50619
2008-05-04 09:15:50 +00:00
Evan Cheng
c1c2adbfc6
Add separate intrinsics for MMX / SSE shifts with i32 integer operands. This allow us to simplify the horribly complicated matching code.
...
llvm-svn: 50601
2008-05-03 00:52:09 +00:00
Evan Cheng
90b9027f68
Undo r50574. We are already ensuring the folded load address is 16-byte aligned.
...
llvm-svn: 50578
2008-05-02 17:01:01 +00:00
Evan Cheng
583a346ec6
80 column violation.
...
llvm-svn: 50575
2008-05-02 07:53:32 +00:00
Evan Cheng
862e3a147c
Not safe folding a load + FsXORPSrr into FsXORPSrm. It's loading a FR64 value but the load folding variant expects a 16-byte aligned address.
...
llvm-svn: 50574
2008-05-02 07:50:58 +00:00
Arnold Schwaighofer
f58a35e2ec
Tail call optimization improvements:
...
Move platform independent code (lowering of possibly overwritten
arguments, check for tail call optimization eligibility) from
target X86ISelectionLowering.cpp to TargetLowering.h and
SelectionDAGISel.cpp.
Initial PowerPC tail call implementation:
Support ppc32 implemented and tested (passes my tests and
test-suite llvm-test).
Support ppc64 implemented and half tested (passes my tests).
On ppc tail call optimization is performed if
caller and callee are fastcc
call is a tail call (in tail call position, call followed by ret)
no variable argument lists or byval arguments
option -tailcallopt is enabled
Supported:
* non pic tail calls on linux/darwin
* module-local tail calls on linux(PIC/GOT)/darwin(PIC)
* inter-module tail calls on darwin(PIC)
If constraints are not met a normal call will be emitted.
A test checking the argument lowering behaviour on x86-64 was added.
llvm-svn: 50477
2008-04-30 09:16:33 +00:00
Scott Michel
9dec950785
Bug fixes and updates for CellSPU, syncing up with trunk. Most notable
...
fixes are target-specific lowering of frame indices, fix constants generated
for the FSMBI instruction, and fixing SPUTargetLowering::computeMaskedBitsFor-
TargetNode().
llvm-svn: 50462
2008-04-30 00:30:08 +00:00
Anton Korobeynikov
2dca0c7323
Don't do stupid things: doInitialization(Module&) is not applicable to ModulePass :)
...
llvm-svn: 50433
2008-04-29 18:16:22 +00:00
Dan Gohman
0285c1e9bb
Fix the SVOffset values for loads and stores produced by
...
memcpy/memset expansion. It was a bug for the SVOffset value
to be used in the actual address calculations.
llvm-svn: 50359
2008-04-28 17:15:20 +00:00
Anton Korobeynikov
54791c2a43
Fix FP return for Win64 ABI
...
llvm-svn: 50342
2008-04-28 07:40:07 +00:00
Anton Korobeynikov
1c5d228377
Properly lower vararg's FORMAL_ARGUMENTS node on win64
...
llvm-svn: 50325
2008-04-27 23:15:03 +00:00
Anton Korobeynikov
0df1f3bc6c
Handle fp80 for win64
...
llvm-svn: 50324
2008-04-27 22:54:09 +00:00
Chris Lattner
b5bd654163
A few inline asm cleanups:
...
- Make targetlowering.h fit in 80 cols.
- Make LowerAsmOperandForConstraint const.
- Make lowerXConstraint -> LowerXConstraint
- Make LowerXConstraint return a const char* instead of taking a string byref.
llvm-svn: 50312
2008-04-26 23:02:14 +00:00
Chris Lattner
1c98ff80c0
no need to implement this method and just have it call
...
the default impl.
llvm-svn: 50311
2008-04-26 22:59:59 +00:00
Evan Cheng
318e7e042c
Extract the lower 64-bit if a MMX value is passed in a XMM register.
...
llvm-svn: 50292
2008-04-25 20:13:28 +00:00
Evan Cheng
eaaec15b4f
Fix illegal MMX_MOVDQ2Qrr pattern. vector_extract result must be a scalar value.
...
llvm-svn: 50291
2008-04-25 20:12:46 +00:00
Evan Cheng
11f101a800
Special handling for MMX values being passed in either GPR64 or lower 64-bits of XMM registers.
...
llvm-svn: 50289
2008-04-25 19:11:04 +00:00
Evan Cheng
0fe99f024d
Fix MMX_MOVQ2DQrr pattern. It's illegal to do a bitconvert from a smaller type to a larger one.
...
llvm-svn: 50278
2008-04-25 18:19:54 +00:00
Chris Lattner
81742d7a8f
add a note
...
llvm-svn: 50267
2008-04-25 17:25:00 +00:00
Evan Cheng
bbbe14502f
80 col violation.
...
llvm-svn: 50266
2008-04-25 17:21:40 +00:00
Evan Cheng
37ca5de3b7
Not checking for intrinsics which do not have a chain operand.
...
llvm-svn: 50260
2008-04-25 08:55:28 +00:00
Evan Cheng
e177dc6696
- Switch from std::set to SmallPtrSet.
...
- Add comments.
llvm-svn: 50259
2008-04-25 08:22:20 +00:00
Evan Cheng
39ae78cadb
MMX argument passing fixes:
...
On Darwin / Linux x86-32, v8i8, v4i16, v2i32 values are passed in MM[0-2].
On Darwin / Linux x86-32, v1i64 values are passed in memory.
On Darwin x86-64, v8i8, v4i16, v2i32 values are passed in XMM[0-7].
On Darwin x86-64, v1i64 values are passed in 64-bit GPRs.
llvm-svn: 50257
2008-04-25 07:56:45 +00:00
Chris Lattner
8c9f6c929a
Loosen up an assertion to allow intrinsics. I really have no
...
idea what this code (findNonImmUse) does, so I'm only guessing
that this is the right thing. It would be really really nice
if this had comments and perhaps switched to SmallPtrSet
(hint hint) :)
This fixes rdar://5886601, a crash on gcc.target/i386/sse4_1-pblendw.c
llvm-svn: 50252
2008-04-25 05:13:01 +00:00
Evan Cheng
484060ba4a
Fix bug in x86 memcpy / memset lowering. If there are trailing bytes not handled by rep instructions, a new memcpy / memset is introduced for them. However, since source / destination addresses are already adjusted, their offsets should be zero.
...
llvm-svn: 50239
2008-04-25 00:26:43 +00:00
Dan Gohman
6054efc488
Make these variables static.
...
llvm-svn: 50196
2008-04-23 23:15:23 +00:00
Anton Korobeynikov
ac6f6045bb
Drop dead includes
...
llvm-svn: 50192
2008-04-23 22:44:03 +00:00
Anton Korobeynikov
361e5f9eee
Adjust option names for C++ backend
...
llvm-svn: 50190
2008-04-23 22:37:03 +00:00
Anton Korobeynikov
193b7db7c7
First step of implementing PR1538: move llvm2cpp logic to new 'target'
...
llvm-svn: 50189
2008-04-23 22:29:24 +00:00
Dan Gohman
5df2f2c2e7
Initial CBE support for multiple return values.
...
llvm-svn: 50187
2008-04-23 21:49:29 +00:00
Anton Korobeynikov
4b572e0f73
Fix typo
...
llvm-svn: 50169
2008-04-23 18:24:25 +00:00
Anton Korobeynikov
372e69e652
Only allow increase of max alignment value
...
llvm-svn: 50168
2008-04-23 18:23:50 +00:00
Anton Korobeynikov
47a8e6d7a9
Be over-conservative: scan for all used virtual registers and calculate maximal stack alignment in assumption, that there will be spill of vector register.
...
llvm-svn: 50167
2008-04-23 18:23:30 +00:00
Anton Korobeynikov
e7754f758b
Add X86 Maximal Stack Alignment Calculator Pass before RA
...
llvm-svn: 50166
2008-04-23 18:23:05 +00:00
Anton Korobeynikov
158f614c67
Do proper book-keeping of offsets and prologue/epilogue code for stack realignment
...
llvm-svn: 50163
2008-04-23 18:21:27 +00:00
Anton Korobeynikov
1f07315f47
If stack realignment is used - incoming args will use EBP as base register and locals - ESP
...
llvm-svn: 50162
2008-04-23 18:21:02 +00:00
Anton Korobeynikov
5079553b9d
Eastimate required stack alignment early, so we can decide, whether we will need frame pointer or not
...
llvm-svn: 50161
2008-04-23 18:20:17 +00:00
Anton Korobeynikov
492641d67f
Cleanup
...
llvm-svn: 50159
2008-04-23 18:19:23 +00:00
Anton Korobeynikov
87325bfdf5
Simplify
...
llvm-svn: 50158
2008-04-23 18:18:36 +00:00
Anton Korobeynikov
73935826d4
Make stack alignment options global for all targets
...
llvm-svn: 50157
2008-04-23 18:18:10 +00:00
Anton Korobeynikov
6a59c959ca
Provide option for enabling-disabling stack realignment
...
llvm-svn: 50156
2008-04-23 18:17:11 +00:00
Anton Korobeynikov
fc59ae78e0
Disable stack realignment for functions with dynamic-sized alloca's
...
llvm-svn: 50155
2008-04-23 18:16:43 +00:00
Anton Korobeynikov
11851230a9
Provide ABI-correct stack alignment
...
llvm-svn: 50154
2008-04-23 18:16:16 +00:00
Anton Korobeynikov
7e6850d1a1
Provide convenient helpers for some operations
...
llvm-svn: 50153
2008-04-23 18:15:48 +00:00
Anton Korobeynikov
71adb49389
Whitespace cleanup
...
llvm-svn: 50152
2008-04-23 18:15:11 +00:00
Dan Gohman
93b5be1824
Implement an x86-64 ABI detail of passing structs by hidden first
...
argument. The x86-64 ABI requires the incoming value of %rdi to
be copied to %rax on exit from a function that is returning a
large C struct.
Also, add a README-X86-64 entry detailing the missed optimization
opportunity and proposing an alternative approach.
llvm-svn: 50075
2008-04-21 23:59:07 +00:00
Dan Gohman
105b523786
Fix the encoding of the MMX movd that moves from MMX to 64-bit GPR.
...
llvm-svn: 50053
2008-04-21 19:52:29 +00:00
Chris Lattner
3117d33f74
Add an ugly note.
...
llvm-svn: 50029
2008-04-21 04:46:30 +00:00
Nicolas Geoffray
036fb2bebf
Don't forget to update the current operand when getting the size of an instruction.
...
llvm-svn: 50007
2008-04-20 23:36:47 +00:00
Chris Lattner
2c5b96fbee
A better fix for my previous patch, MOVZQI2PQIrr just requires SSE2.
...
llvm-svn: 49986
2008-04-20 05:52:46 +00:00
Chris Lattner
f390d62b7f
Switch to using Simplified ConstantFP::get API.
...
llvm-svn: 49977
2008-04-20 00:41:09 +00:00
Evan Cheng
f583b3feb6
64-bit atomic operations.
...
llvm-svn: 49949
2008-04-19 02:30:38 +00:00
Evan Cheng
1c54ebbe2f
Also LXCHG64 -> XCHG64rm.
...
llvm-svn: 49948
2008-04-19 02:05:42 +00:00
Evan Cheng
09e77f6b83
PPC32 atomic operations.
...
llvm-svn: 49947
2008-04-19 01:30:48 +00:00
Evan Cheng
b1d240f973
xchg which references a memory operand does not need to lock prefix. Atomicity is guaranteed.
...
llvm-svn: 49946
2008-04-19 01:20:30 +00:00
Dan Gohman
98ca33cb59
Fix the handling of va_copy on x86-64. As of llvm-gcc r49920
...
llvm-gcc is now lowering va_copy on x86-64, so this completes
the fix for PR2230.
llvm-svn: 49922
2008-04-18 20:55:41 +00:00
Evan Cheng
a626e13995
- Fix atomic operation JIT encoding.
...
- Remove unused instructions.
llvm-svn: 49921
2008-04-18 20:55:36 +00:00
Evan Cheng
2b03674feb
Also support Intel asm syntax.
...
llvm-svn: 49878
2008-04-17 23:35:10 +00:00
Evan Cheng
0b36ca5023
Fix assembly code for atomic operations.
...
llvm-svn: 49869
2008-04-17 21:26:35 +00:00
Evan Cheng
e2e899b5c2
Don't forget about sub-register indices when rematting instructions.
...
llvm-svn: 49830
2008-04-16 23:44:44 +00:00
Dale Johannesen
d19ab27ee1
Unbreak build on x86-64.
...
llvm-svn: 49822
2008-04-16 22:24:33 +00:00
Nicolas Geoffray
1f3211af01
Correlate stubs with functions in JIT: when emitting a stub, the JIT tells the memory manager which function
...
the stub will resolve.
llvm-svn: 49814
2008-04-16 20:46:05 +00:00
Nicolas Geoffray
82baa2d2c6
Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented
...
llvm-svn: 49809
2008-04-16 20:10:13 +00:00
Evan Cheng
341bed7210
Initialize X863DNowLevel.
...
llvm-svn: 49808
2008-04-16 19:03:02 +00:00
Roman Levenstein
728d59166f
Ongoing work on improving the instruction selection infrastructure:
...
Rename SDOperandImpl back to SDOperand.
Introduce the SDUse class that represents a use of the SDNode referred by
an SDOperand. Now it is more similar to Use/Value classes.
Patch is approved by Dan Gohman.
llvm-svn: 49795
2008-04-16 16:15:27 +00:00
Dan Gohman
be8f2b452b
Add support for the form of the SSE41 extractps instruction that
...
puts its result in a 32-bit GPR.
llvm-svn: 49762
2008-04-16 02:32:24 +00:00
Dan Gohman
cf79877623
Recreate the size SDNode instead of reusing the old one in the x86
...
memcpy lowering code; this ensures that the size node has the desired
result type. This fixes a regression from r49572 with @llvm.memcpy.i64
on x86-32.
llvm-svn: 49761
2008-04-16 01:32:32 +00:00
Dan Gohman
6f9b55bc7c
Remove X86_64SRet; it isn't used anymore.
...
llvm-svn: 49759
2008-04-16 00:24:30 +00:00
Dan Gohman
7d27552962
Add movd instructions to move from MMX registers
...
to 64-bit GPR registers on x86-64.
llvm-svn: 49757
2008-04-15 23:55:07 +00:00
Nicolas Geoffray
7e0110f724
Change Divided flag to Split, as suggested by Evan
...
llvm-svn: 49715
2008-04-15 08:08:50 +00:00
Dan Gohman
77049e31b6
Remove unnecessary <sstream> includes.
...
llvm-svn: 49681
2008-04-14 20:40:47 +00:00
Dan Gohman
8d46278998
Fix const-correctness issues with the SrcValue handling in the
...
memory intrinsic expansion code.
llvm-svn: 49666
2008-04-14 17:55:48 +00:00
Dale Johannesen
edcba1161f
Reverse sense of unwind-tables option. This means
...
stack tracebacks on Darwin x86-64 won't work by default;
nevertheless, everybody but me thinks this is a good idea.
llvm-svn: 49663
2008-04-14 17:54:17 +00:00
Nicolas Geoffray
ad5556e8ba
Add a divided flag for the first piece of an argument divided into mulitple parts. Fixes PR1643
...
llvm-svn: 49611
2008-04-13 13:40:22 +00:00
Anton Korobeynikov
ea8dbf596a
Provide option for stack alignment override
...
llvm-svn: 49593
2008-04-12 22:12:22 +00:00
Arnold Schwaighofer
82af0e6a43
This patch corrects the handling of byval arguments for tailcall
...
optimized x86-64 (and x86) calls so that they work (... at least for
my test cases).
Should fix the following problems:
Problem 1: When i introduced the optimized handling of arguments for
tail called functions (using a sequence of copyto/copyfrom virtual
registers instead of always lowering to top of the stack) i did not
handle byval arguments correctly e.g they did not work at all :).
Problem 2: On x86-64 after the arguments of the tail called function
are moved to their registers (which include ESI/RSI etc), tail call
optimization performs byval lowering which causes xSI,xDI, xCX
registers to be overwritten. This is handled in this patch by moving
the arguments to virtual registers first and after the byval lowering
the arguments are moved from those virtual registers back to
RSI/RDI/RCX.
llvm-svn: 49584
2008-04-12 18:11:06 +00:00
Dan Gohman
15edbf989f
Drop ISD::MEMSET, ISD::MEMMOVE, and ISD::MEMCPY, which are not Legal
...
on any current target and aren't optimized in DAGCombiner. Instead
of using intermediate nodes, expand the operations, choosing between
simple loads/stores, target-specific code, and library calls,
immediately.
Previously, the code to emit optimized code for these operations
was only used at initial SelectionDAG construction time; now it is
used at all times. This fixes some cases where rep;movs was being
used for small copies where simple loads/stores would be better.
This also cleans up code that checks for alignments less than 4;
let the targets make that decision instead of doing it in
target-independent code. This allows x86 to use rep;movs in
low-alignment cases.
Also, this fixes a bug that resulted in the use of rep;stos for
memsets of 0 with non-constant memory size when the alignment was
at least 4. It's better to use the library in this case, which
can be significantly faster when the size is large.
This also preserves more SourceValue information when memory
intrinsics are lowered into simple loads/stores.
llvm-svn: 49572
2008-04-12 04:36:06 +00:00
Dan Gohman
41f9d24d52
Fix a bug that prevented x86-64 from using rep.movsq for
...
8-byte-aligned data.
llvm-svn: 49571
2008-04-12 02:35:39 +00:00
Nate Begeman
81586b24d6
80 col fix
...
llvm-svn: 49569
2008-04-12 00:47:57 +00:00
Chris Lattner
9f994482f5
add a note, this is actually not too bad to implement.
...
llvm-svn: 49466
2008-04-10 05:54:50 +00:00
Chris Lattner
869325c4c4
move the x86-32 part of PR2108 here.
...
llvm-svn: 49465
2008-04-10 05:37:47 +00:00
Chris Lattner
3b289289a7
Fix the x86-64 side of PR2108 by adding a v2f64 version of
...
MOVZQI2PQIrr. This would be better handled as a dag combine
(with the goal of eliminating the bitconvert) but I don't know
how to do that safely. Thoughts welcome.
llvm-svn: 49463
2008-04-10 05:13:43 +00:00
Dan Gohman
b3a511b236
Make isVectorClearMaskLegal's operand list const.
...
llvm-svn: 49446
2008-04-09 20:09:42 +00:00
Dan Gohman
f4cd5a4801
Add XMM1 as a second return value register for f32 and f64 on x86-64. This
...
is needed for the x86-64-ABI handling of structs that contain floating-point
members that are returned by value.
llvm-svn: 49441
2008-04-09 17:54:37 +00:00
Dan Gohman
9f7c4f6e16
Add DX as a second return value register for i16 on x86.
...
llvm-svn: 49440
2008-04-09 17:53:38 +00:00
Dale Johannesen
5dcdb08b0d
Rename -disable-required-unwind-tables to unwind-tables-optional.
...
llvm-svn: 49389
2008-04-08 18:07:49 +00:00
Dale Johannesen
2d29b1c5bb
Handle the situation in 2008-01-25-EmptyFunction.ll
...
correctly when unwind info is being generated.
llvm-svn: 49366
2008-04-08 00:37:56 +00:00
Dale Johannesen
ec0fe04044
Implement new llc flag -disable-required-unwind-tables.
...
Corresponds to -fno-unwind-tables (usually default in gcc).
llvm-svn: 49361
2008-04-08 00:10:24 +00:00
Dan Gohman
d7301ea935
Rename MemOperand to MachineMemOperand. This was suggested by
...
review feedback from Chris quite a while ago. No functionality
change.
llvm-svn: 49348
2008-04-07 19:35:22 +00:00
Roman Levenstein
b40d332929
Re-commit of the r48822, where the infinite looping problem discovered
...
by Dan Gohman is fixed.
llvm-svn: 49330
2008-04-07 10:06:32 +00:00
Gabor Greif
6c6b8a57f3
API changes for class Use size reduction, wave 1.
...
Specifically, introduction of XXX::Create methods
for Users that have a potentially variable number of
Uses.
llvm-svn: 49277
2008-04-06 20:25:17 +00:00
Evan Cheng
4d7b2ab16f
Favors pshufd over shufps when shuffling elements from one vector. pshufd is faster than shufps.
...
llvm-svn: 49244
2008-04-05 00:30:36 +00:00
Torok Edwin
a282b19804
strdup needs <cstring>. This fixes a build error with g++-4.3.
...
llvm-svn: 49218
2008-04-04 16:08:00 +00:00
Evan Cheng
0585b4bc2a
Re-enable SSE4.
...
llvm-svn: 49158
2008-04-03 08:53:29 +00:00
Evan Cheng
cb5a5467dc
Fix x86-64 encoding bug. REX prefix must always follow 0x0F prefix. For example, extractps in 64bit mode: 66 REX 0F 3A 17, not 66 0F 3A REX 17.
...
llvm-svn: 49157
2008-04-03 08:53:17 +00:00
Evan Cheng
12d2bbde0d
Cosmetic
...
llvm-svn: 49156
2008-04-03 07:45:18 +00:00
Evan Cheng
f112eb3b1c
Temporarily disabling SSE4 until we fix the encoding issues.
...
llvm-svn: 49129
2008-04-03 04:49:54 +00:00
Evan Cheng
497c607fae
Backing out 48222 temporarily.
...
llvm-svn: 49124
2008-04-03 03:13:16 +00:00
Dan Gohman
5b2503097e
Suppress the 128-bit integer typedef on 32-bit targets, because
...
it causes compile errors.
llvm-svn: 49122
2008-04-02 23:52:49 +00:00
Dan Gohman
4949a9c308
Partial CBackend support for 128-bit integers. This is needed
...
now that llvm-gcc is lowering appropriately-sized struct returns
to i128 on x86-64.
llvm-svn: 49109
2008-04-02 19:40:14 +00:00
Dale Johannesen
84a1314ea1
Cosmetic changes per EH patch review feedback.
...
llvm-svn: 49096
2008-04-02 17:04:45 +00:00
Anton Korobeynikov
d3330dfbf6
Add new CC lowering rule: provide a list of registers, which can be 'shadowed',
...
when some another register is used for argument passing.
Currently is used on Win64.
llvm-svn: 49079
2008-04-02 05:23:57 +00:00
Dale Johannesen
79633a914f
Recommitting EH patch; this should answer most of the
...
review feedback.
-enable-eh is still accepted but doesn't do anything.
EH intrinsics use Dwarf EH if the target supports that,
and are handled by LowerInvoke otherwise.
The separation of the EH table and frame move data is,
I think, logically figured out, but either one still
causes full EH info to be generated (not sure how to
split the metadata correctly).
MachineModuleInfo::needsFrameInfo is no longer used and
is removed.
llvm-svn: 49064
2008-04-02 00:25:04 +00:00
Evan Cheng
e1eee9570f
ReMat of load from stub in pic mode extends the life of pic base. Currently spiller doesn't do a good job of estimating the impact. Disable for now.
...
llvm-svn: 49059
2008-04-01 23:26:12 +00:00
Evan Cheng
5c98bdbc4f
Remove unnecessary and non-deterministic checking code. Re-enable remat of load from gv stub.
...
llvm-svn: 49054
2008-04-01 21:38:20 +00:00
Dan Gohman
a3e01dc1ec
Don't use __bzero for memset if the second argument isn't zero.
...
llvm-svn: 49050
2008-04-01 20:56:18 +00:00
Dan Gohman
168b2b1300
Speculatively micro-optimize memory-zeroing calls on Darwin 10.
...
llvm-svn: 49048
2008-04-01 20:38:36 +00:00
Dale Johannesen
8813206b7f
Revert 49006 for the moment.
...
llvm-svn: 49046
2008-04-01 20:00:57 +00:00
Evan Cheng
d7f2ac9a0a
Disabling remat of load from gv stub (temporarily) again to fix llvmgcc bootstrap miscompare.
...
llvm-svn: 49037
2008-04-01 07:33:13 +00:00
Evan Cheng
a38ae9c502
Unbreak ARM / Thumb soft FP support.
...
llvm-svn: 49012
2008-04-01 01:50:16 +00:00
Dale Johannesen
1336104c02
Accept 'y' constraint (MMX) in inline asm.
...
llvm-svn: 49011
2008-04-01 00:57:48 +00:00
Dale Johannesen
fa4433be71
Emit exception handling info for functions which are
...
not marked nounwind, or for all functions when -enable-eh
is set, provided the target supports Dwarf EH.
llvm-gcc generates nounwind in the right places; other FEs
will need to do so also. Given such a FE, -enable-eh should
no longer be needed.
llvm-svn: 49006
2008-03-31 23:40:23 +00:00
Evan Cheng
a3ce7b4c76
It's not safe to fold a load from GV stub or constantpool into a two-address use.
...
llvm-svn: 49002
2008-03-31 23:19:51 +00:00
Evan Cheng
38a755499d
Move reMaterialize() from TargetRegisterInfo to TargetInstrInfo.
...
llvm-svn: 48995
2008-03-31 20:40:39 +00:00
Evan Cheng
38bfff8a16
Re-apply 48911.
...
llvm-svn: 48977
2008-03-31 07:54:19 +00:00
Nick Lewycky
7d33dc0878
Moved from PR1570.
...
llvm-svn: 48965
2008-03-30 19:07:11 +00:00
Chris Lattner
49e9edd6f6
Fix "Control reaches the end of non-void function" warnings,
...
patch by David Chisnall.
llvm-svn: 48963
2008-03-30 18:22:13 +00:00
Dan Gohman
227e702cae
Fix a tokenfactor node to use the load chain rather than the
...
load value. This fixes PR2177.
llvm-svn: 48932
2008-03-28 23:45:16 +00:00
Evan Cheng
10d0aba260
Backing out 48911 for now. It's breaking stuff.
...
llvm-svn: 48922
2008-03-28 17:49:06 +00:00
Evan Cheng
3b54c5fa08
New entry.
...
llvm-svn: 48912
2008-03-28 07:07:06 +00:00
Evan Cheng
d66e48366f
Load from stub is already re-materializable.
...
llvm-svn: 48911
2008-03-28 06:49:25 +00:00
Evan Cheng
e66720fd57
Code clean up.
...
llvm-svn: 48856
2008-03-27 01:45:11 +00:00
Evan Cheng
aca67f0b29
Allow certain lea instructions to be rematerialized.
...
llvm-svn: 48855
2008-03-27 01:41:09 +00:00
Evan Cheng
1afaf3092f
Remove an unused command line option.
...
llvm-svn: 48854
2008-03-27 01:30:24 +00:00
Roman Levenstein
55b8822511
Use a linked data structure for the uses lists of an SDNode, just like
...
LLVM Value/Use does and MachineRegisterInfo/MachineOperand does.
This allows constant time for all uses list maintenance operations.
The idea was suggested by Chris. Reviewed by Evan and Dan.
Patch is tested and approved by Dan.
On normal use-cases compilation speed is not affected. On very big basic
blocks there are compilation speedups in the range of 15-20% or even better.
llvm-svn: 48822
2008-03-26 12:39:26 +00:00
Evan Cheng
6323ea8467
Fix some SSE4.1 instruction encoding bugs.
...
llvm-svn: 48815
2008-03-26 08:11:49 +00:00
Dale Johannesen
8c1e95810f
Use ## for comment delimiter on darwin x86-32, so
...
llvm's output .s files will go through gcc -std=c99
without triggering preprocesser errors. Approach
suggested by Daveed Vandevoorde.
llvm-svn: 48808
2008-03-25 23:29:30 +00:00
Evan Cheng
6226a78cb1
Smaller function alignment when optimizing for size.
...
llvm-svn: 48805
2008-03-25 22:29:46 +00:00
Evan Cheng
6ee0633a42
Rename option -optimizefor-size to -optimize-size.
...
llvm-svn: 48804
2008-03-25 22:28:39 +00:00
Dan Gohman
2b96ce84aa
Add explicit keywords.
...
llvm-svn: 48801
2008-03-25 22:06:05 +00:00
Dan Gohman
22002efa15
A quick nm audit turned up several fixed tables and objects that were
...
marked read-write. Use const so that they can be allocated in a
read-only segment.
llvm-svn: 48800
2008-03-25 21:45:14 +00:00
Devang Patel
71f3156ea3
Add optimize-for-size knob.
...
llvm-svn: 48793
2008-03-25 21:02:35 +00:00
Dan Gohman
58ad056286
Add CMP32mr and friends to the load-unfolding table. Among
...
other things, this allows the scheduler to unfold a load operand
in the 2008-01-08-SchedulerCrash.ll testcase, so it now successfully
clones the comparison to avoid a pushf+popf.
llvm-svn: 48777
2008-03-25 16:53:19 +00:00
Evan Cheng
3da2a15397
Add \t after .set. Fix by Jay Freeman.
...
llvm-svn: 48753
2008-03-24 23:36:49 +00:00
Bill Wendling
2097b72649
Use the bit size of the operand instead of the hard-coded 32 to generate the
...
mask.
llvm-svn: 48750
2008-03-24 23:16:37 +00:00
Evan Cheng
dbdf48276a
- SSE4.1 extractfps extracts a f32 into a gr32 register. Very useful! Not. Fix the instruction specification and teaches lowering code to use it only when the only use is a store instruction.
...
llvm-svn: 48746
2008-03-24 21:52:23 +00:00
Evan Cheng
14c5714421
Remove duplicated entries.
...
llvm-svn: 48714
2008-03-23 22:56:07 +00:00
Anton Korobeynikov
49574852c1
Minor typo fixes. Also add another FIXME.
...
llvm-svn: 48710
2008-03-23 20:32:06 +00:00
Anton Korobeynikov
7a1df26c95
Add license header
...
llvm-svn: 48707
2008-03-23 14:53:18 +00:00
Anton Korobeynikov
005dbb191c
Add Win64 compilation callback. This allows easy examples to be JITed on Win64!
...
llvm-svn: 48706
2008-03-23 14:44:32 +00:00
Anton Korobeynikov
e07c433652
Provide a JIT selector on win64
...
llvm-svn: 48704
2008-03-23 13:43:47 +00:00
Anton Korobeynikov
8fda34a926
Hack out the PIC mode on Win64 targets. This needs to be investigated later.
...
llvm-svn: 48703
2008-03-23 13:41:18 +00:00
Anton Korobeynikov
7c5f998b22
Code cleanup. Provide generic way of selecting JIT pointer bitwidth regardless
...
of compiler used.
llvm-svn: 48702
2008-03-23 13:40:45 +00:00
Anton Korobeynikov
23d188b49c
Remove old-standing obsolete code.
...
llvm-svn: 48701
2008-03-23 12:32:54 +00:00
Anton Korobeynikov
95f522419c
Honour built-in defines on win64 targets for automatically subtarget recognize.
...
Force stack alignment to 16 bytes on win targets.
llvm-svn: 48695
2008-03-22 21:18:22 +00:00
Anton Korobeynikov
befd472d5e
Recognize "windows" in target triple, not only "win32"
...
llvm-svn: 48694
2008-03-22 21:12:53 +00:00
Anton Korobeynikov
dbde70d7d6
Add information about callee-saved registers on Win64
...
llvm-svn: 48692
2008-03-22 21:04:01 +00:00
Anton Korobeynikov
dad919f561
Add convenient helper for win64 check. Simplify things slightly.
...
llvm-svn: 48691
2008-03-22 20:57:27 +00:00
Anton Korobeynikov
27c8ad4020
Initial support for Win64 calling conventions. Still in early state.
...
llvm-svn: 48690
2008-03-22 20:37:30 +00:00
Anton Korobeynikov
4b85ece1ab
Another comments fixing
...
llvm-svn: 48683
2008-03-22 07:53:40 +00:00
Chris Lattner
308a452c90
Restore this assert now that the livevar bug is fixed.
...
This verifies kill info for "ret" fp operands is right.
llvm-svn: 48656
2008-03-21 20:41:27 +00:00
Duncan Sands
4153fc30c9
Introduce a new node for holding call argument
...
flags. This is needed by the new legalize types
infrastructure which wants to expand the 64 bit
constants previously used to hold the flags on
32 bit machines. There are two functional changes:
(1) in LowerArguments, if a parameter has the zext
attribute set then that is marked in the flags;
before it was being ignored; (2) PPC had some bogus
code for handling two word arguments when using the
ELF 32 ABI, which was hard to convert because of
the bogusness. As suggested by the original author
(Nicolas Geoffray), I've disabled it for the moment.
Tested with "make check" and the Ada ACATS testsuite.
llvm-svn: 48640
2008-03-21 09:14:45 +00:00
Chris Lattner
edfc239ced
remove Evan's "ugly hack" that sorta attempted to get
...
x86-64 return conventions correct, but was never enabled.
We can now do the "right thing" with multiple return values.
llvm-svn: 48635
2008-03-21 06:50:21 +00:00
Chris Lattner
8a4fa95cae
Add support for calls that return two FP values in
...
ST(0)/ST(1).
llvm-svn: 48634
2008-03-21 06:38:26 +00:00
Chris Lattner
933d0d318b
disable a bogus assertion.
...
llvm-svn: 48633
2008-03-21 06:01:05 +00:00
Chris Lattner
260473f983
Enable support for returning two long-double values in ST(0)/ST(1).
...
This allows us to compile fp-stack-2results.ll into:
_test:
fldz
fld1
ret
which returns 1 in ST(0) and 0 in ST(1). This is needed for x86-64
_Complex long double.
llvm-svn: 48632
2008-03-21 05:57:20 +00:00
Evan Cheng
4ae9fee64c
Undo 48570. Correctly match mmx shift instructions with an immediate operand.
...
llvm-svn: 48627
2008-03-21 00:40:09 +00:00
Chris Lattner
f166a78d79
add a note.
...
llvm-svn: 48583
2008-03-20 04:46:13 +00:00
Evan Cheng
8ecb189245
Fix this xform: (sra (shl X, m), result_size) -> (sign_extend (trunc (shl X, result_size - n - m)))
...
llvm-svn: 48578
2008-03-20 02:18:41 +00:00
Chris Lattner
6c4486c5c7
detabify llvm, patch by Mike Stump!
...
llvm-svn: 48577
2008-03-20 01:22:40 +00:00
Scott Michel
e747d20130
Add more patterns to match in the integer comparison test harnesses.
...
Fix bugs encountered, mostly due to range matching for immediates;
the CellSPU's 10-bit immediates are sign extended, covering a
larger range of unsigned values.
llvm-svn: 48575
2008-03-20 00:51:36 +00:00
Evan Cheng
6f729b2820
Add intrinsics to match mmx shift builtin's with immediate operand.
...
llvm-svn: 48569
2008-03-19 23:38:52 +00:00
Devang Patel
5e8cbbea65
PassInfo keep tracks whether a pass is an analysis pass or not.
...
llvm-svn: 48554
2008-03-19 21:56:59 +00:00
Dan Gohman
c9dec33f3f
Add support for multiple return values for the PPC target by
...
converting call result lowering to use the CallingConvLowering
infastructure.
llvm-svn: 48552
2008-03-19 21:39:28 +00:00
Arnold Schwaighofer
19a78545d9
Don't loose incoming argument registers. Fix documentation style.
...
llvm-svn: 48545
2008-03-19 16:39:45 +00:00
Christopher Lamb
958b0494c3
Fix X86's isTruncateFree to not claim that truncate to i1 is free. This fixes Bill's testcase that failed for r48491.
...
llvm-svn: 48542
2008-03-19 08:30:06 +00:00
Bill Wendling
7ae70d6441
On Darwin, GCC issues a ".globl" for something that has a "visibility protected"
...
attribute instead of ".protected".
llvm-svn: 48516
2008-03-18 23:38:12 +00:00
Evan Cheng
5ac87b837e
Fix a x86-64 isel lowering bug that's been around forever. A x86-64 varargs function implicitly reads X86::AL, don't clobber it!
...
llvm-svn: 48515
2008-03-18 23:36:35 +00:00
Dale Johannesen
861708b8bb
Make Complex long long/double/long double work
...
in ppc64 mode.
llvm-svn: 48459
2008-03-17 17:11:08 +00:00
Chris Lattner
c0ac2481af
Check in some #ifdef'd out code switching call argument
...
lowering over to SparcCallingConv.td. We can't make the switch
yet because we can't say to pass f64 registers in 2 x i32 registers
with the td file yet.
llvm-svn: 48449
2008-03-17 06:58:37 +00:00
Chris Lattner
98f1bf9d41
minor cleanups
...
llvm-svn: 48448
2008-03-17 06:57:02 +00:00
Evan Cheng
07643ce604
Unbreak JIT. Ignore TargetInstrInfo::IMPLICIT_DEF.
...
llvm-svn: 48447
2008-03-17 06:56:52 +00:00
Chris Lattner
40ba51c972
remove dead code
...
llvm-svn: 48445
2008-03-17 06:04:10 +00:00
Chris Lattner
fa003f7a57
Switch sparc from using LowerCallTo to using LowerOperation(CALL) like
...
other targets. Use autogenerated calling conv to lower result of
calls.
llvm-svn: 48444
2008-03-17 06:01:07 +00:00
Chris Lattner
3098125c84
Start moving sparc to use SparcCallingConv.td, switching over
...
return lowering first. This fixes a bug where the top and bottom
of i64 values were returned in the wrong registers before.
llvm-svn: 48443
2008-03-17 05:41:48 +00:00
Chris Lattner
5cb886d4d6
split sparc lowering out into SparcISelLowering.{cpp|h} to follow
...
best practices.
llvm-svn: 48442
2008-03-17 03:21:36 +00:00
Chris Lattner
5aef54c950
refactor the LowerOperation code out to individual functions for
...
each lowering, which is 'best practice'.
llvm-svn: 48441
2008-03-17 02:52:07 +00:00
Dale Johannesen
ee1e5be870
Next round of PPC32 ABI changes. Allow for gcc
...
behavior where a callee thinks a param will be
present in memory, even though the ABI doc says
it doesn't have to be. Handle complex long long
and complex double (4 and 8 return regs).
llvm-svn: 48439
2008-03-17 02:13:43 +00:00
Chris Lattner
dc9bf8fda9
various rotate fun.
...
llvm-svn: 48438
2008-03-17 01:47:51 +00:00
Nate Begeman
f9691b8236
Add a couple missing SSE4 instructions
...
llvm-svn: 48430
2008-03-16 21:14:46 +00:00
Gordon Henriksen
04a60ddcd2
C and Objective Caml bindings for the TargetData class.
...
llvm-svn: 48422
2008-03-16 20:08:03 +00:00
Christopher Lamb
b4f4b41048
Make insert_subreg a two-address instruction, vastly simplifying LowerSubregs pass. Add a new TII, subreg_to_reg, which is like insert_subreg except that it takes an immediate implicit value to insert into rather than a register.
...
llvm-svn: 48412
2008-03-16 03:12:01 +00:00
Evan Cheng
9af68f56c5
Remove isImplicitDef TargetInstrDesc flag.
...
llvm-svn: 48381
2008-03-15 00:19:36 +00:00
Evan Cheng
11d2c09adc
Replace all target specific implicit def instructions with a target independent one: TargetInstrInfo::IMPLICIT_DEF.
...
llvm-svn: 48380
2008-03-15 00:03:38 +00:00
Dale Johannesen
6195ace4c0
Implement the real calling convention for ppc32 Altivec:
...
vectors go at the end of the memory area, after all
non-vector parameters.
llvm-svn: 48364
2008-03-14 17:41:26 +00:00
Evan Cheng
877c5ecabd
Fix some 80 col violations.
...
llvm-svn: 48361
2008-03-14 07:46:48 +00:00
Evan Cheng
fc6645a382
Fix a number of encoding bugs. SSE 4.1 instructions MPSADBWrri, PINSRDrr, etc. have 8-bits immediate field (ImmT == Imm8).
...
llvm-svn: 48360
2008-03-14 07:39:27 +00:00
Evan Cheng
6ef1ca4e87
Add debugging stuff.
...
llvm-svn: 48359
2008-03-14 07:13:42 +00:00
Chris Lattner
c60749aa4c
Add an issue that is preventing instcombine from doing a simplification.
...
llvm-svn: 48356
2008-03-14 06:00:19 +00:00
Dan Gohman
6a74c23363
Use SDTNone instead of duplicating it.
...
llvm-svn: 48346
2008-03-13 23:07:40 +00:00
Christopher Lamb
0f1c32eb63
Get rid of a pseudo instruction and replace it with subreg based operation on real instructions, ridding the asm printers of the hack used to do this previously. In the process, update LowerSubregs to be careful about eliminating copies that have side affects.
...
Note: the coalescer will have to be careful about this too, when it starts coalescing insert_subreg nodes.
llvm-svn: 48329
2008-03-13 05:47:01 +00:00
Dale Johannesen
1e54f7c2b6
Do not promote float params to double in varargs
...
calls here. This was done earlier for params in
the varargs part of the params; any float params
that survive to here are in the non-varargs part,
and must not be promoted.
llvm-svn: 48310
2008-03-12 23:40:01 +00:00
Chris Lattner
7925cc72c0
Reimplement the parameter attributes support, phase #1 . hilights:
...
1. There is now a "PAListPtr" class, which is a smart pointer around
the underlying uniqued parameter attribute list object, and manages
its refcount. It is now impossible to mess up the refcount.
2. PAListPtr is now the main interface to the underlying object, and
the underlying object is now completely opaque.
3. Implementation details like SmallVector and FoldingSet are now no
longer part of the interface.
4. You can create a PAListPtr with an arbitrary sequence of
ParamAttrsWithIndex's, no need to make a SmallVector of a specific
size (you can just use an array or scalar or vector if you wish).
5. All the client code that had to check for a null pointer before
dereferencing the pointer is simplified to just access the
PAListPtr directly.
6. The interfaces for adding attrs to a list and removing them is a
bit simpler.
Phase #2 will rename some stuff (e.g. PAListPtr) and do other less
invasive changes.
llvm-svn: 48289
2008-03-12 17:45:29 +00:00
Evan Cheng
df92afe7d3
Clean up my own mess.
...
X86 lowering normalize vector 0 to v4i32. However DAGCombine can fold (sub x, x) -> 0 after legalization. It can create a zero vector of a type that's not expected (e.g. v8i16). We don't want to disable the optimization since leaving a (sub x, x) is really bad. Add isel patterns for other types of vector 0 to ensure correctness. It's highly unlikely to happen other than in bugpoint reduced test cases.
llvm-svn: 48279
2008-03-12 07:02:50 +00:00
Dale Johannesen
19b4c2dfaf
One more bit of Altivec parameter passing.
...
llvm-svn: 48269
2008-03-12 00:49:20 +00:00
Dale Johannesen
460dc31418
Implement Altivec passing to varargs functions on ppc.
...
llvm-svn: 48264
2008-03-12 00:22:17 +00:00
Anton Korobeynikov
55f54ba252
Correctly propagate thread-local flag from aliasee to alias. This fixes PR2137
...
llvm-svn: 48257
2008-03-11 22:38:53 +00:00
Dan Gohman
8e3c88c4e9
Use PassManagerBase instead of FunctionPassManager for functions
...
that merely add passes. This allows them to be used with either
FunctionPassManager or PassManager, or even with a custom new
kind of pass manager.
llvm-svn: 48256
2008-03-11 22:29:46 +00:00
Chris Lattner
fd2c24af72
Implement basic support for the 'f' register class constraint. This basically
...
works, but probably won't if you mix it with 't' or 'u' yet.
llvm-svn: 48243
2008-03-11 19:50:13 +00:00
Chris Lattner
4458eecb7a
coalesce away 80-bit floating point copies.
...
llvm-svn: 48241
2008-03-11 19:30:09 +00:00
Chris Lattner
aa2287714e
convert a massive if statement to a switch.
...
llvm-svn: 48240
2008-03-11 19:28:17 +00:00
Chris Lattner
b3fefb1e5c
start handling the 'f' x87 constraint.
...
llvm-svn: 48239
2008-03-11 19:06:29 +00:00
Christopher Lamb
4d5034cf91
Missed part of recommit.
...
llvm-svn: 48224
2008-03-11 10:27:36 +00:00
Christopher Lamb
74f4d837df
Recommitting parts of r48130. These do not appear to cause the observed failures.
...
llvm-svn: 48223
2008-03-11 10:09:17 +00:00
Evan Cheng
318a01e5fb
If there are multiple register classes that a register belongs to, return the super-class (e.g. on x86, returns GR32, not GR32_).
...
llvm-svn: 48220
2008-03-11 07:54:14 +00:00
Evan Cheng
af1c76846d
When the register allocator runs out of registers, spill a physical register around the def's and use's of the interval being allocated to make it possible for the interval to target a register and spill it right away and restore a register for uses. This likely generates terrible code but is before than aborting.
...
llvm-svn: 48218
2008-03-11 07:19:34 +00:00
Evan Cheng
53213ba056
In 32-bit mode, mark 64-bit GPR's as unallocatable.
...
llvm-svn: 48217
2008-03-11 07:16:00 +00:00
Nick Lewycky
02e4d6f2dd
Fix the build on gcc 4.2.
...
llvm-svn: 48212
2008-03-11 05:56:09 +00:00
Chris Lattner
9826c9365e
Change the model for FP Stack return to use fp operands on the
...
RET instruction instead of using FpSET_ST0_32. This also generalizes
the code to handling returning of multiple FP results.
llvm-svn: 48209
2008-03-11 03:23:40 +00:00
Dan Gohman
85bfbe2293
Generalize ExpandIntToFP to handle the case where the operand is legal
...
and it's the result that requires expansion. This code is a little confusing
because the TargetLoweringInfo tables for [US]INT_TO_FP use the operand type
(the integer type) rather than the result type.
llvm-svn: 48206
2008-03-11 01:59:03 +00:00
Chris Lattner
d1a014af4e
abort with an assert instead of a cerr to get line#
...
llvm-svn: 48199
2008-03-10 23:56:08 +00:00
Scott Michel
599ff689d0
- Style cleanup in IA64ISelLowering.h: add 'virtual' keyword for consistency.
...
- Add test pattern matching in CellSPU's icmp32.ll test harness
- Fix CellSPU fcmp.ll-generated assert.
llvm-svn: 48197
2008-03-10 23:49:09 +00:00
Chris Lattner
f0684bfd16
Don't emit FP_REG_KILL into a block that just returns. Nothing
...
can be live out of the block anyway, so it isn't needed.
llvm-svn: 48192
2008-03-10 23:34:12 +00:00
Dale Johannesen
3278acdaaa
Disable prolog code that aligns the stack when a
...
local object of >16 byte alignment exists. It does not
work and getting it to work is not trivial, as explained
in the comment. This fixes all the remaining ppc32
failures in the struct-layout-1 part of the gcc testsuite.
(gcc does not support this either, and the only way to
get such an object is with __attribute__((aligned)) or
generic vectors; it can't be done in a standard-conforming
program, or with Altivec. So I think disabling it is OK.)
llvm-svn: 48188
2008-03-10 22:59:46 +00:00
Bill Wendling
80bc045af5
Change the "enable/disable" mechanism so that we can enable PPC register
...
scavenging for 32-bit and 64-bit separately.
llvm-svn: 48186
2008-03-10 22:49:16 +00:00
Chris Lattner
d393772580
Eliminate the FP_GET_ST0/FP_SET_ST0 target-specific dag nodes, just lower to
...
copyfromreg/copytoreg instead.
llvm-svn: 48174
2008-03-10 21:08:41 +00:00
Evan Cheng
7d9e5a7680
Default ISD::PREFETCH to expand.
...
llvm-svn: 48169
2008-03-10 19:38:10 +00:00
Evan Cheng
067ecbc341
Revert 48125, 48126, and 48130 for now to unbreak some x86-64 tests.
...
llvm-svn: 48167
2008-03-10 19:31:26 +00:00
Chris Lattner
52be2c645e
fix 80 col violations.
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llvm-svn: 48166
2008-03-10 18:55:53 +00:00
Nicolas Geoffray
a904844534
Stylistic modifications. No functionality changes.
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llvm-svn: 48158
2008-03-10 17:46:45 +00:00
Scott Michel
38f8a1043a
Integer comparison tests for CellSPU.
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llvm-svn: 48152
2008-03-10 16:58:52 +00:00
Scott Michel
bb8e8fca47
Give TargetLowering::getSetCCResultType() a parameter so that ISD::SETCC's
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return ValueType can depend its operands' ValueType.
This is a cosmetic change, no functionality impacted.
llvm-svn: 48145
2008-03-10 15:42:14 +00:00
Nicolas Geoffray
e3381f0f1f
Add description of individual bits in CR. This fix PR1765.
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llvm-svn: 48143
2008-03-10 14:12:10 +00:00
Christopher Lamb
32e5ce3d96
Allow insert_subreg into implicit, target-specific values.
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Change insert/extract subreg instructions to be able to be used in TableGen patterns.
Use the above features to reimplement an x86-64 pseudo instruction as a pattern.
llvm-svn: 48130
2008-03-10 06:12:08 +00:00
Dale Johannesen
e6b0009792
Increase ISD::ParamFlags to 64 bits. Increase the ByValSize
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field to 32 bits, thus enabling correct handling of ByVal
structs bigger than 0x1ffff. Abstract interface a bit.
Fixes gcc.c-torture/execute/pr23135.c and
gcc.c-torture/execute/pr28982b.c in gcc testsuite (were ICE'ing
on ppc32, quietly producing wrong code on x86-32.)
llvm-svn: 48122
2008-03-10 02:17:22 +00:00
Chris Lattner
4a5abdbe3f
Darwin PPC64 indirect call target goes in X12, not R12. This fixes these
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two regression tests:
test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert.ll
test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert2.ll
llvm-svn: 48120
2008-03-09 20:49:33 +00:00
Chris Lattner
23ee644c71
cell really does support cross-regclass moves, because R3 is in lots of different regclasses, and the code is not consistent when it comes to value tracking.
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llvm-svn: 48119
2008-03-09 20:31:11 +00:00
Chris Lattner
9185c43c7d
make sure ar.pfs is in a register class, this fixes test/CodeGen/IA64/ret-0.ll
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llvm-svn: 48118
2008-03-09 20:12:44 +00:00
Chris Lattner
b6bfedbcfd
teach X86InstrInfo::copyRegToReg how to copy into ST(0) from
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an RFP register class.
Teach ScheduleDAG how to handle CopyToReg with different src/dst
reg classes.
This allows us to compile trivial inline asms that expect stuff
on the top of x87-fp stack.
llvm-svn: 48107
2008-03-09 09:15:31 +00:00
Chris Lattner
b29a963cf5
add some code to support cross-register class copying from
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RST -> RFP{32/64/80}. We only handle ST(0) for now.
llvm-svn: 48104
2008-03-09 08:46:19 +00:00
Chris Lattner
53b86390b7
rearrange some code, no functionality change.
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llvm-svn: 48101
2008-03-09 07:58:04 +00:00
Chris Lattner
71189e9501
claim ST(x) registers are 80 bits, which is true. This doesn't affect
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codegen yet because these can't be spilled (they don't exist until after RA).
llvm-svn: 48098
2008-03-09 07:49:01 +00:00
Chris Lattner
2e7537b60b
rename FP_SETRESULT -> FP_SET_ST0
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llvm-svn: 48094
2008-03-09 07:08:44 +00:00
Chris Lattner
826402e365
rename FpGETRESULT32 -> FpGET_ST0_32 etc. Add support for
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isel'ing value preserving FP roundings from one fp stack reg to another
into a noop, instead of stack traffic.
llvm-svn: 48093
2008-03-09 07:05:32 +00:00
Chris Lattner
b628208161
Finish implementing a readme entry: when inserting an i64 variable
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into a vector of zeros or undef, and when the top part is obviously
zero, we can just use movd + shuffle. This allows us to compile
vec_set-B.ll into:
_test3:
movl $1234567, %eax
andl 4(%esp), %eax
movd %eax, %xmm0
ret
instead of:
_test3:
subl $28, %esp
movl $1234567, %eax
andl 32(%esp), %eax
movl %eax, (%esp)
movl $0, 4(%esp)
movq (%esp), %xmm0
addl $28, %esp
ret
llvm-svn: 48090
2008-03-09 05:42:06 +00:00
Chris Lattner
b741ebba29
add a note
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llvm-svn: 48064
2008-03-09 01:08:22 +00:00
Chris Lattner
17f68a3075
Implement a readme entry, compiling
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#include <xmmintrin.h>
__m128i doload64(short x) {return _mm_set_epi16(0,0,0,0,0,0,0,1);}
into:
movl $1, %eax
movd %eax, %xmm0
ret
instead of a constant pool load.
llvm-svn: 48063
2008-03-09 01:05:04 +00:00
Chris Lattner
81deb3bc9c
1) Improve comments.
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2) Don't try to insert an i64 value into the low part of a
vector with movq on an x86-32 target. This allows us to
compile:
__m128i doload64(short x) {return _mm_set_epi16(0,0,0,0,0,0,0,1);}
into:
_doload64:
movaps LCPI1_0, %xmm0
ret
instead of:
_doload64:
subl $28, %esp
movl $0, 4(%esp)
movl $1, (%esp)
movq (%esp), %xmm0
addl $28, %esp
ret
llvm-svn: 48057
2008-03-08 22:59:52 +00:00
Chris Lattner
405f2c6356
minor simplifications to this code, don't create a dead
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SCALAR_TO_VECTOR on paths that end up not using it.
llvm-svn: 48056
2008-03-08 22:48:29 +00:00
Chris Lattner
ff9dc0af80
This one looks easy, add a note.
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llvm-svn: 48055
2008-03-08 22:32:39 +00:00
Chris Lattner
b12697f8bb
move these to the appropriate file
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llvm-svn: 48054
2008-03-08 22:28:45 +00:00
Dale Johannesen
55d6e1a5aa
More ppc32 byval handling (bug fixes). Things
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are looking pretty good now.
llvm-svn: 48043
2008-03-08 01:41:42 +00:00
Evan Cheng
dba1dfe962
Implement x86 support for @llvm.prefetch. It corresponds to prefetcht{0|1|2} and prefetchnta instructions.
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llvm-svn: 48042
2008-03-08 00:58:38 +00:00
Dan Gohman
afeac8050d
Add support for calls with i128 return values on ppc64.
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llvm-svn: 48041
2008-03-08 00:19:12 +00:00
Bill Wendling
948c50e2be
PPC64 passes arguments of integral type in i64 registers, not i32. Reflect this
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by promoting smaller integral values (i32 at this point) to i64, then truncating
to get the wanted size.
llvm-svn: 48030
2008-03-07 20:49:02 +00:00
Dan Gohman
5bf464e1e6
Add support for lowering 128-bit shifts on ppc64.
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llvm-svn: 48029
2008-03-07 20:36:53 +00:00
Dale Johannesen
3e6bacf7be
Next bits of PPC byval handling. Basically functional
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but there are bugs.
llvm-svn: 48028
2008-03-07 20:27:40 +00:00
Chris Lattner
08ec4919ea
Add support for ppc64 shifts with 7-bit (oversized) shift amount (e.g. PPCshl).
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llvm-svn: 48027
2008-03-07 20:18:24 +00:00
Chris Lattner
2f13ccc181
Replace SDT_PPCShiftOp in favor of SDTIntBinOps. This allows it to work
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with 32 or 64-bit operands/results.
llvm-svn: 48026
2008-03-07 20:13:51 +00:00
Chris Lattner
aa81dc7d21
mark frem as expand for all legal fp types on x86, regardless of whether
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we're using SSE or not. This fixes PR2122.
llvm-svn: 48006
2008-03-07 06:36:32 +00:00
Gabor Greif
92e00c1e50
some more spelling changes
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llvm-svn: 47996
2008-03-06 10:51:21 +00:00
Scott Michel
8dd2324903
Refine Cell's i64 constant generation code to cover more constants where the
...
upper and lower 32-bits are the same (in addition to 0 and -1 previously.)
llvm-svn: 47985
2008-03-06 04:02:54 +00:00
Andrew Lenharth
0c26f5bb94
gcc likes things spelled correctly
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llvm-svn: 47981
2008-03-05 23:41:37 +00:00
Dale Johannesen
6bcc9808db
Next bit of PPC ByVal handling; call-site code seems
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correct now.
llvm-svn: 47978
2008-03-05 23:31:27 +00:00
Scott Michel
c29399e54e
- Fix support for "special" i64 immediates that can be loaded
...
using IL, ILA, et. al. v2i64 and i64 are now supported by
the select bits (SELB) instruction.
- Add missing comparison operations (testcase forthcoming)
- More multiclass refactoring.
llvm-svn: 47973
2008-03-05 23:02:02 +00:00
Chris Lattner
83e0b885f8
evan implemented this.
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llvm-svn: 47948
2008-03-05 17:11:51 +00:00
Evan Cheng
a36562006a
isTwoAddress = 1 -> Constraints.
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llvm-svn: 47941
2008-03-05 08:19:16 +00:00
Evan Cheng
6c2bb7c67e
PSLLWri etc. are two-address instructions.
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llvm-svn: 47940
2008-03-05 08:11:27 +00:00
Chris Lattner
7571a88209
add a note
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llvm-svn: 47939
2008-03-05 07:22:39 +00:00
Evan Cheng
d421708e35
Ignore debugging related instructions if they get this far.
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llvm-svn: 47934
2008-03-05 02:34:36 +00:00
Evan Cheng
a2939a16de
Rather than asserting. Dump out the MI that we are not able to encode and abort.
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llvm-svn: 47933
2008-03-05 02:08:03 +00:00
Evan Cheng
e0b3c221ab
Add a target lowering hook to control whether it's worthwhile to compress fp constant.
...
For x86, if sse2 is available, it's not a good idea since cvtss2sd is slower than a movsd load and it prevents load folding. On x87, it's important to shrink fp constant since fldt is very expensive.
llvm-svn: 47931
2008-03-05 01:30:59 +00:00
Andrew Lenharth
95c88272c6
64bit CAS on 32bit x86.
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llvm-svn: 47929
2008-03-05 01:15:49 +00:00
Evan Cheng
18064ddb5b
Refactor code. Remove duplicated functions that basically do the same thing as
...
findRegisterUseOperandIdx, findRegisterDefOperandIndx. Fix some naming inconsistencies.
llvm-svn: 47927
2008-03-05 00:59:57 +00:00
Bill Wendling
37f5b4586a
Removed spurious EnablePPCRS check.
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llvm-svn: 47918
2008-03-04 23:27:33 +00:00
Dale Johannesen
86867d323e
Move PPC lowering functions into PPCTargetLowering
...
class (cosmetic). First piece of byval implementation;
this doesn't work yet. No functional change.
llvm-svn: 47917
2008-03-04 23:17:14 +00:00
Bill Wendling
dc9de245cb
Use a command-line option to turn register scavenging on/off for PPC.
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llvm-svn: 47915
2008-03-04 23:13:51 +00:00
Andrew Lenharth
f5674915c5
x86-64 atomics
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llvm-svn: 47903
2008-03-04 21:13:33 +00:00
Evan Cheng
ae414db8d2
80 column violations.
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llvm-svn: 47878
2008-03-04 03:20:06 +00:00
Evan Cheng
139517b682
Remove -always-fold-and-in-test.
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llvm-svn: 47871
2008-03-04 00:40:35 +00:00
Dan Gohman
ccc0bc5878
Add support for lowering i64 SRA_PARTS and friends on x86-64.
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llvm-svn: 47865
2008-03-03 22:22:09 +00:00
Bill Wendling
8d64999daf
This is the initial check-in for adding register scavenging to PPC. (Currently,
...
PPC-64 doesn't work.) This also lowers the spilling of the CR registers so that
it uses a register other than the default R0 register (the scavenger scrounges
for one). A significant part of this patch fixes how kill information is
handled.
llvm-svn: 47863
2008-03-03 22:19:16 +00:00
Devang Patel
d0d7028a2b
s/isReturnStruct()/hasStructRetAttr()/g
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llvm-svn: 47857
2008-03-03 21:46:28 +00:00
Chris Lattner
f818270d43
another random note
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llvm-svn: 47831
2008-03-02 19:29:42 +00:00
Chris Lattner
f2a9b32eec
add a note
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llvm-svn: 47830
2008-03-02 19:27:34 +00:00
Chris Lattner
299977b5ca
Evan implemented these.
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llvm-svn: 47828
2008-03-02 18:05:14 +00:00
Chris Lattner
4c67781884
Evan implemented this.
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llvm-svn: 47827
2008-03-02 17:56:29 +00:00
Chris Lattner
963b3c9039
add support for lvsl, fixing PR1481
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llvm-svn: 47825
2008-03-02 08:54:27 +00:00
Chris Lattner
fdcd03cc98
add support for the sse.cmp.* intrinsics, which fixes sse.isamax with the CBE.
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llvm-svn: 47824
2008-03-02 08:47:13 +00:00
Chris Lattner
7196bf5358
refactor intrinsic handling code out into its own method.
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llvm-svn: 47823
2008-03-02 08:29:41 +00:00
Chris Lattner
75c409057a
fix printing of undef vectors, this fixes "simple" and "build" in UnitTests/Vector.
...
Now they all pass.
llvm-svn: 47820
2008-03-02 08:14:45 +00:00
Chris Lattner
d8eeb6b1c8
insertelement got the wrong operands.
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llvm-svn: 47819
2008-03-02 08:10:16 +00:00
Chris Lattner
e9aa391b61
Several changes:
...
* Simplify handling of byval, making it easier to understand and more
consistent. This fixes PR2065.
* Clean up and simplify handling of GEPs. I can actually understand it now!
* Implement support for GEP'ing into vectors, this fixes
SingleSource/UnitTests/Vector/build2 among others.
llvm-svn: 47818
2008-03-02 08:07:24 +00:00
Chris Lattner
78f255dca8
Fix a bug I introduced in constant array and constant vector handling.
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llvm-svn: 47816
2008-03-02 05:46:57 +00:00
Chris Lattner
96469b446d
implement shufflevector.
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llvm-svn: 47815
2008-03-02 05:41:07 +00:00
Chris Lattner
18c26f3dad
implement extractelement.
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llvm-svn: 47812
2008-03-02 03:57:08 +00:00
Chris Lattner
72e898e589
implement insertelement.
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llvm-svn: 47811
2008-03-02 03:52:39 +00:00
Chris Lattner
85243c2223
respect isSigned for vector types, fixing sdiv of vectors etc.
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llvm-svn: 47810
2008-03-02 03:41:23 +00:00
Chris Lattner
980424b55c
print the attribute in the right place, this fixes function returning vectors.
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llvm-svn: 47809
2008-03-02 03:39:43 +00:00
Chris Lattner
112819e1e6
vector types are simple types. This fixes div/rem of vectors.
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llvm-svn: 47807
2008-03-02 03:33:31 +00:00
Chris Lattner
8eddd5055d
Print vector types appropriately. This gets basic vector code working
...
(PR1126)
llvm-svn: 47806
2008-03-02 03:29:50 +00:00
Chris Lattner
c5f37fc11d
rename PT -> VT for VectorTypes.
...
llvm-svn: 47805
2008-03-02 03:18:46 +00:00
Chris Lattner
a70385185e
Print i32/i64 integer constants as 1u instead of ((unsigned int)1).
...
Use dyn_cast better.
llvm-svn: 47804
2008-03-02 03:16:38 +00:00
Chris Lattner
38a684c0c9
Move pr717 to here.
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llvm-svn: 47803
2008-03-02 02:51:40 +00:00
Andrew Lenharth
ba7f925582
good catch anton
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llvm-svn: 47800
2008-03-01 23:18:21 +00:00
Andrew Lenharth
f6c220738c
make CAS work
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llvm-svn: 47799
2008-03-01 22:27:48 +00:00
Andrew Lenharth
b91c664226
all but CAS working on x86
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llvm-svn: 47798
2008-03-01 21:52:34 +00:00
Andrew Lenharth
ad29a49169
Add lock prefix support to x86. Also add the instructions necessary for the atomic ops. They are still marked pseudo, since I cannot figure out what format to use, but they are the correct opcode.
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llvm-svn: 47795
2008-03-01 13:37:02 +00:00