Owen Anderson
14abbb1a2e
Provide Thumb2 encodings for basic loads and stores.
...
llvm-svn: 120340
2010-11-29 22:44:32 +00:00
Bill Wendling
2271583883
Have the getAddrMode3OpValue() function in ARMCodeEmitter.cpp produce the same
...
value that the one in ARMMCCodeEmitter.cpp does.
llvm-svn: 119878
2010-11-20 00:26:37 +00:00
Jim Grosbach
941d812765
Minor cleanups to a few llvm_unreachable() calls.
...
llvm-svn: 119767
2010-11-19 00:27:09 +00:00
Jason W Kim
331b7407c8
Fix .o emission of ARM movt/movw. MCSymbolRefExpr::VK_ARM_(HI||LO)16 for the .o path now works for ARM.
...
Note: lo16AllZero remains in ARMInstrInfo.td - It can be factored out when Thumb movt is repaired.
Existing tests cover this update.
llvm-svn: 119760
2010-11-18 23:37:15 +00:00
Jim Grosbach
5d9d8356fa
Clean up LEApcrel instuction(s) a bit. It's not really a Pseudo, so don't mark
...
it as such. Add some encoding information.
llvm-svn: 119588
2010-11-17 23:33:14 +00:00
Jim Grosbach
16aeabf0d5
Fix comment typo.
...
llvm-svn: 119573
2010-11-17 21:57:51 +00:00
Bill Wendling
7d3f3104d7
The machine instruction no longer encodes the submode as a separate operand. We
...
should get the submode from the load/store multiple instruction's opcode.
llvm-svn: 119461
2010-11-17 05:31:09 +00:00
Jim Grosbach
7aabb8c5ee
ARM LDR_PRE/LDR_POST/STR_PRE/STR_POST (and the *B counterparts) binary encoding.
...
llvm-svn: 119180
2010-11-15 20:47:07 +00:00
Evan Cheng
f3c75f91e9
Eliminate ARM::MOVi2pieces. Just use MOVi32imm and expand it to either movi+orr or movw+movt depending on the subtarget.
...
llvm-svn: 118938
2010-11-12 23:03:38 +00:00
Owen Anderson
f1ffc8fdc9
First stab at providing correct Thumb2 encodings, start with adc.
...
llvm-svn: 118924
2010-11-12 21:12:40 +00:00
Owen Anderson
85cf1b8ff5
Fill out support for Thumb2 encodings of NEON instructions.
...
llvm-svn: 118854
2010-11-11 23:12:55 +00:00
Owen Anderson
0913dac245
Add correct Thumb2 encodings for NEON vst[1,2,3,4] and vld[1,2,3,4].
...
llvm-svn: 118843
2010-11-11 21:36:43 +00:00
Owen Anderson
f43f09f6f6
Add support for Thumb2 encodings of NEON data processing instructions, using the new PostEncoderMethod infrastructure.
...
More tests to come.
llvm-svn: 118819
2010-11-11 19:07:48 +00:00
Jim Grosbach
abf0e10ea0
Encoding of destination fixup for ARM branch and conditional branch
...
instructions.
llvm-svn: 118801
2010-11-11 18:04:49 +00:00
Jim Grosbach
cfc32e3b5a
Encoding for ARM LDRSH_POST.
...
llvm-svn: 118794
2010-11-11 16:55:29 +00:00
Jim Grosbach
3b13f9013c
ARM STRH encoding information.
...
llvm-svn: 118757
2010-11-11 01:09:40 +00:00
Jim Grosbach
ad037e5ded
ARM LDM encoding for the mode (ia, ib, da, db) operand.
...
llvm-svn: 118736
2010-11-10 23:38:36 +00:00
Jim Grosbach
f64560f315
Add encoder method for ARM load/store shifted register offset operands.
...
llvm-svn: 118513
2010-11-09 17:20:53 +00:00
Bill Wendling
34599f4aa8
The MC code couldn't handle ARM LDR instructions with negative offsets:
...
vldr.64 d1, [r0, #-32]
The problem was with how the addressing mode 5 encodes the offsets. This change
makes sure that the way offsets are handled in addressing mode 5 is consistent
throughout the MC code. It involves re-refactoring the "getAddrModeImmOpValue"
method into an "Imm12" and "addressing mode 5" version. But not to worry! The
majority of the duplicated code has been unified.
llvm-svn: 118144
2010-11-03 01:49:29 +00:00
Bill Wendling
1546322a9c
Rename getAddrModeImm12OpValue to getAddrModeImmOpValue and expand it to work
...
with immediates up to 16-bits in size. The same logic is applied to other LDR
encodings, e.g. VLDR, but which use a different immediate bit width (8-bits in
VLDR's case). Removing the "12" allows it to be more generic.
llvm-svn: 118094
2010-11-02 22:31:46 +00:00
Owen Anderson
8aba4dbe03
Rename encoder methods to match naming convention.
...
llvm-svn: 118093
2010-11-02 22:28:01 +00:00
Owen Anderson
9d85c89ade
Add correct NEON encodings for vld2, vld3, and vld4 basic variants.
...
llvm-svn: 117997
2010-11-02 01:24:55 +00:00
Owen Anderson
6647eb222b
Add correct NEON encodings for the "multiple single elements" form of vld.
...
llvm-svn: 117984
2010-11-02 00:05:05 +00:00
Jim Grosbach
996d1280bd
Encode the register list operands for ARM mode LDM/STM instructions.
...
llvm-svn: 117753
2010-10-30 00:37:59 +00:00
Jim Grosbach
7ca6ac347d
80 column fix.
...
llvm-svn: 117741
2010-10-29 23:21:57 +00:00
Jim Grosbach
7cf8dcc5bd
s/getNEONVcvtImm32/getNEONVcvtImm32OpValue/ to be consistent with other operand
...
encoder functions.
llvm-svn: 117738
2010-10-29 23:19:55 +00:00
Jim Grosbach
86ecfda983
Refactor ARM STR/STRB instruction patterns into STR{B}i12 and STR{B}rs, like
...
the LDR instructions have. This makes the literal/register forms of the
instructions explicit and allows us to assign scheduling itineraries
appropriately. rdar://8477752
llvm-svn: 117505
2010-10-27 23:12:14 +00:00
Owen Anderson
9437a20a72
Provide correct encodings for NEON vcvt, which has its own special immediate encoding
...
for specifying fractional bits for fixed point conversions.
llvm-svn: 117501
2010-10-27 22:49:00 +00:00
Jim Grosbach
db7ba38ca4
JIT imm12 encoding for constant pool entry references.
...
llvm-svn: 117483
2010-10-27 20:39:40 +00:00
Jim Grosbach
0df1207e99
ARM JIT fix for LDRi12 and company.
...
llvm-svn: 117478
2010-10-27 19:55:59 +00:00
Jim Grosbach
5d4415c6b0
The new LDR* instruction patterns should handle the necessary encoding of
...
operands in the TableGen'erated bits, so we don't need to do the additional
magic explicitly.
llvm-svn: 117461
2010-10-27 17:52:51 +00:00
Jim Grosbach
30f6744f05
First part of refactoring ARM addrmode2 (load/store) instructions to be more
...
explicit about the operands. Split out the different variants into separate
instructions. This gives us the ability to, among other things, assign
different scheduling itineraries to the variants. rdar://8477752.
llvm-svn: 117409
2010-10-26 22:37:02 +00:00
Gabor Greif
6e58dbc9e4
fix memory-layout assumption which only holds on little-endian systems
...
llvm-svn: 117176
2010-10-22 23:16:11 +00:00
Jim Grosbach
cb41e97b5c
ARM Binary encoding information for BFC/BFI instructions.
...
llvm-svn: 117072
2010-10-21 22:03:21 +00:00
Bill Wendling
0f96ff63b3
Add encodings for movement between ARM core registers and single-precision
...
registers.
llvm-svn: 116961
2010-10-20 22:44:54 +00:00
Bill Wendling
8e4ceb45f2
ARMCodeEmitter::emitMiscInstruction is dead. Long live
...
ARMCodeEmitter::emitMiscInstruction!
llvm-svn: 116644
2010-10-15 23:35:12 +00:00
Jim Grosbach
67f94c42d8
ARM mode encoding information for UBFX and SBFX instructions.
...
llvm-svn: 116588
2010-10-15 17:15:16 +00:00
Jim Grosbach
29dc23398f
Tweak the ARM backend to use the RRX mnemonic instead of the 'mov a, b, rrx'
...
pseudonym.
llvm-svn: 116512
2010-10-14 20:43:44 +00:00
Bill Wendling
33a2ecd5e4
Add encoding for 'fmstat'.
...
llvm-svn: 116466
2010-10-14 01:19:34 +00:00
Bill Wendling
cd41f22ec1
- Add encodings for multiply add/subtract instructions in all their glory.
...
- Add missing patterns for some multiply add/subtract instructions.
- Add encodings for VMRS and VMSR.
llvm-svn: 116464
2010-10-14 01:02:08 +00:00
Jim Grosbach
8f0bea85bf
Add ARM mode encoding for [SU]XT[BH] and [SU]XTA[BH] instructions.
...
llvm-svn: 116421
2010-10-13 19:56:10 +00:00
Jim Grosbach
79cebf409d
Add the rest of the ARM so_reg encoding options (register shifted register)
...
and move to a custom operand encoder. Remove the last of the special handling
stuff from ARMMCCodeEmitter::EncodeInstruction.
llvm-svn: 116377
2010-10-12 23:53:58 +00:00
Jim Grosbach
de78ccb013
Move the ARM so_imm encoding into a custom operand encoder and remove the
...
explicit handling of the instructions referencing it from the MC code
emitter.
llvm-svn: 116367
2010-10-12 23:18:08 +00:00
Jim Grosbach
f4cf5bef46
Add custom encoder for the 's' bit denoting whether an ARM arithmetic
...
instruction should set the processor status flags or not. Remove the now
unnecessary special handling for the bit from the MCCodeEmitter.
llvm-svn: 116360
2010-10-12 23:00:24 +00:00
Jim Grosbach
85b45fcc52
Reapply 116059, this time without the fatfingered pasto at the top.
...
''const'ify getMachineOpValue() and associated helpers.'
llvm-svn: 116067
2010-10-08 17:45:54 +00:00
Jim Grosbach
674fa65e33
Reverting 116059. Bots are unhappy with it.
...
llvm-svn: 116064
2010-10-08 17:28:40 +00:00
Jim Grosbach
8d4bb23650
'const'ify getMachineOpValue() and associated helpers.
...
llvm-svn: 116059
2010-10-08 16:52:44 +00:00
Jim Grosbach
df2ff926a6
Make <target>CodeEmitter::getBinaryCodeForInstr() a const method.
...
llvm-svn: 116018
2010-10-08 00:21:28 +00:00
Jim Grosbach
2699e92c0e
move getRegisterNumbering() to out of ARMBaseRegisterInfo into the helper
...
functions in ARMBaseInfo.h so it can be used in the MC library as well.
For anything bigger than this, we may want a means to have a small support
library for shared helper functions like this. Cross that bridge when we
come to it.
llvm-svn: 114016
2010-09-15 20:26:25 +00:00
Jim Grosbach
8a4ae35eed
Refactor uses of getRegisterNumbering() to not need the isSPVFP argument. Check
...
if the register is a member of the SPR register class directly instead.
llvm-svn: 114012
2010-09-15 19:44:57 +00:00
Chris Lattner
8df3ffd7ac
zap dead code.
...
llvm-svn: 113073
2010-09-04 18:12:00 +00:00
Bob Wilson
31d487d235
Change ARM VFP VLDM/VSTM instructions to use addressing mode #4 , just like
...
all the other LDM/STM instructions. This fixes asm printer crashes when
compiling with -O0. I've changed one of the NEON tests (vst3.ll) to run
with -O0 to check this in the future.
Prior to this change VLDM/VSTM used addressing mode #5 , but not really.
The offset field was used to hold a count of the number of registers being
loaded or stored, and the AM5 opcode field was expanded to specify the IA
or DB mode, instead of the standard ADD/SUB specifier. Much of the backend
was not aware of these special cases. The crashes occured when rewriting
a frameindex caused the AM5 offset field to be changed so that it did not
have a valid submode. I don't know exactly what changed to expose this now.
Maybe we've never done much with -O0 and NEON. Regardless, there's no longer
any reason to keep a count of the VLDM/VSTM registers, so we can use
addressing mode #4 and clean things up in a lot of places.
llvm-svn: 112322
2010-08-27 23:18:17 +00:00
Bob Wilson
e382fce916
Change ARM PKHTB and PKHBT instructions to use a shift_imm operand to avoid
...
printing "lsl #0 ". This fixes the remaining parts of pr7792. Make
corresponding changes for encoding/decoding these instructions.
llvm-svn: 111251
2010-08-17 17:23:19 +00:00
Bob Wilson
3582107cf8
Move the ARM SSAT and USAT optional shift amount operand out of the
...
instruction opcode. This also fixes part of PR7792.
llvm-svn: 110875
2010-08-11 23:10:46 +00:00
Bob Wilson
0650cceb38
Add a separate ARM instruction format for Saturate instructions.
...
(I discovered 2 more copies of the ARM instruction format list, bringing the
total to 4!! Two of them were already out of sync. I haven't yet gotten into
the disassembler enough to know the best way to fix this, but something needs
to be done.) Add support for encoding these instructions.
llvm-svn: 110754
2010-08-11 00:01:18 +00:00
Owen Anderson
f2fea95f2f
Reapply r110396, with fixes to appease the Linux buildbot gods.
...
llvm-svn: 110460
2010-08-06 18:33:48 +00:00
Owen Anderson
aadd8a89ca
Revert r110396 to fix buildbots.
...
llvm-svn: 110410
2010-08-06 00:23:35 +00:00
Owen Anderson
b9762c07cb
Don't use PassInfo* as a type identifier for passes. Instead, use the address of the static
...
ID member as the sole unique type identifier. Clean up APIs related to this change.
llvm-svn: 110396
2010-08-05 23:42:04 +00:00
Xerxes Ranby
c7a04bcaa5
ARMv4 JIT forgets to set the lr register when making a indirect function call. Fixes PR7608
...
llvm-svn: 109125
2010-07-22 17:28:34 +00:00
Bill Wendling
e2833a21c2
Rename DBG_LABEL PROLOG_LABEL, because it's only used during prolog emission and
...
thus is a much more meaningful name.
llvm-svn: 108563
2010-07-16 22:20:36 +00:00
Bob Wilson
1b4210315e
Add support for encoding VDUP (ARM core register) instructions.
...
llvm-svn: 107201
2010-06-29 20:13:29 +00:00
Bob Wilson
be81c92b41
Add support for encoding NEON VMOV (from core register to scalar) instructions.
...
The encoding is the same as VMOV (from scalar to core register) except that
the operands are in different places.
llvm-svn: 107167
2010-06-29 17:34:07 +00:00
Bob Wilson
2a4e6d0e34
Fix Thumb encoding of VMOV (scalar to ARM core register). The encoding is
...
the same as ARM except that the condition code field is always set to ARMCC::AL.
llvm-svn: 107107
2010-06-29 00:26:13 +00:00
Bob Wilson
aee90dacaa
Make the ARMCodeEmitter identify Thumb functions via ARMFunctionInfo instead
...
of the Subtarget.
llvm-svn: 107086
2010-06-28 22:23:17 +00:00
Bob Wilson
378395412f
Refactor encoding function for NEON 1-register with modified immediate format.
...
llvm-svn: 107070
2010-06-28 21:16:30 +00:00
Bob Wilson
6385cb2386
Support Thumb mode encoding of NEON instructions.
...
llvm-svn: 107068
2010-06-28 21:12:19 +00:00
Bob Wilson
aff7e7c1cc
Add support for encoding NEON VMOV (from scalar to core register) instructions.
...
llvm-svn: 106938
2010-06-26 04:07:15 +00:00
Bob Wilson
d1e4e67954
Add support for encoding 3-register NEON instructions, and fix
...
emitNEON2RegInstruction's handling of 2-address operands.
llvm-svn: 106900
2010-06-25 22:40:46 +00:00
Bob Wilson
a1739048a1
Add support for encoding 2-register NEON instructions.
...
llvm-svn: 106891
2010-06-25 21:17:19 +00:00
Dan Gohman
74d5144414
Use pre-increment instead of post-increment when the result is not used.
...
llvm-svn: 106542
2010-06-22 15:08:57 +00:00
Bob Wilson
5e3c60fb63
Add instruction encoding for the Neon VMOV immediate instruction. This changes
...
the machine instruction representation of the immediate value to be encoded
into an integer with similar fields as the actual VMOV instruction. This makes
things easier for the disassembler, since it can just stuff the bits into the
immediate operand, but harder for the asm printer since it has to decode the
value to be printed. Testcase for the encoding will follow later when MC has
more support for ARM.
llvm-svn: 105836
2010-06-11 21:34:50 +00:00
Jim Grosbach
f3bd81ce11
Clean up 80 column violations. No functional change.
...
llvm-svn: 105350
2010-06-02 21:53:11 +00:00
Shih-wei Liao
c535c0e055
Coding style change (Adding 1 missing space.)
...
llvm-svn: 104670
2010-05-26 04:46:50 +00:00
Shih-wei Liao
2f4221272a
Adding the missing implementation for ARM::SBFX and ARM::UBFX.
...
Fixing http://llvm.org/bugs/show_bug.cgi?id=7225 .
llvm-svn: 104667
2010-05-26 03:21:39 +00:00
Shih-wei Liao
007309e940
Adding the missing implementation of Bitfield's "clear" and "insert".
...
Fixing http://llvm.org/bugs/show_bug.cgi?id=7222 .
llvm-svn: 104653
2010-05-26 00:25:05 +00:00
Shih-wei Liao
4a26d7ca61
To handle s* registers in emitVFPLoadStoreMultipleInstruction().
...
Fixing http://llvm.org/bugs/show_bug.cgi?id=7221 .
llvm-svn: 104652
2010-05-26 00:02:28 +00:00
Zonr Chang
465ebb1bcf
Add missing implementation to the materialization of VFP misc. instructions (vmrs, vmsr and vmov (immediate))
...
llvm-svn: 104588
2010-05-25 10:23:52 +00:00
Zonr Chang
5ce8b82ebf
Add support to MOVimm32 using movt/movw for ARM JIT
...
llvm-svn: 104587
2010-05-25 08:42:45 +00:00
Dan Gohman
fba34ef042
Fix -Wcast-qual warnings.
...
llvm-svn: 101655
2010-04-17 17:42:52 +00:00
Dan Gohman
0e0b8cf9fd
Add const qualifiers to CodeGen's use of LLVM IR constructs.
...
llvm-svn: 101334
2010-04-15 01:51:59 +00:00
Chris Lattner
80b41881bc
rename llvm::llvm_report_error -> llvm::report_fatal_error
...
llvm-svn: 100709
2010-04-07 22:58:41 +00:00
Bob Wilson
2fcf1547f2
Clean up whitespace.
...
llvm-svn: 98769
2010-03-17 21:16:45 +00:00
Bob Wilson
aee6e76a7d
Remove redundant writeback flag in ARM addressing mode 5.
...
llvm-svn: 98648
2010-03-16 18:38:09 +00:00
Bob Wilson
279818d473
Remove the writeback flag from ARM's address mode 4. Now that we have separate
...
instructions for ld/st with writeback, the flag is completely redundant.
llvm-svn: 98643
2010-03-16 17:46:45 +00:00
Chris Lattner
ba3b320aa3
change the DBG_LABEL MachineInstr to always be created
...
with an MCSymbol instead of an immediate.
llvm-svn: 98481
2010-03-14 07:56:48 +00:00
Chris Lattner
5fef80c5aa
change the LabelSDNode to be EHLabelSDNode and make it hold
...
an MCSymbol. Make the EH_LABEL MachineInstr hold its label
with an MCSymbol instead of ID. Fix a bug in MMI.cpp which
would return labels named "Label4" instead of "label4".
llvm-svn: 98463
2010-03-14 02:33:54 +00:00
Chris Lattner
149cf816bb
change EH related stuff (other than EH_LABEL) to use MCSymbol
...
instead of label ID's. This cleans up and regularizes a bunch
of code and makes way for future progress.
Unfortunately, this pointed out to me that JITDwarfEmitter.cpp
is largely copy and paste from DwarfException/MachineModuleInfo
and other places. This is very sad and disturbing. :(
One major change here is that TidyLandingPads moved from being
called in DwarfException::BeginFunction to being called in
DwarfException::EndFunction. There should not be any
functionality change from doing this, but I'm not an EH expert.
llvm-svn: 98459
2010-03-14 01:41:15 +00:00
Bob Wilson
163aa28fa1
Attempt to appease the arm-linux buildbot by fixing the JIT encodings for new
...
base register updating load/store-multiple instructions.
llvm-svn: 98427
2010-03-13 07:34:35 +00:00
Bob Wilson
1ce9157601
Fix ARM buildbot breakage.
...
llvm-svn: 98215
2010-03-11 00:46:22 +00:00
Bob Wilson
e49828788b
Fix an obvious typo in an assert.
...
Patch by Sean Callanan.
llvm-svn: 98200
2010-03-10 22:38:45 +00:00
Anton Korobeynikov
e0e616a74d
Initial bits of ARMv4-only support.
...
Patch by John Tytgat!
llvm-svn: 97886
2010-03-06 19:39:36 +00:00
Chris Lattner
7acf9be6c4
move target-independent opcodes out of TargetInstrInfo
...
into TargetOpcodes.h. #include the new TargetOpcodes.h
into MachineInstr. Add new inline accessors (like isPHI())
to MachineInstr, and start using them throughout the
codebase.
llvm-svn: 95687
2010-02-09 19:54:29 +00:00
Chris Lattner
6996a481db
tidy some targets.
...
llvm-svn: 95146
2010-02-02 22:13:21 +00:00
Chris Lattner
00a839b592
detemplatize ARM code emitter.
...
llvm-svn: 95138
2010-02-02 21:48:51 +00:00
Chris Lattner
ec61994b1d
remove dead code.
...
llvm-svn: 95134
2010-02-02 21:38:59 +00:00
Chris Lattner
e3f214b438
prep work to support a future where getJumpTableInfo will return
...
a null pointer for functions with no jump tables. No functionality
change.
llvm-svn: 94469
2010-01-25 23:22:00 +00:00
Dan Gohman
b5ec39e2dc
Remove ISD::DEBUG_LOC and ISD::DBG_LABEL, which are no longer used.
...
Note that "hasDotLocAndDotFile"-style debug info was already broken;
people wanting this functionality should implement it in the
AsmPrinter/DwarfWriter code.
llvm-svn: 89711
2009-11-23 23:20:51 +00:00
Jeffrey Yasskin
502d93267d
Make the need-stub variables accurate and consistent. In the case of
...
MachineRelocations, "stub" always refers to a far-call stub or a
load-a-faraway-global stub, so this patch adds "Far" to the term. (Other stubs
are used for lazy compilation and dlsym address replacement.) The variable was
also inconsistent between the positive and negative sense, and the positive
sense ("NeedStub") was more demanding than is accurate (since a nearby-enough
function can be called directly even if the platform often requires a stub).
Since the negative sense causes double-negatives, I switched to
"MayNeedFarStub" globally.
llvm-svn: 86363
2009-11-07 08:51:52 +00:00
Bob Wilson
6eb4f53d90
Add support for BlockAddress values in ARM constant pools.
...
llvm-svn: 85806
2009-11-02 16:59:06 +00:00
Nick Lewycky
2b8400628d
Remove includes of Support/Compiler.h that are no longer needed after the
...
VISIBILITY_HIDDEN removal.
llvm-svn: 85043
2009-10-25 06:57:41 +00:00