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170 Commits

Author SHA1 Message Date
Hao Liu
4c6cc894d2 Fix the bugs about AArch64 Load/Store vector types and bitcast between i64 and vector types. 
e.g. "%tmp = load <2 x i64>* %ptr" can't be selected. 
     "%tmp = bitcast i64 %in to <2 x i32>" can't be selected.

llvm-svn: 195424
 2013-11-22 08:47:22 +00:00
Hao Liu
b1bce975ea Revert last change by haoliu because of buildbot failure. 
llvm-svn: 195423
 2013-11-22 08:34:54 +00:00
Hao Liu
eb2535e203 Fix a Cygwin build failure caused by enum values starting with '_', which is conflicted with some platform macros. 
This solution only renames variables, no functional change.

NOTE: This is a candidate for the 3.4 branch.
llvm-svn: 195421
 2013-11-22 08:17:16 +00:00
Jiangning Liu
a50f9e81f3 For AArch64 back-end instruction selection, lower Neon_Lowxxx with EXTRCT_SUBREG. 
llvm-svn: 195408
 2013-11-22 02:45:13 +00:00
Ana Pazos
86d72bbede Implemented Neon scalar vdup_lane intrinsics. 
Fixed scalar dup alias and added test case.

llvm-svn: 195330
 2013-11-21 08:16:15 +00:00
Ana Pazos
5ddc31e426 Implemented Neon scalar by element intrinsics. 
Intrinsics implemented: vqdmull_lane, vqdmulh_lane, vqrdmulh_lane,
vqdmlal_lane, vqdmlsl_lane scalar Neon intrinsics.

llvm-svn: 195327
 2013-11-21 07:37:04 +00:00
Hao Liu
b26dfe0306 Implement AArch64 neon instructions class SIMD lsone and SIMD lone-post. 
llvm-svn: 195078
 2013-11-19 02:17:05 +00:00
Jiangning Liu
42b7a215f4 Implement AArch64 SISD intrinsics for vget_high and vget_low. 
llvm-svn: 195074
 2013-11-19 01:46:48 +00:00
Kevin Qin
7b74269765 implement MC layer of AArch64 neon instruction PMULL and PMULL2 with 128 bit integer. 
llvm-svn: 195072
 2013-11-19 01:40:25 +00:00
Jiangning Liu
7c858f236d Add predicate for AArch64 crypto instructions. 
llvm-svn: 195071
 2013-11-19 01:38:31 +00:00
Juergen Ributzka
5357a6d64b [weak vtables] Remove a bunch of weak vtables 
This patch removes most of the trivial cases of weak vtables by pinning them to
a single object file. The memory leaks in this version have been fixed. Thanks
Alexey for pointing them out.

Differential Revision: http://llvm-reviews.chandlerc.com/D2068

Reviewed by Andy

llvm-svn: 195064
 2013-11-19 00:57:56 +00:00
Alexey Samsonov
3bfef6bdb6 Revert r194865 and r194874. 
This change is incorrect. If you delete virtual destructor of both a base class
and a subclass, then the following code:
  Base *foo = new Child();
  delete foo;
will not cause the destructor for members of Child class. As a result, I observe
plently of memory leaks. Notable examples I investigated are:
ObjectBuffer and ObjectBufferStream, AttributeImpl and StringSAttributeImpl.

llvm-svn: 194997
 2013-11-18 09:31:53 +00:00
Kevin Qin
eb2e892703 [AArch64 NEON]Add mov alias for simd copy instructions. 
Set some unspecified bits of INS/DUP to zero as ARMARM requested.

llvm-svn: 194996
 2013-11-18 09:20:32 +00:00
Hao Liu
fcc294f3dd Implement the newly added ACLE functions for ld1/st1 with 2/3/4 vectors. 
The functions are like: vst1_s8_x2 ...

llvm-svn: 194990
 2013-11-18 06:31:53 +00:00
Ana Pazos
b1568fd504 Implemented aarch64 Neon scalar vmulx_lane intrinsics 
Implemented aarch64 Neon scalar vfma_lane intrinsics
Implemented aarch64 Neon scalar vfms_lane intrinsics

Implemented legacy vmul_n_f64, vmul_lane_f64, vmul_laneq_f64
intrinsics (v1f64 parameter type) using Neon scalar instructions.

Implemented legacy vfma_lane_f64, vfms_lane_f64,
vfma_laneq_f64, vfms_laneq_f64 intrinsics (v1f64 parameter type)
using Neon scalar instructions.

llvm-svn: 194888
 2013-11-15 23:32:10 +00:00
Juergen Ributzka
ee3af15269 [weak vtables] Remove a bunch of weak vtables 
This patch removes most of the trivial cases of weak vtables by pinning them to
a single object file.

Differential Revision: http://llvm-reviews.chandlerc.com/D2068

Reviewed by Andy

llvm-svn: 194865
 2013-11-15 22:34:48 +00:00
Chad Rosier
6b1d577e71 [AArch64] Fix the scalar NEON ACLE functions so that they return float/double 
rather than the vector equivalent.

llvm-svn: 194853
 2013-11-15 21:28:10 +00:00
Alexey Samsonov
081e3ce6c8 Hopefully fix uninitialized memory read in AArch64AsmParser found by MSan bootstrap bot 
llvm-svn: 194818
 2013-11-15 15:49:30 +00:00
Chad Rosier
7891b8257a [AArch64] Remove redundant Neon_immAllOnes/Neon_immAllZeros leaf patterns. 
llvm-svn: 194733
 2013-11-14 22:02:46 +00:00
NAKAMURA Takumi
878c6ce6b5 AArch64DAGToDAGISel::SelectVTBL(): Fix a warning. [-Wunused-variable] 
llvm-svn: 194679
 2013-11-14 07:04:07 +00:00
Kevin Qin
7409a29609 [AArch64 neon] support poly64 and relevant intrinsic functions. 
llvm-svn: 194659
 2013-11-14 03:27:58 +00:00
Kevin Qin
47a3b639e3 Implement aarch64 neon instruction class SIMD misc. 
llvm-svn: 194656
 2013-11-14 02:44:13 +00:00
Jiangning Liu
5a9b5605ba Implement AArch64 NEON instruction set AdvSIMD (table). 
llvm-svn: 194648
 2013-11-14 01:57:32 +00:00
Chad Rosier
fae5b22550 [AArch64] Add support for legacy AArch32 NEON scalar shift by immediate 
instructions.  This patch does not include the shift right and accumulate
instructions.  A number of non-overloaded intrinsics have been remove in favor
of their overloaded counterparts.

llvm-svn: 194598
 2013-11-13 20:05:37 +00:00
Chad Rosier
ba5d2d1be6 [AArch64] Implemented AdvSIMD scalar x indexed element format and AdvSIMD scalar 
copy in MC layer. Added the MC layer tests.  Fixed triple setting in test cases.

Patch by Ana Pazos <apazos@codeaurora.org>.

llvm-svn: 194501
 2013-11-12 19:13:08 +00:00
Chad Rosier
8d7ebe36dd [AArch64] The shift right/left and insert immediate builtins expect 3 
source operands, a vector, an element to insert, and a shift amount.

llvm-svn: 194406
 2013-11-11 19:11:11 +00:00
Chad Rosier
4848250116 [AArch64] Add support for NEON scalar floating-point convert to fixed-point instructions. 
llvm-svn: 194394
 2013-11-11 18:04:07 +00:00
Tim Northover
cafa93e8e2 AArch64: refactor vector list creation to be more uniform 
Instructions taking a vector list (e.g. "ld2 {v0.2d, v1.d2}, [x0]") need a
special register-class to deal with the constraints, and C++ code to support
selection. However, that C++ code can be made reasonably uniform to simplify
the selection process. Hence this patch.

No functionality change, so no tests.

llvm-svn: 194361
 2013-11-11 03:35:43 +00:00
Benjamin Kramer
1a2fc10168 Remove some unnecessary temporary strings. 
llvm-svn: 194335
 2013-11-09 22:48:13 +00:00
Richard Barton
23f9645b7b Make PrintAsmOperand call to the superclass to handle 'n' and 'c' operand modifiers. 
llvm-svn: 194270
 2013-11-08 18:09:57 +00:00
Amara Emerson
5240ae1ac8 [AArch64] Remove NEON from "generic" CPU target. 
We can change this back when NEON support is complete and ready to become
enabled by default.

llvm-svn: 194152
 2013-11-06 16:19:08 +00:00
Jiangning Liu
9c0eb8e7ba Implement AArch64 Neon instruction set Perm. 
llvm-svn: 194123
 2013-11-06 03:35:27 +00:00
Jiangning Liu
1cdd311f06 Implement AArch64 Neon instruction set Bitwise Extract. 
llvm-svn: 194118
 2013-11-06 02:25:49 +00:00
Jiangning Liu
59b8117b0b Implement AArch64 Neon Crypto instruction classes AES, SHA, and 3 SHA. 
llvm-svn: 194085
 2013-11-05 17:42:05 +00:00
Hao Liu
386d8dd5a6 Implement AArch64 post-index vector load/store multiple N-element structure class SIMD(lselem-post). 
Including following 14 instructions:
4 ld1 insts: post-index load multiple 1-element structure to sequential 1/2/3/4 registers.
ld2/ld3/ld4: post-index load multiple N-element structure to sequential N registers (N=2,3,4).
4 st1 insts: post-index store multiple 1-element structure from sequential 1/2/3/4 registers.
st2/st3/st4: post-index store multiple N-element structure from sequential N registers (N = 2,3,4).

llvm-svn: 194043
 2013-11-05 03:39:32 +00:00
Kevin Qin
63fa5c1ef6 Implemented aarch64 neon intrinsic vcopy_lane with float type. 
llvm-svn: 194041
 2013-11-05 02:03:59 +00:00
Tim Northover
6110ffc9ca AArch64: use default asm operand printing when modifier inapplicable 
If an inline assembly operand has multiple constraints (e.g. "Ir" for immediate
or register) and an operand modifier (E.g. "w" for "print register as wN") then
we need to decide behaviour when the modifier doesn't apply to the constraint.

Previousely produced some combination of an assertion failure and a fatal
error. GCC's behaviour appears to be to ignore the modifier and print the
operand in the default way. This patch should implement that.

llvm-svn: 194024
 2013-11-04 23:04:07 +00:00
Chad Rosier
3f3427283c [AArch64] Simplify a few of the instruction patterns. No functional change intended. 
llvm-svn: 193867
 2013-11-01 17:13:44 +00:00
Chad Rosier
0701443fc8 [AArch64] Fix assembly string formatting and other coding standard violations. 
llvm-svn: 193866
 2013-11-01 17:13:42 +00:00
Chad Rosier
fd7dc7524c [AArch64] Add support for NEON scalar fixed-point convert to floating-point instructions. 
llvm-svn: 193816
 2013-10-31 22:36:59 +00:00
Chad Rosier
aea5ba449f [AArch64] Add support for NEON scalar shift immediate instructions. 
llvm-svn: 193790
 2013-10-31 19:28:44 +00:00
Amara Emerson
ce9bb052e5 [AArch64] Make the use of FP instructions optional, but enabled by default. 
This adds a new subtarget feature called FPARMv8 (implied by NEON), and
predicates the support of the FP instructions and registers on this feature.

llvm-svn: 193739
 2013-10-31 09:32:11 +00:00
Chad Rosier
02e430c891 [AArch64] Add support for NEON scalar floating-point compare instructions. 
llvm-svn: 193691
 2013-10-30 15:19:37 +00:00
Rafael Espindola
68ddc56344 Add a helper getSymbol to AsmPrinter. 
llvm-svn: 193627
 2013-10-29 17:07:16 +00:00
Weiming Zhao
02f69c25b7 [AArch64] Implement FrameAddr and ReturnAddr 
Fixes PR17690

llvm-svn: 193625
 2013-10-29 17:00:25 +00:00
Tim Northover
30527a23a1 AArch64: add 'a' inline asm operand modifier 
This is used in the Linux kernel, and effectively just means "print an
address".

llvm-svn: 193593
 2013-10-29 08:22:33 +00:00
Nadav Rotem
d99242eb75 Optimize concat_vectors(X, undef) -> scalar_to_vector(X). 
This optimization is not SSE specific so I am moving it to DAGco.
The new scalar_to_vector dag node exposed a missing pattern in the AArch64 target that I needed to add.

llvm-svn: 193393
 2013-10-25 06:41:18 +00:00
Amara Emerson
de52a239bd [AArch64] Fix NZCV reg live-in bug in F128CSEL codegen. 
When generating the IfTrue basic block during the F128CSEL pseudo-instruction
handling, the NZCV live-in for the newly created BB wasn't being added. This
caused a fault during MI-sched/live range calculation when the predecessor
for the fall-through BB didn't have a live-in for phys-reg as expected.

llvm-svn: 193316
 2013-10-24 08:28:24 +00:00
Chad Rosier
838b6065b8 [AArch64] Add the constraint to NEON scalar mla/mls instructions. 
llvm-svn: 193117
 2013-10-21 20:11:47 +00:00
Chad Rosier
163fdd3e73 [AArch64] Add support for NEON scalar extract narrow instructions. 
llvm-svn: 192970
 2013-10-18 14:03:24 +00:00