1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-24 03:33:20 +01:00
Commit Graph

204857 Commits

Author SHA1 Message Date
Roman Lebedev
60367f78e7 Revert "[NFC][SCEV] Improve tests for ptrtoint modelling (D88806)"
Buildbots aren't happy, need to investigate.
This reverts commit 32cc8f7998abe1824e0832a49b66559471c9b879.
2020-10-09 14:10:43 +03:00
Jonas Paulsson
9a455a4c8e [SystemZ] Use LA instead of AGR in eliminateFrameIndex().
Since AGR clobbers CC it should not be used here.

Fixes https://bugs.llvm.org/show_bug.cgi?id=47736.

Review: Ulrich Weigand
Differential Revision: https://reviews.llvm.org/D89034
2020-10-09 13:06:33 +02:00
Roman Lebedev
87cbbfcf0e [NFC][SCEV] Improve tests for ptrtoint modelling (D88806) 2020-10-09 13:50:30 +03:00
Esme-Yi
725cbaf080 [DAGCombiner] Add decomposition patterns for Mul-by-Imm.
Summary: This patch is derived from D87384.
In this patch we expand the existing decomposition of mul-by-constant to be more general by implementing 2 patterns:
```
  mul x, (2^N + 2^M) --> (add (shl x, N), (shl x, M))
  mul x, (2^N - 2^M) --> (sub (shl x, N), (shl x, M))
```
The conversion will be trigged if the multiplier is a big constant that the target can't use a single multiplication instruction to handle. This is controlled by the hook `decomposeMulByConstant`.
More over, the conversion benefits from an ILP improvement since the instructions are independent. A case with the sequence like following also gets benefit since a shift instruction is saved.

```
*res1 = a * 0x8800;
*res2 = a * 0x8080;
```

Reviewed By: spatel

Differential Revision: https://reviews.llvm.org/D88201
2020-10-09 08:51:40 +00:00
Georgii Rymar
47f4e42b78 [llvm-readelf/obj][test] - Stop using precompiled binary in mips-plt.test
This removes the precompiled binary and rewrites test to use YAML.

After this change we'll have no more precompiled inputs in `llvm-readobj/ELF/Inputs`.

Differential revision: https://reviews.llvm.org/D89097
2020-10-09 11:48:49 +03:00
Bevin Hansson
ad6d96ea4f [Fixed Point] Add floating point methods to APFixedPoint.
This adds methods to APFixedPoint for converting to and from
floating point values.

Differential Revision: https://reviews.llvm.org/D85961
2020-10-09 10:27:42 +02:00
Bevin Hansson
5f5f4fe543 [IR] Add Type::getFloatingPointTy.
It is possible to get a fltSemantics of a particular Type,
but there is no way to produce a Type based on a
fltSemantics.

This adds the function Type::getFloatingPointTy, which
will return the appropriate floating point Type for a given
fltSemantics.

ConstantFP is modified to use this function instead of
implementing it itself. Also some minor refactors to use
Type::getFltSemantics instead of a hand-rolled version.

Differential Revision: https://reviews.llvm.org/D87512
2020-10-09 10:27:41 +02:00
Fangrui Song
5611055efa [MCRegister] Simplify isStackSlot & isPhysicalRegister and delete isPhysical. NFC 2020-10-08 22:08:33 -07:00
Fangrui Song
ff30c5884e Fix incorect Register -> MCRegister conversion
getReg returns a Register which may represent a virtual register.
2020-10-08 21:40:48 -07:00
Xing GUO
dd75275a41 [llvm-dwarfdump][test] Rewrite verify_die_ranges.s in YAML. NFC.
This patch rewrites test case verify_die_ranges.s in YAML which helps
simplify the test.

Reviewed By: jhenderson, JDevlieghere, dblaikie

Differential Revision: https://reviews.llvm.org/D88200
2020-10-09 11:13:10 +08:00
Xing GUO
960c301574 [DWARFYAML] Make the opcode_base and the standard_opcode_lengths fields optional.
This patch makes the opcode_base and the standard_opcode_lengths fields
of the line table optional. When both of them are not specified,
yaml2obj emits them according to the line table's version.

Reviewed By: jhenderson

Differential Revision: https://reviews.llvm.org/D88355
2020-10-09 11:10:03 +08:00
Kazushi (Jam) Marukawa
9d098730c5 [VE] Add new MVT types for NEC SX Aurora VE vector
This patch adds entries for:
    v64i64
    v128i64
    v256i64
    v64f64
    v128f64
    v256f64

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D88776
2020-10-09 12:07:41 +09:00
Kai Luo
dac99baf5d [TwoAddressInstruction][PowerPC] Call regOverlapsSet to find out real clobbers and uses
In `rescheduleKillAboveMI`, current implementation uses `SmallSet` to track reg's defs and uses. When comparing, use `SmallSet.count` to find out if it's clobbered or used. It's not correct if involving subregisters. This patch uses `regOverlapsSet` already used by `rescheduleMIBelowKill` to fix the issue.

Fixed https://bugs.llvm.org/show_bug.cgi?id=47707.

Reviewed By: #powerpc, nemanjai

Differential Revision: https://reviews.llvm.org/D88716
2020-10-09 02:34:54 +00:00
Esme-Yi
fb349c0fba [NFC][PowerPC] Supplement test cases for D88274. 2020-10-09 02:32:05 +00:00
QingShan Zhang
0ba32a4447 [NFC][Test] Update the test with update_llc_test_checks.py 2020-10-09 02:26:03 +00:00
Kai Luo
6b4d4c8ee7 [PowerPC] Add RUN line for powerpc 32-bit. NFC. 2020-10-09 00:29:01 +00:00
Austin Kerbow
ae3d83e89b [AMDGPU] Fix mai hazard VALU to LD/ST
Fixes: SWDEV-251863

Differential Revision: https://reviews.llvm.org/D89079
2020-10-08 17:13:02 -07:00
Yuanfang Chen
6d12c0842b [NFC] Fix a comment in MachinePassManager.h
Fix "warning: '\returns' command used in a comment that is not attached
to a function or method declaration [-Wdocumentation]
1 warning generated."
2020-10-08 15:38:57 -07:00
Fangrui Song
c199a61ffa [X86] Fix some clang-tidy bugprone-argument-comment issues 2020-10-08 15:26:50 -07:00
Mircea Trofin
074f58db6d [NFC][MC] MCRegister API typing.
Mostly LiveIntervals, with their effects (users).

Differential Revision: https://reviews.llvm.org/D89018
2020-10-08 15:08:34 -07:00
Simon Pilgrim
8f93933775 [InstCombine] visitTrunc - trunc(shl(X, C)) --> shl(trunc(X),trunc(C)) vector support
Annoyingly vectors aren't supported by shouldChangeType(), but we have precedents for always performing this on vector types (e.g. narrowBinOp).

Differential Revision: https://reviews.llvm.org/D89067
2020-10-08 22:07:51 +01:00
Quentin Colombet
32690c693f [GlobalISel] Add missing pass dependencies for IRTranslator
The IRTranslator depends on the branch probability info pass when the
optimization level is different than None and it depends all the time on
the StackProtector pass.

We have to explicitly call out pass dependencies otherwise the pass manager
may not be able to schedule the IRTranslator.

Before this patch, we were lucky because previous passes depend on the branch
probability info pass (like the Global Variable Optimization) and the stack
protector pass is initialized in initializeCodeGen.
However, if the target has a custom pipeline without any passes like Global
Variable Optimization, the pipeline creation will fail, at least because of
the branch probability info pass dependency (it is unlikely that
initializeCodeGen is not called).

This patch adds the missing dependencies to the IRTranslator.

Differential Revision: https://reviews.llvm.org/D89063
2020-10-08 13:57:21 -07:00
Simon Pilgrim
a0c0bac22a [InstCombine] Add additional trunc(shl(x,c)) -> shl(trunc(x),trunc(c)) vector tests 2020-10-08 21:11:48 +01:00
Sanjay Patel
43799dbe92 [InstCombine] allow vector splats for add+xor with low-mask
This can be allowed with undef elements too, but that can be another step:
https://alive2.llvm.org/ce/z/hnC4Z-
2020-10-08 15:53:38 -04:00
Simon Pilgrim
405a6508c3 [Transforms] visitCmpBlock - don't dereference a dyn_cast<>. NFCI.
Use cast<> as we immediately dereference the pointer afterwards - cast<> will assert if we fail.

Prevents clang static analyzer warning that we could deference a null pointer.
2020-10-08 20:18:32 +01:00
Sanjay Patel
75c88e4411 [InstCombine] remove unnecessary one-use check from add-xor transform
Pre-conditions seem to be optimal, but we don't need a use check
because we are only replacing an add with a sub.

https://rise4fun.com/Alive/hzN

  Pre: (~C1 | C2 == -1) && isPowerOf2(C2+1)
  %m = and i8 %x, C1
  %f = xor i8 %m, C2
  %r = add i8 %f, C3
  =>
  %r = sub i8 C2 + C3, %m
2020-10-08 15:08:51 -04:00
Sanjay Patel
5f6285202c [InstCombine] add tests for add-xor; NFC 2020-10-08 15:08:51 -04:00
Simon Pilgrim
2c22c76b35 [SLP] optimizeGatherSequence - assert every Instruction in the worklist is non-null.
Fixes clang static analyzer warning.
2020-10-08 20:02:18 +01:00
Heejin Ahn
5493d37e90 [WebAssembly] Handle indirect uses of longjmp
In LowerEmscriptenEHSjLj, `longjmp` used to be replaced with
`emscripten_longjmp_jmpbuf(jmp_buf*, i32)`, which will eventually be
lowered to `emscripten_longjmp(i32, i32)`. The reason we used two
different names was because they had different signatures in the IR
pass.

D88697 fixed this by only using `emscripten_longjmp(i32, i32)` and
adding a `ptrtoint` cast to its first argument, so
```
longjmp(buf, 0)
```
becomes
```
emscripten_longjmp((i32)buf, 0)
```

But this assumed all uses of `longjmp` was a direct call to it, which
was not the case. This patch handles indirect uses of `longjmp` by
replacing
```
longjmp
```
with
```
(i32(*)(jmp_buf*, i32))emscripten_longjmp
```

Reviewed By: tlively

Differential Revision: https://reviews.llvm.org/D89032
2020-10-08 11:37:19 -07:00
Quentin Colombet
a8adfce70f [KnownBits] Add a sextOrTrunc method
We already offer zextOrTrunc and it seems natural to offer the
same capability for sign extension.

This patch is a preparatory addition useful for future computeKnownBits
developments.

Differential Revision: https://reviews.llvm.org/D88937
2020-10-08 11:33:06 -07:00
Quentin Colombet
f285fa2832 [KnownBits] Add a computeForMul method
This patch refactors the logic in ValueTracking.cpp so that
computeKnownBitsForMul now uses a helper function from KnownBits.

NFC

Differential Revision: https://reviews.llvm.org/D88935
2020-10-08 11:33:06 -07:00
Quentin Colombet
9a66924cac [unittests] Add a few tests for computeKnownBits with ranges
These tests make sure that the range information is properly
understood during computeKnownBits analysis.

NFC

Differential Revision: https://reviews.llvm.org/D88934
2020-10-08 11:33:06 -07:00
Rahman Lavaee
194be1c7dd Introduce and use a new section type for the bb_addr_map section.
This patch lets the bb_addr_map (renamed to __llvm_bb_addr_map) section use a special section type (SHT_LLVM_BB_ADDR_MAP) instead of SHT_PROGBITS. This would help parsers, dumpers and other tools to use the sh_type ELF field to identify this section rather than relying on string comparison on the section name.

Reviewed By: jhenderson

Differential Revision: https://reviews.llvm.org/D88199
2020-10-08 11:13:19 -07:00
Simon Pilgrim
dacb3eca7f [Transforms] CodeExtractor::verifyAssumptionCache - don't dereference a dyn_cast<>. NFCI.
Use cast<> as we immediately dereference the pointer afterwards - cast<> will assert if we fail.

Prevents clang static analyzer warning that we could deference a null pointer.
2020-10-08 19:04:30 +01:00
Simon Pilgrim
f9f63fa563 [Analysis] ScalarEvolution::getUMinFromMismatchedTypes - assert we've found the max type. NFCI.
Found by clang static analyzer.
2020-10-08 19:04:29 +01:00
Simon Pilgrim
63f335044d [AVR] Fix null dereference warning. NFCI.
We were checking if the ConstantSDNode was null but then immediately dereferencing it afterward - fold these both into a single check. Use the APInt::ult() helper as well.

Found by clang static analyzer.
2020-10-08 19:04:29 +01:00
Joseph Huber
92d68263b1 [OpenMP] Replace OpenMP RTL Functions With OMPIRBuilder and OMPKinds.def
Summary:
Replace the OpenMP Runtime Library functions used in CGOpenMPRuntimeGPU
for OpenMP device code generation with ones in OMPKinds.def and use
OMPIRBuilder for generating runtime calls. This allows us to
consolidate more OpenMP code generation into the OMPIRBuilder. Future
additions to the GPU runtime functions should now go in OMPKinds.def

Reviewers: jdoerfert

Subscribers: aaron.ballman cfe-commits guansong llvm-commits sstefan1 yaxunl

Tags: #OpenMP #LLVM #clang

Differential Revision: https://reviews.llvm.org/D88430
2020-10-08 14:00:22 -04:00
Dan Liew
a50a440b7c [lit] Try to remove the flakeyness of shtest-timeout.py and googletest-timeout.py.
The tests previously relied on the `short.py` and `FirstTest.subTestA`
script being executed on a machine within a short time window (1 or 2
seconds). While this "seems to work" it can fail on resource constrained
machines. We could bump the timeout a little bit (bumping it too
much would mean the test would take a long time to execute) but it wouldn't
really solve the problem of the test being prone to failures.

This patch tries to remove this flakeyness by separating testing into
two separate parts:

1. Testing if a test can hit a timeout.
2. Testing if a test can run to completion in the presence of a
timeout.

This way we can give (1.) a really short timeout (to make the test run
as fast as possible) and (2.) a really long timeout. This means for (2.)
we are no longer trying to rely on the "short" test executing within
some short time window. Instead the window is now 3600 seconds which
should be long enough even for a heavily resource constrained machine to
execute the "short" test.

Thanks to Julian Lettner for suggesting this approach. This superseeds
my original approach in https://reviews.llvm.org/D88807.

This patch also changes the command line override test to run the quick
test rather than the slow one to make the test run faster.

Differential Revision: https://reviews.llvm.org/D89020
2020-10-08 10:46:18 -07:00
Amara Emerson
bbd25a9a88 [GlobalISel] Add G_VECREDUCE_* opcodes for vector reductions.
These mirror the IR and SelectionDAG intrinsics & nodes.

Opcodes added:
G_VECREDUCE_SEQ_FADD
G_VECREDUCE_SEQ_FMUL
G_VECREDUCE_FADD
G_VECREDUCE_FMUL
G_VECREDUCE_FMAX
G_VECREDUCE_FMIN
G_VECREDUCE_ADD
G_VECREDUCE_MUL
G_VECREDUCE_AND
G_VECREDUCE_OR
G_VECREDUCE_XOR
G_VECREDUCE_SMAX
G_VECREDUCE_SMIN
G_VECREDUCE_UMAX
G_VECREDUCE_UMIN

Differential Revision: https://reviews.llvm.org/D88750
2020-10-08 10:33:19 -07:00
Sanjay Patel
43cd7a3a13 [InstCombine] allow vector splats for add+xor with signmask 2020-10-08 10:46:34 -04:00
Sanjay Patel
2ffd36d959 [InstCombine] add vector splat tests for add of signmask; NFC 2020-10-08 10:46:33 -04:00
Jay Foad
9cb53ff372 [AMDGPU] Add patterns for mad/mac legacy f32 instructions
Note that all subtargets up to GFX10.1 have v_mad_legacy_f32, but GFX8/9
lack v_mac_legacy_f32. GFX10.3 has no mad/mac f32 instructions at all.

Differential Revision: https://reviews.llvm.org/D88890
2020-10-08 15:20:06 +01:00
Nico Weber
385deec198 [gn build] (manually) port 9b58b0c06e6 better 2020-10-08 10:13:54 -04:00
Nico Weber
aaecbeabb4 [gn build] (manually) port 9b58b0c06e6 2020-10-08 10:08:45 -04:00
diggerlin
ad439cc870 [AIX] add new option -mignore-xcoff-visibility
SUMMARY:

In IBM compiler xlclang , there is an option -fnovisibility which suppresses visibility. For more details see: https://www.ibm.com/support/knowledgecenter/SSGH3R_16.1.0/com.ibm.xlcpp161.aix.doc/compiler_ref/opt_visibility.html.

We need to add the option -mignore-xcoff-visibility for compatibility with the IBM AIX OS (as the option is enabled by default in AIX). With this option llvm does not emit any visibility attribute to ASM or XCOFF object file.

The option only work on the AIX OS, for other non-AIX OS using the option will report an unsupported options error.

In AIX OS:

1.1  the option -mignore-xcoff-visibility is enabled by default , if there is not -fvisibility=* and -mignore-xcoff-visibility explicitly in the clang command .

1.2 if there is -fvisibility=* explicitly but not -mignore-xcoff-visibility  explicitly in the clang command.  it will generate visibility attributes.

1.3 if there are  both  -fvisibility=* and  -mignore-xcoff-visibility  explicitly in the clang command. The option  "-mignore-xcoff-visibility" wins , it do not emit the visibility attribute.

The option -mignore-xcoff-visibility has no effect on visibility attribute when compile with -emit-llvm option to generated LLVM IR.

Reviewer: daltenty,Jason Liu

Differential Revision: https://reviews.llvm.org/D87451
2020-10-08 09:34:58 -04:00
Georgii Rymar
2637660f2c [llvm-readobj] - Fix possible crashes related to dumping gnu hash symbols.
It fixes possible scenarios when we crash/assert with `--hash-symbols` when
dumping an invalid GNU hash table which has a broken value in the buckets array.

This fixes a crash reported in comments for
https://bugs.llvm.org/show_bug.cgi?id=47681

Differential revision: https://reviews.llvm.org/D88561
2020-10-08 16:21:56 +03:00
Sebastian Neubauer
e32da025fd [AMDGPU] Use isLegalMUBUFImmOffset more
Instead of hardcoding isUInt<12>.

Differential Revision: https://reviews.llvm.org/D88961
2020-10-08 14:31:44 +02:00
Simon Pilgrim
86361d772e [InstCombine] matchFunnelShift - support non-uniform constant vector shift amounts (PR46895)
Complete basic PR46895 fixes by refactoring D87452/D88402 to allow us to match non-uniform constant values.

We still don't handle non-uniform vectors that contain undef elements, but that can wait until we have a decent generic mechanism for this.

Differential Revision: https://reviews.llvm.org/D88420
2020-10-08 12:56:27 +01:00
Markus Lavin
ad940d62c6 [DebugInfo] Improve dbg preservation in LSR.
Use SCEV to salvage additional @llvm.dbg.value that have turned into
referencing undef after transformation (and traditional
salvageDebugInfo). Before transformation compute SCEV for each
@llvm.dbg.value in the loop body and store it (along side its current
DIExpression). After transformation update those @llvm.dbg.value now
referencing undef by comparing its stored SCEV to the SCEV of the
current loop-header PHI-nodes. Allow match with offset by inserting
compensation code in the DIExpression.

Includes fix for the nullptr deref that caused the original commit
to be reverted in 9d63029770.

Fixes : PR38815

Differential Revision: https://reviews.llvm.org/D87494
2020-10-08 13:16:43 +02:00
Dmitry Preobrazhensky
973a031f69 [AMDGPU][MC][GFX1030] Disabled v_mac_f32
See bug 47741 <https://bugs.llvm.org/show_bug.cgi?id=47741>

Reviewers: nhaehnle, rampitec

Differential Revision: https://reviews.llvm.org/D89000
2020-10-08 14:00:52 +03:00