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Author SHA1 Message Date
Chris Lattner
cdefc1c441 add the ability for TargetData to return information about legal integer 
datatypes on a given CPU.  This is intended to allow instcombine and other
transformations to avoid converting big sequences of operations to an
inconvenient width, and will help clean up after SRoA.  See also "Adding 
legal integer sizes to TargetData" on Feb 1, 2009 on llvmdev, and PR3451.

Comments welcome.

llvm-svn: 86370
 2009-11-07 09:35:34 +00:00
Chris Lattner
f99bf8cb76 more cleanup. 
llvm-svn: 86369
 2009-11-07 09:23:04 +00:00
Chris Lattner
8abcfed7c7 add some missing #includes 
llvm-svn: 86367
 2009-11-07 09:20:54 +00:00
Chris Lattner
d3f71f2a61 rewrite TargetData to use StringRef/raw_ostream instead of thrashing std::strings. 
llvm-svn: 86366
 2009-11-07 09:13:23 +00:00
Jeffrey Yasskin
502d93267d Make the need-stub variables accurate and consistent. In the case of 
MachineRelocations, "stub" always refers to a far-call stub or a
load-a-faraway-global stub, so this patch adds "Far" to the term. (Other stubs
are used for lazy compilation and dlsym address replacement.) The variable was
also inconsistent between the positive and negative sense, and the positive
sense ("NeedStub") was more demanding than is accurate (since a nearby-enough
function can be called directly even if the platform often requires a stub).
Since the negative sense causes double-negatives, I switched to
"MayNeedFarStub" globally.

llvm-svn: 86363
 2009-11-07 08:51:52 +00:00
Eric Christopher
c5bcc1db29 Fix a couple of shuffle patterns to use movhlps instead 
of movhps as the constraint.  Changes optimizations so
update testcases as appropriate as well.

llvm-svn: 86360
 2009-11-07 08:45:53 +00:00
Mon P Wang
c01eb38a3b Fixed Overload table bug noticed by Jakob 
llvm-svn: 86332
 2009-11-07 04:07:33 +00:00
Evan Cheng
899d8cb6a0 Refactor code. Fix a potential missing check. Teach isIdentical() about tLDRpci_pic. 
llvm-svn: 86330
 2009-11-07 04:04:34 +00:00
Evan Cheng
8eaaffb9da - Add TargetInstrInfo::isIdentical(). It's similar to MachineInstr::isIdentical 
except it doesn't care if the definitions' virtual registers differ. This is
  used by machine LICM and other MI passes to perform CSE.
- Teach Thumb2InstrInfo::isIdentical() to check two t2LDRpci_pic are identical.
  Since pc relative constantpool entries are always different, this requires it
  it check if the values can actually the same.

llvm-svn: 86328
 2009-11-07 03:52:02 +00:00
Ted Kremenek
f8905e9718 Update CMake file. 
llvm-svn: 86325
 2009-11-07 03:26:59 +00:00
Kenneth Uildriks
91ceaa85a2 Add code to check at SelectionDAGISel::LowerArguments time to see if return values can be lowered to registers. Coming soon, code to perform sret-demotion if return values cannot be lowered to registers 
llvm-svn: 86324
 2009-11-07 02:11:54 +00:00
Johnny Chen
5158450544 My previous patch (r84124) for setting the encoding bits 4 and 7 of DPSoRegFrm 
was wrong and too aggressive in the sense that DPSoRegFrm includes both constant
shifts (with Inst{4} = 0) and register controlled shifts (with Inst{4} = 1 and
Inst{7} = 0).  The 'rr' fragment of the multiclass definitions actually means
register/register with no shift, see A8-11.

llvm-svn: 86319
 2009-11-07 00:54:36 +00:00
Jim Grosbach
71c5411651 80-columns 
llvm-svn: 86310
 2009-11-07 00:13:30 +00:00
Evan Cheng
6e3e66375a - Add pseudo instructions tLDRpci_pic and t2LDRpci_pic which does a pc-relative 
load of a GV from constantpool and then add pc. It allows the code sequence to
  be rematerializable so it would be hoisted by machine licm.
- Add a late pass to break these pseudo instructions into a number of real
  instructions. Also move the code in Thumb2 IT pass that breaks up t2MOVi32imm
  to this pass. This is done before post regalloc scheduling to allow the
  scheduler to proper schedule these instructions. It also allow them to be
  if-converted and shrunk by later passes.

llvm-svn: 86304
 2009-11-06 23:52:48 +00:00
Anton Korobeynikov
dca40933ee Honour subreg machine operands during asmprinting 
llvm-svn: 86303
 2009-11-06 23:45:15 +00:00
Bob Wilson
e79354a831 Print VMOV (immediate) operands as hexadecimal values. Apple's assembler 
will not accept negative values for these.  LLVM's default operand printing
sign extends values, so that valid unsigned values appear as negative
immediates.  Print all VMOV immediate operands as hex values to resolve this.
Radar 7372576.

llvm-svn: 86301
 2009-11-06 23:33:28 +00:00
Evan Cheng
aaf30ce699 Remove ARMPCLabelIndex from ARMISelLowering. Use ARMFunctionInfo::createConstPoolEntryUId() instead. 
llvm-svn: 86294
 2009-11-06 22:24:13 +00:00
Daniel Dunbar
4daaf9d3f4 Pass StringRef by value. 
llvm-svn: 86251
 2009-11-06 10:58:06 +00:00
Dan Gohman
ada358e6a2 Factor out the printing of the leading tab into printInlineAsm. 
llvm-svn: 86199
 2009-11-06 00:04:54 +00:00
Dan Gohman
1a8616a0d7 Use SUBREG_TO_REG instead of INSERT_SUBREG to model x86-64's 
implicit zero-extend.

llvm-svn: 86196
 2009-11-05 23:53:08 +00:00
Dan Gohman
eec0f1c506 Remove uninteresting and confusing debug output. 
llvm-svn: 86149
 2009-11-05 18:47:09 +00:00
Chris Lattner
7f61fbfcca add a note from PR5313 
llvm-svn: 86146
 2009-11-05 18:19:19 +00:00
Mon P Wang
0669a8df22 Reintroduce support for overloading target intrinsics 
llvm-svn: 86114
 2009-11-05 03:19:08 +00:00
Jim Grosbach
ef37391033 Grammar. 
llvm-svn: 86068
 2009-11-04 23:20:40 +00:00
Jim Grosbach
2867641b64 Now that the memory leak from McCat/08-main has been fixed (86056), re-enable 
aggressive testing of dynamic stack alignment.
Note that this is off by default, and enabled for LLCBETA nightly results.

llvm-svn: 86064
 2009-11-04 23:11:07 +00:00
Jim Grosbach
c0cabc9119 If a function has no stack frame at all, dynamic realignment isn't necessary. 
llvm-svn: 86057
 2009-11-04 22:41:51 +00:00
Jim Grosbach
c8a01556f4 dynamic stack realignment necessitates scanning the floating point callee- 
saved instructions even if no stack adjustment for those saves is needed.

llvm-svn: 86056
 2009-11-04 22:41:00 +00:00
Bob Wilson
25738f9e79 Add PowerPC codegen for indirect branches. 
llvm-svn: 86050
 2009-11-04 21:31:18 +00:00
Jakob Stoklund Olesen
f775e222e0 Print out an informative comment for KILL instructions. 
The KILL pseudo-instruction may survive to the asm printer pass, just like the IMPLICIT_DEF. Print the KILL as a comment instead of just leaving a blank line in the output.

With -asm-verbose=0, a blank line is printed, like IMPLICIT?DEF.

llvm-svn: 86041
 2009-11-04 19:24:37 +00:00
Evan Cheng
22121f4c69 The .n suffix must go after the predicate. 
llvm-svn: 86019
 2009-11-04 07:38:48 +00:00
Evan Cheng
1a06b12330 Use ldr.n to workaround a darwin assembler bug. 
llvm-svn: 85980
 2009-11-04 00:00:39 +00:00
Evan Cheng
b50510c510 Fix t2Int_eh_sjlj_setjmp. Immediate form of orr is a 32-bit instruction. So it should be 22 bytes instead of 20 bytes long. 
llvm-svn: 85965
 2009-11-03 23:13:34 +00:00
Evan Cheng
caab17007b fconsts / fconstd immediate should be proceeded with #. 
llvm-svn: 85952
 2009-11-03 21:59:33 +00:00
Anton Korobeynikov
de7cbab064 Move subtarget check upper for NEON reg-reg fixup pass. 
llvm-svn: 85914
 2009-11-03 18:46:11 +00:00
Evan Cheng
1d4575274c Trim unnecessary include. 
llvm-svn: 85878
 2009-11-03 07:08:08 +00:00
Bob Wilson
97331f70ca For Thumb indirect branches, use "mov pc, reg" which does not switch 
between ARM/Thumb modes and does not require the low bit of the target
address to be set for Thumb.

llvm-svn: 85874
 2009-11-03 06:29:56 +00:00
Evan Cheng
ed22395c61 Fix PR5367. QPR_8 is the super regclass of DPR_8 and SPR_8. 
llvm-svn: 85871
 2009-11-03 05:52:54 +00:00
Evan Cheng
2807af42c0 Clean up copyRegToReg. 
llvm-svn: 85870
 2009-11-03 05:51:39 +00:00
Evan Cheng
9bedf1b587 Add QPR_8 as a superreg class of SPR_8 and DPR_8. 
llvm-svn: 85869
 2009-11-03 05:50:57 +00:00
Ted Kremenek
a474928cda Update CMake file. 
llvm-svn: 85861
 2009-11-03 04:14:12 +00:00
Anton Korobeynikov
ff29071cc6 Turn neon reg-reg moves fixup code into separate pass. This should reduce the compile time. 
llvm-svn: 85850
 2009-11-03 01:04:26 +00:00
Anton Korobeynikov
48b30c79be Revert r85049, it is causing PR5367 
llvm-svn: 85847
 2009-11-03 00:24:48 +00:00
Bob Wilson
7e071e14eb Revert previous change to a comment. The BlockAddresses go in the 
constant pool so they don't get wrapped separately.

llvm-svn: 85844
 2009-11-03 00:02:05 +00:00
Bob Wilson
3144715b53 Put BlockAddresses into ARM constant pools. 
llvm-svn: 85824
 2009-11-02 20:59:23 +00:00
Kevin Enderby
633b294095 Fix ARMAsmParser::ParseMemoryOffsetReg() where the parameter OffsetRegNum should 
have been passed as a reference.

llvm-svn: 85823
 2009-11-02 20:14:39 +00:00
David Goodwin
9aa890eab6 Fix schedule model for BFC. 
llvm-svn: 85809
 2009-11-02 17:28:36 +00:00
Bob Wilson
0c213bed8b Hyphenate some comments. 
llvm-svn: 85808
 2009-11-02 17:10:37 +00:00
Bob Wilson
6eb4f53d90 Add support for BlockAddress values in ARM constant pools. 
llvm-svn: 85806
 2009-11-02 16:59:06 +00:00
Bob Wilson
ac53e0c640 Prune unnecessary include. 
llvm-svn: 85805
 2009-11-02 16:58:31 +00:00
Evan Cheng
e79ff8a615 These are done / no longer care. 
llvm-svn: 85798
 2009-11-02 07:58:25 +00:00
Evan Cheng
532dfd431f Add an entry. 
llvm-svn: 85797
 2009-11-02 07:51:19 +00:00
Evan Cheng
57f7c7c914 Unbreak ARMBaseRegisterInfo::copyRegToReg. 
llvm-svn: 85787
 2009-11-02 04:44:55 +00:00
Anton Korobeynikov
09147da530 Handle splats of undefs properly. This includes the testcase for PR5364 as well. 
llvm-svn: 85767
 2009-11-02 00:12:06 +00:00
Anton Korobeynikov
9737bfedeb Do not infer the target type for COPY_TO_REGCLASS from dest regclass, this won't work if it can contain several types. Require explicit result type for the node for now. This fixes PR5364. 
PS: It seems that blackfin usage of copy_to_regclass is completely bogus!
llvm-svn: 85766
 2009-11-02 00:11:39 +00:00
Anton Korobeynikov
ed410a8ee3 64-bit FP loads & stores operate on both NEON and VFP pipelines. 
llvm-svn: 85765
 2009-11-02 00:11:06 +00:00
Anton Korobeynikov
3ba3789153 Use NEON reg-reg moves, where profitable. This reduces "domain-cross" stalls, when we used to mix vfp and neon code (the former were used for reg-reg moves) 
llvm-svn: 85764
 2009-11-02 00:10:38 +00:00
Evan Cheng
a409c074c8 Fix a couple more places where we are creating ld / st instructions without memoperands. 
llvm-svn: 85746
 2009-11-01 22:04:35 +00:00
Evan Cheng
4a0d47f209 Make use of imm12 version of Thumb2 ldr / str instructions more aggressively. 
llvm-svn: 85743
 2009-11-01 21:12:51 +00:00
Chris Lattner
4cf2980e59 improve x86 codegen support for blockaddress. We now compile 
the testcase into:

_test1:                                                     ## @test1
## BB#0:                                                    ## %entry
	leaq	L_test1_bb6(%rip), %rax
	jmpq	*%rax
L_test1_bb:                                                 ## Address Taken
LBB1_1:                                                     ## %bb
	movb	$1, %al
	ret
L_test1_bb6:                                                ## Address Taken
LBB1_2:                                                     ## %bb6
	movb	$2, %al
	ret

Note, it is very very strange that BlockAddressSDNode doesn't carry 
around TargetFlags.  Dan, please fix this.

llvm-svn: 85703
 2009-11-01 03:25:03 +00:00
Evan Cheng
de16fff3e8 Use cbz and cbnz instructions. 
llvm-svn: 85698
 2009-10-31 23:46:45 +00:00
Jim Grosbach
5b094f3b36 vml[as].f32 cause stalls in following advanced SIMD instructions. Avoid using 
them for scalar floating point operations for now.

llvm-svn: 85697
 2009-10-31 22:57:36 +00:00
Jim Grosbach
ace75c4288 Expand 64-bit logical shift right inline 
llvm-svn: 85687
 2009-10-31 21:42:19 +00:00
Jim Grosbach
16ae289667 Expand 64-bit arithmetic shift right inline 
llvm-svn: 85685
 2009-10-31 21:00:56 +00:00
Jim Grosbach
534d2cb249 Expand 64 bit left shift inline rather than using the libcall. For now, this 
is unconditional. Making it still use the libcall when optimizing for size
would be a good adjustment.

llvm-svn: 85675
 2009-10-31 19:38:01 +00:00
Evan Cheng
9178904e56 It's safe to remat t2LDRpci; Add PseudoSourceValue to load / store's to enable more machine licm. More changes coming. 
llvm-svn: 85643
 2009-10-31 03:39:36 +00:00
Kevin Enderby
c8d047130a Updates to the ARM target assembler for llvm-mc per review comments from 
Daniel Dunbar.
- Reordered the fields in the ARMOperand Mem struct to make the struct smaller.
Making bool's into 1 bit fields and put the MCExpr* fields adjacent to each
other.
- Fixed a number of places in ARMAsmParser.cpp so they have doxygen comments.
- Change the name of ARMAsmParser::ParseRegister() to MaybeParseRegister and
added the bool ParseWriteBack parameter.
- Changed ARMAsmParser::ParseMemory() to call MaybeParseRegister().
- Added ARMAsmParser::ParseMemoryOffsetReg to factor out parsing the offset of a
memory operand.  And use it for both parsing both preindexed and post indexing
addressing forms in ARMAsmParser::ParseMemory.
- Changed the first argument to ParseShift() to a reference.
- Changed ParseShift() to check for Rrx first and return to reduce nesting.

llvm-svn: 85632
 2009-10-30 22:55:57 +00:00
Bob Wilson
1c2cbe3945 Add a note about Robert Muth's alternate jump table implementation. 
llvm-svn: 85624
 2009-10-30 22:22:46 +00:00
Dan Gohman
ad6c6a3d33 Fix MachineLICM to use the correct virtual register class when 
unfolding loads for hoisting.  getOpcodeAfterMemoryUnfold returns the
opcode of the original operation without the load, not the load
itself, MachineLICM needs to know the operand index in order to get
the correct register class. Extend getOpcodeAfterMemoryUnfold to
return this information.

llvm-svn: 85622
 2009-10-30 22:18:41 +00:00
Bob Wilson
94d79c1f43 Fix a comment. 
llvm-svn: 85610
 2009-10-30 20:13:25 +00:00
Rafael Espindola
d4fadd76da This fixes functions like 
void f (int a1, int a2, int a3, int a4, int a5,...)

In ARMTargetLowering::LowerFormalArguments if the function has 4 or
more regular arguments we used to set VarArgsFrameIndex using an
offset of 0, which is only correct if the function has exactly 4
regular arguments.

llvm-svn: 85590
 2009-10-30 14:33:14 +00:00
Bob Wilson
95064e348a Add ARM codegen for indirect branches. 
clang/test/CodeGen/indirect-goto.c runs! (unoptimized)

llvm-svn: 85577
 2009-10-30 05:45:42 +00:00
Dan Gohman
2767aa065e Initial x86 support for BlockAddresses. 
llvm-svn: 85557
 2009-10-30 01:28:02 +00:00
Jim Grosbach
95e1ff2dba Dial back the realignment a bit. 
llvm-svn: 85546
 2009-10-30 00:08:40 +00:00
Dan Gohman
3393a4c997 Rename usesCustomDAGSchedInserter to usesCustomInserter, and update a 
bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.

llvm-svn: 85517
 2009-10-29 18:10:34 +00:00
Jim Grosbach
071b4ec891 To get more thorough testing from llc-beta nightly runs, do dynamic stack 
realignment regardless of whether it's strictly necessary.

llvm-svn: 85476
 2009-10-29 02:41:21 +00:00
Bob Wilson
fc1194919b Revert r85346 change to control tail merging by CodeGenOpt::Level. 
I'm going to redo this using the OptimizeForSize function attribute.

llvm-svn: 85426
 2009-10-28 20:46:46 +00:00
Bob Wilson
af37728221 Add a Thumb BRIND pattern. Change the ARM BRIND assembly to separate the 
opcode and operand with a tab.  Check for these instructions in the usual
places.

llvm-svn: 85411
 2009-10-28 18:26:41 +00:00
Evan Cheng
519b231883 fconsts and fconstd are obviously re-materializable. 
llvm-svn: 85410
 2009-10-28 18:19:56 +00:00
Jim Grosbach
e42dc83a9f Cleanup now that frame index scavenging via post-pass is working for ARM and Thumb2. 
llvm-svn: 85406
 2009-10-28 17:33:28 +00:00
Evan Cheng
16ed5ac7ff Give ARMISD::EH_SJLJ_LONGJMP and EH_SJLJ_SETJMP names. 
llvm-svn: 85381
 2009-10-28 06:55:03 +00:00
Evan Cheng
5935e48b96 X86 palignr intrinsics immediate field is in bits. ISel must transform it into bytes. 
llvm-svn: 85379
 2009-10-28 06:30:34 +00:00
Chris Lattner
f605b2e8f9 Previously, all operands to Constant were themselves constant. 
In the new world order, BlockAddress can have a BasicBlock operand.
This doesn't permute much, because if you have a ConstantExpr (or
anything more specific than Constant) we still know the operand has
to be a Constant.

llvm-svn: 85375
 2009-10-28 05:14:34 +00:00
Evan Cheng
1babe43881 Use fconsts and fconstd to materialize small fp constants. 
llvm-svn: 85362
 2009-10-28 01:44:26 +00:00
Evan Cheng
4e3bc5efb7 Add a second ValueType argument to isFPImmLegal. 
llvm-svn: 85361
 2009-10-28 01:43:28 +00:00
Dan Gohman
b20fae567f Update SystemZ to use PSW following the way x86 uses EFLAGS. Besides 
eliminating a use of MVT::Flag, this is needed for an upcoming CodeGen
change.

This unfortunately requires SystemZ to switch to the list-burr
scheduler, in order to handle the physreg defs properly, however
that's what LLVM has available at this time.

llvm-svn: 85357
 2009-10-28 00:55:57 +00:00
Bob Wilson
b709aa6b3c Add an indirect branch pattern for ARM. Testcase will be coming soon. 
llvm-svn: 85355
 2009-10-28 00:37:03 +00:00
Chris Lattner
2bc8002f4c rename indbr -> indirectbr to appease the residents of #llvm. 
llvm-svn: 85351
 2009-10-28 00:19:10 +00:00
Bob Wilson
98c9fb94ab Record CodeGen optimization level in the BranchFolding pass so that we can 
use it to control tail merging when there is a tradeoff between performance
and code size.  When there is only 1 instruction in the common tail, we have
been merging.  That can be good for code size but is a definite loss for
performance.  Now we will avoid tail merging in that case when the
optimization level is "Aggressive", i.e., "-O3".  Radar 7338114.

Since the IfConversion pass invokes BranchFolding, it too needs to know
the optimization level.  Note that I removed the RegisterPass instantiation
for IfConversion because it required a default constructor.  If someone
wants to keep that for some reason, we can add a default constructor with
a hard-wired optimization level.

llvm-svn: 85346
 2009-10-27 23:49:38 +00:00
Bill Wendling
8f96a88125 Add new note. 
llvm-svn: 85341
 2009-10-27 23:30:07 +00:00
Jim Grosbach
7c0566a5cc Enable virtual register based frame index scavenging by default for ARM & T2. 
llvm-svn: 85335
 2009-10-27 22:52:29 +00:00
Bill Wendling
cb9a2f20d5 Move and clarify note. 
llvm-svn: 85334
 2009-10-27 22:48:31 +00:00
Jim Grosbach
a6946f0f50 Infrastructure for dynamic stack realignment on ARM. For now, this is off by 
default behind a command line option. This will enable better performance for
vectors on NEON enabled processors.

llvm-svn: 85333
 2009-10-27 22:45:39 +00:00
Bill Wendling
2aaf2ae6e1 Note corrected. 
llvm-svn: 85332
 2009-10-27 22:43:24 +00:00
Bill Wendling
3e4dd02a1e Modify note. 
llvm-svn: 85331
 2009-10-27 22:40:45 +00:00
Bill Wendling
3edf1d3854 Add a note. 
llvm-svn: 85329
 2009-10-27 22:34:43 +00:00
Chris Lattner
34c90ce60d cppbackend support for indbr 
llvm-svn: 85312
 2009-10-27 21:24:48 +00:00
Chris Lattner
f21034d6c3 CBE support for indbr. 
llvm-svn: 85311
 2009-10-27 21:21:06 +00:00
Johnny Chen
b746e248cd Similar to r85280, do not clear the "S" bit for RSBri and RSBrs. 
llvm-svn: 85299
 2009-10-27 20:51:49 +00:00
Johnny Chen
d63b06e0f6 Set condition code bits of BL and BLr9 to 0b1110 (ALways) to distinguish between 
BL_pred and BLr9_pred.

llvm-svn: 85297
 2009-10-27 20:45:15 +00:00
Evan Cheng
151726ad30 Do away with addLegalFPImmediate. Add a target hook isFPImmLegal which returns true if the fp immediate can be natively codegened by target. 
llvm-svn: 85281
 2009-10-27 19:56:55 +00:00
Bob Wilson
5ca76e601f Do not clear the "S" bit for RSCri and RSCrs. They inherit from the "sI" 
instruction format that already takes care of setting this.

llvm-svn: 85280
 2009-10-27 19:52:03 +00:00
Johnny Chen
528c66b30c Explicitly specify 0b00, i.e, zero rotation, as the rotate filed (Inst{11-10}) 
for the r/rr fragment of the multiclass AI_unary_rrot/AI_bin_rrot.

llvm-svn: 85271
 2009-10-27 18:44:24 +00:00
Sanjiv Gupta
c690360ed5 Remove unnecessary gotos to fall-thru successors. 
llvm-svn: 85257
 2009-10-27 17:40:24 +00:00
Johnny Chen
37851c95e8 Test commit. Added '.' to the comment line. 
llvm-svn: 85255
 2009-10-27 17:25:15 +00:00
Chris Lattner
5596e0eb77 apparently the X86 JIT isn't fully contextized, it is still using getGlobalContext() :( 
llvm-svn: 85252
 2009-10-27 17:01:03 +00:00
Rafael Espindola
7eb2a8fb0b Correctly align double arguments in the stack. 
llvm-svn: 85235
 2009-10-27 14:09:44 +00:00
Evan Cheng
032eef9720 Now VFP instructions. 
llvm-svn: 85186
 2009-10-27 00:20:49 +00:00
Evan Cheng
f30e5556ba Change Thumb1 and Thumb2 instructions to separate opcode from operands with a tab instead of a space. 
llvm-svn: 85184
 2009-10-27 00:08:59 +00:00
Evan Cheng
a883c2ebb7 Change ARM asm strings to separate opcode from operands with a tab instead of a space. 
llvm-svn: 85178
 2009-10-26 23:45:59 +00:00
Victor Hernandez
673c036bc7 Remove FreeInst. 
Remove LowerAllocations pass.
Update some more passes to treate free calls just like they were treating FreeInst.

llvm-svn: 85176
 2009-10-26 23:43:48 +00:00
Bob Wilson
5a870f848e Try to get ahead of Johnny Chen and pro-actively add some more ARM encoding 
bits.  Johnny, please review -- I do not have a good track record of getting
these right.

llvm-svn: 85173
 2009-10-26 22:59:12 +00:00
Bob Wilson
ace97183c7 Fix ARM encoding typo: Opcod3 is not passed to ASuI parent class. 
Patch by Johnny Chen.

llvm-svn: 85169
 2009-10-26 22:42:13 +00:00
Bob Wilson
32ee4ee163 Add more ARM instruction encodings for 's' bit set and "rs" register encoding 
bits.  Patch by Johnny Chen.

llvm-svn: 85167
 2009-10-26 22:34:44 +00:00
Ted Kremenek
acb9fe806e Update CMake files. 
llvm-svn: 85161
 2009-10-26 22:06:01 +00:00
Anton Korobeynikov
4f40949874 Revert r85134, it breaks mingw build 
llvm-svn: 85138
 2009-10-26 18:40:24 +00:00
Sanjiv Gupta
7ea628e8db Make PIC16 overlay a loadable pass. 
llvm-svn: 85134
 2009-10-26 18:22:59 +00:00
David Goodwin
f6199e95b0 Break anti-dependence breaking out into its own class. 
llvm-svn: 85127
 2009-10-26 16:59:04 +00:00
Chandler Carruth
766362c707 Move DataTypes.h to include/llvm/System, update all users. This breaks the last 
direct inclusion edge from System to Support.

llvm-svn: 85086
 2009-10-26 01:35:46 +00:00
Jim Grosbach
eae0e509c0 of -> or 
llvm-svn: 85065
 2009-10-25 19:14:48 +00:00
Jim Grosbach
29b842a6c1 80-column cleanup 
llvm-svn: 85064
 2009-10-25 18:55:46 +00:00
Sanjiv Gupta
18574b11b0 Reapply 85006 with a minor fix. 
llvm-svn: 85052
 2009-10-25 08:14:11 +00:00
Evan Cheng
d748ce45ab Add ARM getMatchingSuperRegClass to handle S / D / Q cross regclass coalescing. 
llvm-svn: 85049
 2009-10-25 07:53:28 +00:00
Evan Cheng
77ecc0adc5 Don't forget subreg indices when folding load / store. 
llvm-svn: 85048
 2009-10-25 07:52:27 +00:00
Nick Lewycky
2b8400628d Remove includes of Support/Compiler.h that are no longer needed after the 
VISIBILITY_HIDDEN removal.

llvm-svn: 85043
 2009-10-25 06:57:41 +00:00
Nick Lewycky
711c726c97 Remove VISIBILITY_HIDDEN from class/struct found inside anonymous namespaces. 
Chris claims we should never have visibility_hidden inside any .cpp file but
that's still not true even after this commit.

llvm-svn: 85042
 2009-10-25 06:33:48 +00:00
Chris Lattner
81c06b943c this is done. 
llvm-svn: 85041
 2009-10-25 06:17:51 +00:00
Nick Lewycky
cacdc4d65a Remove ICmpInst::isSignedPredicate which was a reimplementation 
CmpInst::isSigned.

llvm-svn: 85037
 2009-10-25 05:20:17 +00:00
Sanjiv Gupta
ec0d345a46 Revert back 85006 for now as it breaks PIC16 tests. 
llvm-svn: 85008
 2009-10-24 18:19:41 +00:00
Sanjiv Gupta
1fcb847e01 Adding support for placing global objects in shared data memory. 
llvm-svn: 85006
 2009-10-24 18:02:44 +00:00
Evan Cheng
0e5c6b3b69 80 col violation. 
llvm-svn: 84986
 2009-10-24 02:07:42 +00:00
Jim Grosbach
e295e49760 Restrict Thumb1 register allocation to low registers, even for instructions that 
can access the hi regs. Our prologue and epilogue code doesn't know how to
properly handle save/restore of the hi regs, so things go badly when we alloc
them.

llvm-svn: 84982
 2009-10-24 00:19:24 +00:00
Jim Grosbach
5b5a404677 FIXME no longer applies. R12 and R3 are available for allocation 
llvm-svn: 84977
 2009-10-23 23:07:42 +00:00
Chris Lattner
d1dbcae98f some stuff is done, we still have constantexpr simplification to do. 
llvm-svn: 84943
 2009-10-23 07:00:55 +00:00
Evan Cheng
0db11ae5a2 X86 needs critical path anti-dependency breaking. 
llvm-svn: 84931
 2009-10-23 05:57:35 +00:00
David Goodwin
82c1dd9754 Allow the target to select the level of anti-dependence breaking that should be performed by the post-RA scheduler. The default is none. 
llvm-svn: 84911
 2009-10-22 23:19:17 +00:00
Bob Wilson
8f4f73da55 Revert 84843. Evan, this was breaking some of the if-conversion tests. 
llvm-svn: 84868
 2009-10-22 16:52:21 +00:00
Benjamin Kramer
b159c164d2 Shift art to the right to keep GCC from complaining about multi-line comments. 
llvm-svn: 84849
 2009-10-22 09:28:49 +00:00
Evan Cheng
2edd1efa46 Move if-conversion before post-regalloc scheduling so the predicated instruction get scheduled properly. 
llvm-svn: 84843
 2009-10-22 06:48:32 +00:00
Evan Cheng
d411ac1267 Load / store multiple was missing opportunites when the load / store bundles are at the end of the bb. Test case is already in, the bug is exposed by subsequent commit. 
llvm-svn: 84842
 2009-10-22 06:47:35 +00:00
Evan Cheng
0c6aa52214 Trim more includes. 
llvm-svn: 84832
 2009-10-22 05:11:00 +00:00
Evan Cheng
166f455456 Trim include. 
llvm-svn: 84831
 2009-10-22 05:08:49 +00:00
Chris Lattner
e0932e92e9 fix warning. 
llvm-svn: 84826
 2009-10-22 03:42:27 +00:00
Evan Cheng
8fdd1661fa Don't generate sbfx / ubfx with negative lsb field. Patch by David Conrad. 
llvm-svn: 84813
 2009-10-22 00:40:00 +00:00
Anton Korobeynikov
bbc637e96d Use special DAG-to-DAG preprocessing to allow mem-mem instructions to be selected. 
Yay for ASCII graphics!

llvm-svn: 84808
 2009-10-22 00:16:00 +00:00
Jim Grosbach
f79f9afb91 Missing piece of the ARM frame index post-scavenging conditionalization 
llvm-svn: 84798
 2009-10-21 23:40:56 +00:00
Jim Grosbach
363a67d9c5 Conditionalize ARM/T2 frame index post-scavenging while working out fixes 
for a few bugs.

llvm-svn: 84791
 2009-10-21 22:59:24 +00:00
Bob Wilson
26a4580439 Most of the NEON shuffle instructions do not support 64-bit element types. 
llvm-svn: 84785
 2009-10-21 21:36:27 +00:00
Anton Korobeynikov
141a4a2f42 Revert r84764, it breaks mingw build 
llvm-svn: 84783
 2009-10-21 21:15:18 +00:00
Jim Grosbach
452de96b04 Improve handling of immediates by splitting 32-bit immediates into two 16-bit 
immediate operands when they will fit into the using instruction.

llvm-svn: 84778
 2009-10-21 20:44:34 +00:00
Anton Korobeynikov
23ea13afbb Add DAG printing for RMW stuff debugging 
llvm-svn: 84776
 2009-10-21 19:18:28 +00:00
Anton Korobeynikov
d233af8049 RMW preprocessing stuff was incorrect. Grab the stuff from x86 backend and disable some tests until it will be clever enough to handle them. 
llvm-svn: 84775
 2009-10-21 19:17:55 +00:00
Anton Korobeynikov
6329ddd231 Implement branch folding 
llvm-svn: 84774
 2009-10-21 19:17:18 +00:00
Anton Korobeynikov
c9ed87ea9a Cosmetic changes, no functionality changes 
llvm-svn: 84773
 2009-10-21 19:16:49 +00:00
Bob Wilson
41f94edfb0 Fix NEON VST2LN instruction encoding. 
Patch by Johnny Chen.

llvm-svn: 84767
 2009-10-21 17:54:01 +00:00
Bob Wilson
5f9ea75e2b Revert 84732. It was the wrong fix. 
llvm-svn: 84766
 2009-10-21 17:52:34 +00:00
Sanjiv Gupta
9e78b53be3 Build shared lib instead of an archive. 
llvm-svn: 84764
 2009-10-21 17:27:23 +00:00
Sanjiv Gupta
d6fd961c5c Add a pass to overlay pic16 data sections for function frame and automatic 
variables. This pass can be invoked by llvm-ld or opt to traverse over the call graph 
to detect what function frames and their automatic variables can be overlaid.
Currently this builds an archive , but needs to be changed to a loadable module.

llvm-svn: 84753
 2009-10-21 10:42:44 +00:00
Evan Cheng
275a09e55d Match more patterns to movt. 
llvm-svn: 84751
 2009-10-21 08:15:52 +00:00
Chris Lattner
690911b253 tidy 
llvm-svn: 84738
 2009-10-21 04:10:24 +00:00
Bob Wilson
02d3df4a87 Fix some more NEON instruction encoding problems. 
Thanks to Johnny Chen for discovering the problem.

llvm-svn: 84732
 2009-10-21 02:27:20 +00:00
Bob Wilson
e85a3142bc Leave some NEON instruction encoding bits unspecified instead of setting 
a default value of zero.  This is important for decoding the instructions.
Patch by Johnny Chen, with some changes from me, too.

llvm-svn: 84730
 2009-10-21 02:15:46 +00:00
Chris Lattner
2363ec8194 IPSCCP is missing stuff. 
llvm-svn: 84725
 2009-10-21 01:10:37 +00:00
Anton Korobeynikov
7c7a801467 Add note 
llvm-svn: 84713
 2009-10-21 00:14:15 +00:00
Anton Korobeynikov
f7e27bb17e Be crazy and assert in case of unsupported modifier passed. 
llvm-svn: 84712
 2009-10-21 00:13:58 +00:00
Anton Korobeynikov
3b90c55321 Handle external symbols 
llvm-svn: 84711
 2009-10-21 00:13:42 +00:00
Anton Korobeynikov
d104087bfe Distinguish between pcrel imm operands and 'normal' ones. Fix fixes gross weirdness of asmprinting. 
llvm-svn: 84710
 2009-10-21 00:13:25 +00:00
Anton Korobeynikov
c35bd58bd5 Add basic block operands & jump kinds 
llvm-svn: 84709
 2009-10-21 00:13:05 +00:00
Anton Korobeynikov
2bcb24c40b Ignore all implicit reg operands 
llvm-svn: 84708
 2009-10-21 00:12:44 +00:00
Anton Korobeynikov
f3003dfcd1 Add a workaround for different memops prefixes 
llvm-svn: 84707
 2009-10-21 00:12:27 +00:00
Anton Korobeynikov
af4c4ee8f5 Checkpoint MCInst printer. We (almostly) able to print global / JT / constpool entries 
llvm-svn: 84706
 2009-10-21 00:12:08 +00:00
Anton Korobeynikov
5a6771aab2 Add simple operand printing stuff 
llvm-svn: 84704
 2009-10-21 00:11:27 +00:00
Anton Korobeynikov
8b01906b63 Add experimental MSP430 MCInstLowering stuff 
llvm-svn: 84703
 2009-10-21 00:11:08 +00:00
Anton Korobeynikov
0c059394ac Wire up MSP430 printMCInst() method 
llvm-svn: 84702
 2009-10-21 00:10:47 +00:00
Anton Korobeynikov
a534ef3f63 Add MSP430 InstPrinter stub 
llvm-svn: 84701
 2009-10-21 00:10:30 +00:00
Anton Korobeynikov
8dc97f136b Use proper target data 
llvm-svn: 84700
 2009-10-21 00:10:00 +00:00
Daniel Dunbar
502e00c5b9 Fix -Asserts warning. 
llvm-svn: 84687
 2009-10-20 22:10:05 +00:00
Jim Grosbach
8a182902ef Disable by default while debugging 
llvm-svn: 84669
 2009-10-20 20:31:31 +00:00
Jim Grosbach
5f9188c873 add cmd line opt to disable frame index reuse for ARM and T2. debug aid. 
llvm-svn: 84664
 2009-10-20 20:19:50 +00:00
Dan Gohman
6b54c70e78 Following r84485, add Defs = [EFLAGS] to the 32-bit lock instructions too. 
llvm-svn: 84652
 2009-10-20 18:14:49 +00:00
Dan Gohman
e0ace5c4eb Make TranslateX86CC return COND_INVALID instead of aborting when it 
encounters an OEQ or UNE comparison, and update its callers to check
for this return status and recover. This fixes a problem resulting from
the LowerOperation hooks being called from LegalizeVectorOps, because
LegalizeVectorOps only lowers vectors, so OEQ and UNE comparisons may
still be at large. This fixes PR5092.

llvm-svn: 84640
 2009-10-20 16:22:37 +00:00
Benjamin Kramer
dee347a8e8 Random #include pruning. 
llvm-svn: 84632
 2009-10-20 11:44:38 +00:00
Sanjiv Gupta
28330ebddc This file is replaeced by PIC16Section.h. 
llvm-svn: 84628
 2009-10-20 09:16:32 +00:00
Chris Lattner
2a04686991 implement some more easy hooks. 
llvm-svn: 84614
 2009-10-20 06:22:33 +00:00
Chris Lattner
8137f1aef2 Implement some hooks, make printOperand abort if unknown modifiers are 
present.

llvm-svn: 84613
 2009-10-20 06:15:28 +00:00
Chris Lattner
dfe75a5667 t2MOVi32imm is currently always lowered by the Thumb2ITBlockPass. 
llvm-svn: 84611
 2009-10-20 05:58:02 +00:00
Daniel Dunbar
87b361d3d6 Wire up the ARM MCInst printer, for llvm-mc. 
llvm-svn: 84600
 2009-10-20 05:15:36 +00:00
Jim Grosbach
ea8ab9a323 Now that all ARM subtargets use frame index scavenging, the Thumb1 requires* 
functions are not needed.

llvm-svn: 84587
 2009-10-20 01:32:47 +00:00
Jim Grosbach
c4acd85bfd Enable post-pass frame index register scavenging for ARM and Thumb2 
llvm-svn: 84585
 2009-10-20 01:26:58 +00:00
Chris Lattner
8b2fb5c12a lower ARM::MOVi32imm properly. 
llvm-svn: 84583
 2009-10-20 01:11:37 +00:00
Chris Lattner
b345825d9e add support for external symbols. The mc instprinter can now handle 
reasonable code like Codegen/ARM/2009-02-27-SpillerBug.ll, producing 
identical output except for superior formatting of constant pool entries.

llvm-svn: 84582
 2009-10-20 00:56:16 +00:00
Chris Lattner
510ca3ebd7 get fancy: support basic block operands. Yay for jumps. 
llvm-svn: 84579
 2009-10-20 00:52:47 +00:00
Chris Lattner
279abd0841 add supprort for the 'sbit' operand, MOVi apparently has one. 
llvm-svn: 84577
 2009-10-20 00:46:11 +00:00
Chris Lattner
18bc7716d6 add support for instruction predicates. 
llvm-svn: 84575
 2009-10-20 00:42:49 +00:00
Chris Lattner
976978de4a implement printSORegOperand, add lowering for the nasty and despicable MOVi2pieces :) 
llvm-svn: 84573
 2009-10-20 00:40:56 +00:00
Jim Grosbach
ea7293494f Refs: A8-598. 
Leave Inst{11-8}, which represents the starting byte index of the extracted
result in the concatenation of the operands and is left unspecified.

Patch by Johnny Chen.

llvm-svn: 84572
 2009-10-20 00:38:19 +00:00
Jim Grosbach
aaa0e97800 Add missing encoding bits to NLdSt class of instructions. 
Patch by Johnny Chen.

llvm-svn: 84570
 2009-10-20 00:19:08 +00:00
Chris Lattner
db0e4f883d X86 should ignore implicit regs when lowering to MCInst also, 
no functionality change.

llvm-svn: 84567
 2009-10-19 23:35:57 +00:00
Chris Lattner
8a38b12ffe handle addmode4 modifiers, fix a fixme in printRegisterList 
by ignoring all implicit regs when lowering.

llvm-svn: 84566
 2009-10-19 23:31:43 +00:00
Chris Lattner
5630502650 simplify by using the twine form of GetOrCreateSymbol 
llvm-svn: 84565
 2009-10-19 23:05:23 +00:00
Jim Grosbach
2fb5eb1264 Enable allocation of R3 in Thumb1 
llvm-svn: 84563
 2009-10-19 22:57:03 +00:00