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16139 Commits

Author SHA1 Message Date
Owen Anderson
c9f6909c96 Add correct encodings for the basic form of vst1. 
llvm-svn: 118067
 2010-11-02 21:06:06 +00:00
Owen Anderson
b34a5f1d02 Factor out a common encoding class for loads and stores with a lane parameter. 
llvm-svn: 118055
 2010-11-02 20:47:39 +00:00
Owen Anderson
ee1337c01f Add correct encodings for the rest of the vld instructions that we generate. 
llvm-svn: 118053
 2010-11-02 20:40:59 +00:00
Jim Grosbach
5fe61a5f86 Sort bit assignments. Cosmetic change only. 
llvm-svn: 118029
 2010-11-02 17:59:04 +00:00
Jim Grosbach
d6df785c6d Revert r114340 (improvements in Darwin function prologue/epilogue), as it broke 
assumptions about stack layout. Specifically, LR must be saved next to FP.

llvm-svn: 118026
 2010-11-02 17:35:25 +00:00
Owen Anderson
9d85c89ade Add correct NEON encodings for vld2, vld3, and vld4 basic variants. 
llvm-svn: 117997
 2010-11-02 01:24:55 +00:00
Eric Christopher
a376fe69a1 Remove an assert - it's possible to be hit, and we just want to avoid 
handling those cases for now.

llvm-svn: 117996
 2010-11-02 01:24:49 +00:00
Eric Christopher
a033f49ed1 Whitespeace 
llvm-svn: 117995
 2010-11-02 01:22:45 +00:00
Eric Christopher
26ddb729bd No really, no thumb1 for arm fast isel. Also add an informative comment as 
to what someone would need to do to support thumb1.

llvm-svn: 117994
 2010-11-02 01:21:28 +00:00
Owen Anderson
f4ab06d0b6 Attempt to provide correct encodings for a number of other vld1 variants, which we can't test 
since we can neither generate nor parse them at the moment.

llvm-svn: 117988
 2010-11-02 00:24:52 +00:00
Owen Anderson
bdb861b46f Add aesthetic break. 
llvm-svn: 117986
 2010-11-02 00:14:00 +00:00
Owen Anderson
6647eb222b Add correct NEON encodings for the "multiple single elements" form of vld. 
llvm-svn: 117984
 2010-11-02 00:05:05 +00:00
Jim Grosbach
e5a253a203 Explicitly check for non-consant reference in an LDRi12 instruction. Add FIXME 
for handling the fixup necessary.

llvm-svn: 117978
 2010-11-01 23:45:50 +00:00
Jim Grosbach
d50562f0ea Remove unused function. 
llvm-svn: 117977
 2010-11-01 23:40:56 +00:00
Bob Wilson
411b511ac0 Add support for alignment operands on VLD1-lane instructions. 
This is another part of the fix for Radar 8599955.

llvm-svn: 117976
 2010-11-01 23:40:51 +00:00
Bill Wendling
dd4216420a Missed reverting this bit. 
llvm-svn: 117971
 2010-11-01 23:17:54 +00:00
Bill Wendling
37c9af176d Minor cleanup. 
llvm-svn: 117969
 2010-11-01 23:11:22 +00:00
Chris Lattner
f94c2b782a rearrange a bit. 
llvm-svn: 117967
 2010-11-01 23:07:52 +00:00
Bob Wilson
b6bc135df8 Add NEON VLD1-lane instructions. Partial fix for Radar 8599955. 
llvm-svn: 117964
 2010-11-01 22:04:05 +00:00
Bill Wendling
69e7c09c32 Move the machine operand MC encoding patterns to the parent classes. 
llvm-svn: 117956
 2010-11-01 21:17:06 +00:00
Chris Lattner
b0ac93cf15 use our fancy new MnemonicAlias mechanism to remove a bunch of hacks 
from X86AsmParser.cpp

llvm-svn: 117952
 2010-11-01 21:06:34 +00:00
Bill Wendling
4340c9449a When we look at instructions to convert to setting the 's' flag, we need to look 
at more than those which define CPSR. You can have this situation:

(1)  subs  ...
(2)  sub   r6, r5, r4
(3)  movge ...
(4)  cmp   r6, 0
(5)  movge ...

We cannot convert (2) to "subs" because (3) is using the CPSR set by
(1). There's an analogous situation here:

(1)  sub   r1, r2, r3
(2)  sub   r4, r5, r6
(3)  cmp   r4, ...
(5)  movge ...
(6)  cmp   r1, ...
(7)  movge ...

We cannot convert (1) to "subs" because of the intervening use of CPSR.

llvm-svn: 117950
 2010-11-01 20:41:43 +00:00
Bob Wilson
a9c593e696 NEON does not support truncating vector stores. Radar 8598391. 
llvm-svn: 117940
 2010-11-01 18:31:39 +00:00
Jim Grosbach
acc28d1b2a Add FIXME. 
llvm-svn: 117936
 2010-11-01 18:11:14 +00:00
Jim Grosbach
53d2661c60 Add 'IsThumb' predicate to patterns marked as 'IsThumb1Only'. The latter gates 
codegen using the patterns; the latter gates the assembler recognizing the
instruction.

llvm-svn: 117931
 2010-11-01 17:08:58 +00:00
Jim Grosbach
76910aa62f Mark ARM subtarget features that are available for the assembler. 
llvm-svn: 117929
 2010-11-01 16:59:54 +00:00
Jim Grosbach
2605b2b54f trailing whitespace 
llvm-svn: 117927
 2010-11-01 16:44:21 +00:00
Jim Grosbach
311aa5e22f The T2 extract/pack instructions are only valid in Thumb2 mode. Mark the 
patterns as such

llvm-svn: 117923
 2010-11-01 15:59:52 +00:00
Bill Wendling
da3d0ce7b5 Move instruction encoding bits into the parent class and remove the temporary 
*_Encode classes. These instructions are the only ones which use those classes,
so a subclass isn't necessary.

llvm-svn: 117906
 2010-11-01 06:00:39 +00:00
Chris Lattner
d595d1f4d7 "mov[zs]x (mem), GR16" are not ambiguous: the mem 
must be 8 bits.  Support this memory form.

llvm-svn: 117902
 2010-11-01 05:41:10 +00:00
Chris Lattner
81d051481e Implement enough of the missing instalias support to get 
aliases installed and working.  They now work when the
matched pattern and the result instruction have exactly
the same operand list.

This is now enough for us to define proper aliases for
movzx and movsx, implementing rdar://8017633 and PR7459.

Note that we do not accept instructions like:
  movzx 0(%rsp), %rsi

GAS accepts this instruction, but it doesn't make any
sense because we don't know the size of the memory
operand.  It could be 8/16/32 bits.

llvm-svn: 117901
 2010-11-01 05:34:34 +00:00
Chris Lattner
0a4807eefc make the asm matcher emitter reject instructions that have comments 
in their asmstring.  Fix the two x86 "NOREX" instructions that have them.
If these comments are important, the instlowering stuff can print them.

llvm-svn: 117897
 2010-11-01 04:44:29 +00:00
Chris Lattner
9da275f86b reject instructions that contain a \n in their asmstring. Mark 
various X86 and ARM instructions that are bitten by this as isCodeGenOnly,
as they are.

llvm-svn: 117884
 2010-11-01 00:46:16 +00:00
Chris Lattner
a4c36d0efe fix the !eq operator in tblgen to return a bit instead of an int. 
Use this to make the X86 and ARM targets set isCodeGenOnly=1 
automatically for their instructions that have Format=Pseudo,
resolving a hack in tblgen.

llvm-svn: 117862
 2010-10-31 19:22:57 +00:00
Chris Lattner
5d088218e5 two changes: make the asmmatcher generator ignore ARM pseudos properly, 
and make it a hard error for instructions to not have an asm string.
These instructions should be marked isCodeGenOnly.

llvm-svn: 117861
 2010-10-31 19:15:18 +00:00
Chris Lattner
01acd65875 reapply r117858 with apparent editor malfunction fixed (somehow I 
got a dulicated line).

llvm-svn: 117860
 2010-10-31 19:10:56 +00:00
Chris Lattner
8132a182e7 revert r117858 while I check out a failure I missed. 
llvm-svn: 117859
 2010-10-31 19:05:32 +00:00
Chris Lattner
70b05a5b88 the asm matcher can't handle operands with modifiers (like ${foo:bar}). 
Instead of silently ignoring these instructions, emit a hard error and
force the target author to either refactor the target or mark the 
instruction 'isCodeGenOnly'.

Mark a few instructions in ARM and MBlaze as isCodeGenOnly the are 
doing this.

llvm-svn: 117858
 2010-10-31 18:48:12 +00:00
Chris Lattner
8aaac91ca4 sketch out the planned instruction alias mechanism, add some comments about 
how the push/pop mnemonic aliases are wrong.

llvm-svn: 117857
 2010-10-31 18:43:46 +00:00
Duncan Sands
92f33ea784 Factorize the duplicated logic for choosing the right argument 
calling convention out of the fast and normal ISel files, and
into the calling convention TD file.

llvm-svn: 117856
 2010-10-31 13:21:44 +00:00
Duncan Sands
0f49c49476 Remove CCAssignFnForRet from X86 FastISel in favour of RetCC_X86, 
which has the same logic specified in the CallingConv TD file.
This brings FastISel in line with the standard X86 ISel.

llvm-svn: 117855
 2010-10-31 13:02:38 +00:00
Eric Christopher
e012ee8db9 Make sure we have a legal type (and simple) before continuing. 
llvm-svn: 117848
 2010-10-30 21:25:26 +00:00
Chris Lattner
49227ad505 Resolve a terrible hack in tblgen: instead of hardcoding 
"In32BitMode" and "In64BitMode" into tblgen, allow any
predicate that inherits from AssemblerPredicate.

llvm-svn: 117831
 2010-10-30 19:38:20 +00:00
Chris Lattner
15e92ddd01 Implement (and document!) support for MnemonicAlias's to have Requires 
directives, allowing things like this:

def : MnemonicAlias<"pop", "popl">, Requires<[In32BitMode]>;
def : MnemonicAlias<"pop", "popq">, Requires<[In64BitMode]>;

Move the rest of the X86 MnemonicAliases over to the .td file.

llvm-svn: 117830
 2010-10-30 19:23:13 +00:00
Chris Lattner
441672d7cb really zap alias. 
llvm-svn: 117824
 2010-10-30 18:23:25 +00:00
Chris Lattner
ba9271be5b move fcompi alias to .td file and zap some useless code. 
llvm-svn: 117823
 2010-10-30 18:22:53 +00:00
Chris Lattner
1b3b2e113f move rep aliases to td file 
llvm-svn: 117822
 2010-10-30 18:17:33 +00:00
Chris Lattner
49f977366f move sal aliases to .td file. 
llvm-svn: 117821
 2010-10-30 18:14:54 +00:00
Chris Lattner
54892b4d8d fix an encoding mismatch where "sal %eax, 1" was not using the short encoding 
for shl.  Caught by inspection.

llvm-svn: 117820
 2010-10-30 18:13:10 +00:00
Chris Lattner
38179edecd move a bunch more aliases from .cpp -> .td file. 
llvm-svn: 117819
 2010-10-30 18:07:17 +00:00
Chris Lattner
ac7f4957b1 move cmov aliases to .td file. 
llvm-svn: 117818
 2010-10-30 17:56:50 +00:00
Chris Lattner
acec7b7d46 move setcc and jcc aliases from .cpp to .td 
llvm-svn: 117817
 2010-10-30 17:51:45 +00:00
Chris Lattner
e90ff8dcb6 move some code. 
llvm-svn: 117816
 2010-10-30 17:38:55 +00:00
Chris Lattner
7c61e4bca2 implement (and document!) the first kind of MC assembler alias, which 
just remaps one mnemonic to another.  Convert a few of the X86 aliases
from .cpp to .td code.

llvm-svn: 117815
 2010-10-30 17:36:36 +00:00
Jim Grosbach
b6c76a2662 Add FIXME. 
llvm-svn: 117787
 2010-10-30 14:54:23 +00:00
Jim Grosbach
951667ac39 Clean up comments. 
llvm-svn: 117785
 2010-10-30 13:48:28 +00:00
Jim Grosbach
775afa274f Tidy up. 
llvm-svn: 117782
 2010-10-30 12:59:16 +00:00
Chris Lattner
45c679522d stay out of the reserved namespace 
llvm-svn: 117773
 2010-10-30 04:57:14 +00:00
Chris Lattner
deabc3d7fa simplify this code. 
llvm-svn: 117771
 2010-10-30 04:35:59 +00:00
Chris Lattner
3a36dd4a0b split MaybeParseRegister into its two logical uses, eliminating malloc+free traffic. 
llvm-svn: 117769
 2010-10-30 04:09:10 +00:00
Jim Grosbach
298cac8db3 Avoid re-evaluating MI.getNumOperands() every iteration of the loop. 
llvm-svn: 117766
 2010-10-30 01:40:16 +00:00
Bob Wilson
183c466006 Overhaul memory barriers in the ARM backend. Radar 8601999. 
There were a number of issues to fix up here:
* The "device" argument of the llvm.memory.barrier intrinsic should be
used to distinguish the "Full System" domain from the "Inner Shareable"
domain.  It has nothing to do with using DMB vs. DSB instructions.
* The compiler should never need to emit DSB instructions.  Remove the
ARMISD::SYNCBARRIER node and also remove the instruction patterns for DSB.
* Merge the separate DMB/DSB instructions for options only used for the
disassembler with the default DMB/DSB instructions.  Add the default
"full system" option ARM_MB::SY to the ARM_MB::MemBOpt enum.
* Add a separate ARMISD::MEMBARRIER_MCR node for subtargets that implement
a data memory barrier using the MCR instruction.
* Fix up encodings for these instructions (except MCR).
I also updated the tests and added a few new ones to check for DMB options
that were not currently being exercised.

llvm-svn: 117756
 2010-10-30 00:54:37 +00:00
Jim Grosbach
996d1280bd Encode the register list operands for ARM mode LDM/STM instructions. 
llvm-svn: 117753
 2010-10-30 00:37:59 +00:00
Bill Wendling
b68e0d0ee3 Some instructions end with an "ls" prefix, but it doesn't indicate that they are 
conditional. Check for those instructions explicitly.

llvm-svn: 117747
 2010-10-29 23:50:21 +00:00
Jim Grosbach
9a473e23b8 Remove hard tab characters. 
llvm-svn: 117742
 2010-10-29 23:23:15 +00:00
Jim Grosbach
7ca6ac347d 80 column fix. 
llvm-svn: 117741
 2010-10-29 23:21:57 +00:00
Jim Grosbach
038d376c59 trailing whitespace 
llvm-svn: 117740
 2010-10-29 23:21:03 +00:00
Jim Grosbach
7cf8dcc5bd s/getNEONVcvtImm32/getNEONVcvtImm32OpValue/ to be consistent with other operand 
encoder functions.

llvm-svn: 117738
 2010-10-29 23:19:55 +00:00
Evan Cheng
7695213793 Fix fpscr <-> GPR latency info. 
llvm-svn: 117737
 2010-10-29 23:16:55 +00:00
Jim Grosbach
e811e91d02 add FIXME 
llvm-svn: 117718
 2010-10-29 21:56:51 +00:00
Jim Grosbach
fcfc42b7bb Convert ARM::MOVi2pieces to a true pseudo-instruction and expand it in 
the ARMExpandPseudos pass rather than during the asm lowering.

llvm-svn: 117714
 2010-10-29 21:35:25 +00:00
Eric Christopher
bf7cf2a203 Handle comparison values we already have - this fixes the consumer-typeset 
failure for llvm-gcc on arm fast isel.

llvm-svn: 117710
 2010-10-29 21:08:19 +00:00
Jim Grosbach
93fbda05ee ARM::MOVi32imm is expanded in ARMExpandPseudoInsts, so there's no need to 
handle it in the asm lowering.

llvm-svn: 117707
 2010-10-29 20:37:06 +00:00
Jim Grosbach
52638aa1c8 Fix typo. 
llvm-svn: 117703
 2010-10-29 20:21:49 +00:00
Jim Grosbach
4ca61d9877 ARM encoding information for CLREX, SWP and SWPB. Add comment for sjlj pseudos and a FIXME for TLS. 
llvm-svn: 117702
 2010-10-29 20:21:36 +00:00
Jim Grosbach
162e3345fb ARM mode LDREX*/STREX* binary encodings. 
llvm-svn: 117695
 2010-10-29 19:58:57 +00:00
Jim Grosbach
5bc94b46a9 Encoding information for ARM conditional move instructions. 
llvm-svn: 117687
 2010-10-29 19:28:17 +00:00
Evan Cheng
392d2cbdcc Avoiding overly aggressive latency scheduling. If the two nodes share an 
operand and one of them has a single use that is a live out copy, favor the
one that is live out. Otherwise it will be difficult to eliminate the copy
if the instruction is a loop induction variable update. e.g.

BB:
sub r1, r3, #1
str r0, [r2, r3]
mov r3, r1
cmp
bne BB

=>

BB:
str r0, [r2, r3]
sub r3, r3, #1
cmp
bne BB

This fixed the recent 256.bzip2 regression.

llvm-svn: 117675
 2010-10-29 18:09:28 +00:00
Evan Cheng
92293993bd - Don't schedule nodes with only MVT::Flag and MVT::Other values for latency. 
- Compute CopyToReg use operand latency correctly.

llvm-svn: 117674
 2010-10-29 18:07:31 +00:00
Jim Grosbach
edec5cc6b8 Handle ARM addrmode5 instructions with an offset. 
llvm-svn: 117672
 2010-10-29 17:41:25 +00:00
John Thompson
6115a7f1d4 Inline asm multiple alternative constraints development phase 2 - improved basic logic, added initial platform support. 
llvm-svn: 117667
 2010-10-29 17:29:13 +00:00
Jim Grosbach
6f257bd31b Revert 117660. Apparently it's not as trivial as that... 
llvm-svn: 117663
 2010-10-29 16:50:53 +00:00
Jim Grosbach
8c9a2ee86e ARM addrmode5 instructions have neither writeback nor post-indexed modes. 
llvm-svn: 117660
 2010-10-29 16:38:59 +00:00
Jim Grosbach
29961ebfc5 Trailing whitespace. 
llvm-svn: 117651
 2010-10-29 14:46:02 +00:00
Benjamin Kramer
f2442da5f6 ARMAsmParser: Plug a memory leak. 
llvm-svn: 117648
 2010-10-29 09:43:39 +00:00
Eric Christopher
930a767468 Add an unreachable to silence warning - the switch is actually 
fully enumerated.

llvm-svn: 117647
 2010-10-29 09:26:59 +00:00
Chris Lattner
115cd02d22 add simple support for addrmode5 operands, allowing 
vldr.64 to work.  I have no idea if this is fully right, but 
it is in the right direction.

llvm-svn: 117626
 2010-10-29 00:27:31 +00:00
Chris Lattner
ef237e6013 give better error diagnostics, for example: 
t.s:1:14: error: invalid operand for instruction
vldr.64	d17, [r0]   
       	     ^

instead of:

t.s:1:1: error: unrecognized instruction
vldr.64	d17, [r0]   
^

llvm-svn: 117611
 2010-10-28 21:41:58 +00:00
Chris Lattner
ba1e908431 hook up getOpcodeName for ARM so that "llc -show-mc-inst" includes 
the opcode string in the inst dump, e.g.:
	vmov	r2, r3, d17             @ encoding: [0x31,0x2b,0x53,0xec]
                                        @ <MCInst #989 VMOVRRD
                                        @  <MCOperand Reg:68>
                                        @  <MCOperand Reg:69>
                                        @  <MCOperand Reg:19>
                                        @  <MCOperand Imm:14>
                                        @  <MCOperand Reg:0>>

The "VMOVRRD" is new.

llvm-svn: 117609
 2010-10-28 21:37:33 +00:00
Chris Lattner
4210ffb9c5 move a method out of line. 
llvm-svn: 117605
 2010-10-28 21:28:01 +00:00
Chris Lattner
b6c7a9e204 remove the rest of hte owningptr's, no functionality change. 
llvm-svn: 117603
 2010-10-28 20:52:15 +00:00
Benjamin Kramer
fbfb8cf5f8 Reduce malloc thrashing. 
llvm-svn: 117572
 2010-10-28 18:41:23 +00:00
Jim Grosbach
d02c1c7d77 PLD, PLDW, PLI encodings, plus refactor their use of addrmode2. 
llvm-svn: 117571
 2010-10-28 18:34:10 +00:00
Chris Lattner
0a21ad2553 rearrange ParseRegisterList. 
llvm-svn: 117560
 2010-10-28 17:23:41 +00:00
Chris Lattner
a9c0f00f10 refactor some code to simplify it, eliminating some owningptr's. 
llvm-svn: 117559
 2010-10-28 17:20:03 +00:00
Evan Cheng
bc4588c439 Re-commit 117518 and 117519 now that ARM MC test failures are out of the way. 
llvm-svn: 117531
 2010-10-28 06:47:08 +00:00
Evan Cheng
fdc80a0316 Revert 117518 and 117519 for now. They changed scheduling and cause MC tests to fail. Ugh. 
llvm-svn: 117520
 2010-10-28 02:00:25 +00:00
Evan Cheng
5c358e02ea - Assign load / store with shifter op address modes the right itinerary classes. 
- For now, loads of [r, r] addressing mode is the same as the
  [r, r lsl/lsr/asr #] variants. ARMBaseInstrInfo::getOperandLatency() should
  identify the former case and reduce the output latency by 1.
- Also identify [r, r << 2] case. This special form of shifter addressing mode
  is "free".

llvm-svn: 117519
 2010-10-28 01:49:06 +00:00
Dale Johannesen
b78530f9b0 Fix pastos in handling of AVX cvttsd2si, PR8491. 
Bruno, please review, but I'm pretty sure this is right.
Patch by Alex Mac!

llvm-svn: 117514
 2010-10-28 00:35:54 +00:00
Owen Anderson
e75f7c5419 Add correct NEON encodings for vtbl and vtbx. 
llvm-svn: 117513
 2010-10-28 00:18:46 +00:00
Owen Anderson
008116cb71 Add correct NEON encodings for vext, vtrn, vuzp, and vzip. 
llvm-svn: 117512
 2010-10-27 23:56:39 +00:00
Bob Wilson
2f8b69b196 Fix compiler warnings about signed/unsigned comparisons. 
llvm-svn: 117511
 2010-10-27 23:49:00 +00:00
Evan Cheng
44d2802e1d Shifter ops are not always free. Do not fold them (especially to form 
complex load / store addressing mode) when they have higher cost and
when they have more than one use.

llvm-svn: 117509
 2010-10-27 23:41:30 +00:00
Jim Grosbach
86ecfda983 Refactor ARM STR/STRB instruction patterns into STR{B}i12 and STR{B}rs, like 
the LDR instructions have. This makes the literal/register forms of the
instructions explicit and allows us to assign scheduling itineraries
appropriately. rdar://8477752

llvm-svn: 117505
 2010-10-27 23:12:14 +00:00
Owen Anderson
9437a20a72 Provide correct encodings for NEON vcvt, which has its own special immediate encoding 
for specifying fractional bits for fixed point conversions.

llvm-svn: 117501
 2010-10-27 22:49:00 +00:00
Jim Grosbach
1d5b71b3cc Trailing whitespace 
llvm-svn: 117496
 2010-10-27 21:39:08 +00:00
Owen Anderson
d28d229ded Provide correct encodings for the get_lane and set_lane variants of vmov. 
llvm-svn: 117495
 2010-10-27 21:28:09 +00:00
Kevin Enderby
a53cc6a764 Added the x86 instruction ud2b (2nd official undefined instruction). 
llvm-svn: 117485
 2010-10-27 20:46:49 +00:00
Jim Grosbach
db7ba38ca4 JIT imm12 encoding for constant pool entry references. 
llvm-svn: 117483
 2010-10-27 20:39:40 +00:00
Bob Wilson
cdc8dff3ac SelectionDAG shuffle nodes do not allow operands with different numbers of 
elements than the result vector type.  So, when an instruction like:

%8 = shufflevector <2 x float> %4, <2 x float> %7, <4 x i32> <i32 1, i32 0, i32 3, i32 2>

is translated to a DAG, each operand is changed to a concat_vectors node that appends 2 undef elements.  That is:

shuffle [a,b], [c,d] is changed to:
shuffle [a,b,u,u], [c,d,u,u]

That's probably the right thing for x86 but for NEON, we'd much rather have:

shuffle [a,b,c,d], undef

Teach the DAG combiner how to do that transformation for ARM.  Radar 8597007.

llvm-svn: 117482
 2010-10-27 20:38:28 +00:00
Jim Grosbach
0df1207e99 ARM JIT fix for LDRi12 and company. 
llvm-svn: 117478
 2010-10-27 19:55:59 +00:00
Owen Anderson
7c46fcfee4 Provide correct NEON encodings for vdup. 
llvm-svn: 117475
 2010-10-27 19:25:54 +00:00
Michael J. Spencer
5518dda87e x86-Win32: Switch ftol2 calling convention from stdcall to C. 
llvm-svn: 117474
 2010-10-27 18:52:38 +00:00
Jim Grosbach
5d4415c6b0 The new LDR* instruction patterns should handle the necessary encoding of 
operands in the TableGen'erated bits, so we don't need to do the additional
magic explicitly.

llvm-svn: 117461
 2010-10-27 17:52:51 +00:00
Owen Anderson
c8757eb137 Add correct NEON encodings for vsli and vsri. 
llvm-svn: 117459
 2010-10-27 17:40:08 +00:00
Owen Anderson
e64b7187a9 Add correct NEON encodings for vsra and vrsra. 
llvm-svn: 117458
 2010-10-27 17:29:29 +00:00
Jim Grosbach
09eab01a37 The immediate operands of an LDRi12 instruction doesn't need the addrmode2 
encoding tricks. Handle the 'imm doesn't fit in the insn' case.

llvm-svn: 117454
 2010-10-27 16:50:31 +00:00
Kevin Enderby
74a2614673 Yet another tweak to X86 instructions to add ud2a as an alias to ud2 
(still to add ud2b).

llvm-svn: 117435
 2010-10-27 03:01:02 +00:00
Kevin Enderby
d22f3b9de7 Another tweak to X86 instructions to add the missing flex instruction (without 
the wait prefix).

llvm-svn: 117434
 2010-10-27 02:53:04 +00:00
Kevin Enderby
e812b356cc Tweaks to X86 instructions to allow the 'w' suffix in places it makes 
sense, when the instruction takes the 16-bit ax register or m16 memory
location.  These changes to llvm-mc matches what the darwin assembler
allows for these instructions.  Done differently than in r117031 that
caused a valgrind error which was later reverted.

llvm-svn: 117433
 2010-10-27 02:32:19 +00:00
Jim Grosbach
5ccda16fe2 LDRi12 machine instructions handle negative offset operands normally (simple 
integer values), not with the addrmode2 encoding.

llvm-svn: 117429
 2010-10-27 01:19:41 +00:00
Kevin Enderby
d5235bb45c Added some aliases to the fcomip and fucompi Intel instructions. So that llvm-mc 
will accept versions that the darwin assembler allows.  Forms ending in "pi" and
forms without all the operands.

llvm-svn: 117427
 2010-10-27 00:59:28 +00:00
Jim Grosbach
6453c7cdf9 One more spot where the new arm mode LDR instruction representation 
doesn't need the additional addrmode2 register operand. Missed it the first
time around.

llvm-svn: 117421
 2010-10-27 00:38:16 +00:00
Wesley Peck
854507453a Adding disassembler to the MicroBlaze backend. 
llvm-svn: 117420
 2010-10-27 00:23:01 +00:00
Jim Grosbach
4d4caf1384 Split ARM::LDRB into LDRBi12 and LDRBrs. Adjust accordingly. Continuing on 
rdar://8477752.

llvm-svn: 117419
 2010-10-27 00:19:44 +00:00
Jim Grosbach
625e128d29 Since I parameterized this bit, I should probably actually use said parameter. 
llvm-svn: 117418
 2010-10-26 23:58:04 +00:00
Dale Johannesen
e7f07349e4 Use a MemIntrinsicSDNode for ISD::PREFETCH, which touches 
memory, so a MachineMemOperand is useful (not propagated
into the MachineInstr yet).  No functional change except
for dump output.

llvm-svn: 117413
 2010-10-26 23:11:10 +00:00
Owen Anderson
1dc05f20e2 Add correct NEON encodings for vqshl, vqshrn, vqshrun, vqrshl, vqshrn, and vqrshrun. 
llvm-svn: 117411
 2010-10-26 22:50:46 +00:00
Jim Grosbach
30f6744f05 First part of refactoring ARM addrmode2 (load/store) instructions to be more 
explicit about the operands. Split out the different variants into separate
instructions. This gives us the ability to, among other things, assign
different scheduling itineraries to the variants. rdar://8477752.

llvm-svn: 117409
 2010-10-26 22:37:02 +00:00
Owen Anderson
55c0bad37d Correct NEON encodings for vshrn, vrshl, vrshr, vrshrn. 
llvm-svn: 117402
 2010-10-26 21:58:41 +00:00
Owen Anderson
570a4cdc45 Simplify classes for shift instructions, which are never commutable. 
llvm-svn: 117398
 2010-10-26 21:13:59 +00:00
Owen Anderson
0cecbd810e Provide correct NEON encodings for vshl, register and immediate forms. 
llvm-svn: 117394
 2010-10-26 20:56:57 +00:00
Jim Grosbach
04cd5e5841 Grammar. 
llvm-svn: 117388
 2010-10-26 19:34:41 +00:00
Jim Grosbach
db5b1d93c2 Nuke extraneous comment. It's applicable elsewhere, but not in this func. 
llvm-svn: 117387
 2010-10-26 19:22:23 +00:00
Owen Anderson
d8e5d26a56 Add correct NEON encoding for vpadal. 
llvm-svn: 117380
 2010-10-26 18:18:03 +00:00
Rafael Espindola
adaf2ea5c6 handle X86::EH_RETURN64 and X86::EH_RETURN. 
llvm-svn: 117378
 2010-10-26 18:09:55 +00:00
Owen Anderson
b7618a821f Add NEON encodings for vmov and vmvn of immediates. 
llvm-svn: 117374
 2010-10-26 17:40:54 +00:00
Rafael Espindola
e38790534e Implement some relaxations for arithmetic instructions. The limitation 
on RIP relative relocations looks artificial, but this is a superset of
what we were able to do before.

llvm-svn: 117364
 2010-10-26 14:09:12 +00:00
Kalle Raiskila
64680cd5b8 Change v64 datalayout in SPU. 
The SPU ABI does not mention v64, and all examples
in C suggest v128 are treated similarily to arrays, 
we use array alignment for v64 too. This makes the 
alignment of e.g. [2 x <2 x i32>] behave "intuitively"
and similar to as if the elements were e.g. i32s.

This also makes an "unaligned store" test to be 
aligned, with different (but functionally equivalent)
code generated.

llvm-svn: 117360
 2010-10-26 10:45:47 +00:00
Evan Cheng
324e678bb7 Use instruction itinerary to determine what instructions are 'cheap'. 
llvm-svn: 117348
 2010-10-26 02:08:50 +00:00
Evan Cheng
59acb7e4cf NEON vmov's are in Neon domain. 
llvm-svn: 117347
 2010-10-26 02:03:05 +00:00
Bob Wilson
abe62128b5 Tidy up redundant check. 
llvm-svn: 117331
 2010-10-26 00:02:19 +00:00
Rafael Espindola
5fecad6a27 Produce the headers directly in the Finish method. This allows us to use 
the existing streamer methods that are endian safe.

llvm-svn: 117323
 2010-10-25 22:26:55 +00:00
Dale Johannesen
2566d39d07 An stdcall function calling a non-stdcall function 
cannot use tailcall.  PR 8461.

llvm-svn: 117322
 2010-10-25 22:17:05 +00:00
Owen Anderson
e5e0dcd665 Add correct encodings for NEON vabal. 
llvm-svn: 117315
 2010-10-25 21:29:04 +00:00
Owen Anderson
3eff0b86a5 Add correct NEON encodings for vaba. 
llvm-svn: 117309
 2010-10-25 20:52:57 +00:00
Owen Anderson
61f5b3f2dc Attempt to provide correct encodings for NEON vbit and vbif, even though we can't test them at the moment. 
llvm-svn: 117294
 2010-10-25 20:17:22 +00:00
Owen Anderson
072692331e Provide correct NEON encodings for vbsl. 
llvm-svn: 117293
 2010-10-25 20:13:13 +00:00
Jim Grosbach
1a13b873e7 imm12 operands aren't Thumb2 only, so rename the printer helper function. 
llvm-svn: 117291
 2010-10-25 20:00:01 +00:00
Owen Anderson
59e85cbd66 Add correct instruction encodings for vbic, vorn, and vmvn. 
llvm-svn: 117282
 2010-10-25 18:43:52 +00:00