1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-21 03:53:04 +02:00
Commit Graph

150409 Commits

Author SHA1 Message Date
Simon Pilgrim
87025c75e2 [CostModel][X86] Add scalar arithmetic cost tests
llvm-svn: 305810
2017-06-20 17:10:27 +00:00
Simon Pilgrim
f41727e6d0 [CostModel][X86] Declare costs variables based on type
The alphabetical progression isn't that useful

llvm-svn: 305808
2017-06-20 17:04:46 +00:00
Craig Topper
fac5b9df49 [TableGen] Take a parameter by reference instead of pointer so we don't have to add & on both callers. NFC
llvm-svn: 305807
2017-06-20 16:34:37 +00:00
Craig Topper
0391f937fe [TableGen] Use range based for loop. NFC
llvm-svn: 305806
2017-06-20 16:34:35 +00:00
Yuka Takahashi
3b19a660ec [GSoC] Flag value completion for clang
This is patch for GSoC project, bash-completion for clang.

To use this on bash, please run `source clang/utils/bash-autocomplete.sh`.
bash-autocomplete.sh is code for bash-completion.

In this patch, Options.td was mainly changed in order to add value class
in Options.inc.

llvm-svn: 305805
2017-06-20 16:31:31 +00:00
Sanjay Patel
f4fed2c4b8 [x86] enable CGP memcmp() expansion for 2/4/8 byte sizes
There are a couple of potential improvements as seen in the IR and asm:
1. We're unnecessarily extending to a larger type to compare values.
2. The codegen for (select cond, 1, -1) could avoid a cmov.
(or we could change the order of the compares, so we have a select with 0 operand)

llvm-svn: 305802
2017-06-20 15:58:30 +00:00
Simon Pilgrim
df21643743 [X86][SSE] Relax 0/-1 vector element insertion to work for any vector with >=16bit elements
Shuffle lowering/combining now does a good job for 256/512-bit vectors - we don't need to prevent this

llvm-svn: 305801
2017-06-20 15:19:02 +00:00
Tim Northover
a30b7057aa DAG: correctly legalize UMULO.
We were incorrectly sign extending into the high word (as you would for
SMULO) when legalizing UMULO in terms of a wider full multiplication.

Patch by James Duley.

llvm-svn: 305800
2017-06-20 15:01:38 +00:00
Vassil Vassilev
b1c3f2425a D33466: Make file non-executable.
llvm-svn: 305795
2017-06-20 14:20:48 +00:00
Sanjay Patel
2cd42e59fa [InstCombine] fix code/test comments for r305792; NFC
These diffs were in the last version of the patch in D33342,
but I accidentally committed the previous rev. 

llvm-svn: 305793
2017-06-20 12:45:46 +00:00
Sanjay Patel
b1e57ed5ec [InstCombine] try to canonicalize xor-of-icmps to and-of-icmps
We have a large portfolio of folds for and-of-icmps and or-of-icmps in InstSimplify and InstCombine, 
but hardly anything for xor-of-icmps. Rather than trying to rethink and translate all of those folds, 
we can use the truth table definition of xor:

X ^ Y --> (X | Y) & !(X & Y)

...to see if we can convert the xor to and/or and then use the existing folds.

http://rise4fun.com/Alive/J9v

Differential Revision: https://reviews.llvm.org/D33342

llvm-svn: 305792
2017-06-20 12:40:55 +00:00
Daniel Sanders
0c5795464b [globalisel][tablegen] Add support for COPY_TO_REGCLASS.
Summary:
As part of this
* Emitted instructions now have named MachineInstr variables associated
  with them. This isn't particularly important yet but it's a small step
  towards multiple-insn emission.
* constrainSelectedInstRegOperands() is no longer hardcoded. It's now added
  as the ConstrainOperandsToDefinitionAction() action. COPY_TO_REGCLASS uses
  an alternate constraint mechanism ConstrainOperandToRegClassAction() which
  supports arbitrary constraints such as that defined by COPY_TO_REGCLASS.

Reviewers: ab, qcolombet, t.p.northover, rovka, kristof.beyls, aditya_nandakumar

Reviewed By: ab

Subscribers: javed.absar, igorb, llvm-commits

Differential Revision: https://reviews.llvm.org/D33590

llvm-svn: 305791
2017-06-20 12:36:34 +00:00
Simon Pilgrim
a081b25bbc Fix Wdocumentation warning
llvm-svn: 305790
2017-06-20 12:28:33 +00:00
Simon Pilgrim
8890df3f13 [X86][SSE] Dropped old INSERT_VECTOR_ELT lowering TODO
Target shuffle combining now supports the matching of INSERT_VECTOR_ELT/PINSRW/PINSRB for merging multiple insertions into shuffles/bitmasks.

llvm-svn: 305788
2017-06-20 10:33:34 +00:00
Simon Pilgrim
fb1bb45c57 Fixed test name. NFCI.
llvm-svn: 305787
2017-06-20 10:24:06 +00:00
Igor Breger
812ef348d0 [GlobalISel][X86] fix compilation error ( -Werror=unused-function )
llvm-svn: 305786
2017-06-20 09:40:57 +00:00
Haojian Wu
d2efe6d376 [SelectionDAG] Fix an use-after-free issue introduced in r305775.
vector.back() will be invalidated when memory reallocation happens.

llvm-svn: 305785
2017-06-20 09:29:43 +00:00
Igor Breger
4e3209ead1 [GlobalISel][X86] Get correct RegClass for given RegBank.
Summary:
In some cases RegClass depends on target feature. Hight (16-31) vector registers exist only if AVX512f available.
Split from https://reviews.llvm.org/D33665

Reviewers: qcolombet, t.p.northover, zvi, guyblank

Reviewed By: t.p.northover, guyblank

Subscribers: guyblank, rovka, llvm-commits, kristof.beyls

Differential Revision: https://reviews.llvm.org/D33952

Conflicts:
	test/CodeGen/X86/GlobalISel/select-memop-scalar.mir

llvm-svn: 305784
2017-06-20 09:15:10 +00:00
Igor Breger
078eb813d6 [GlobalISel] combine not symmetric merge/unmerge nodes.
Summary:
In some cases legalization ends up with not symmetric merge/unmerge nodes.
Transform it to merge/unmerge nodes.

Reviewers: t.p.northover, qcolombet, zvi

Reviewed By: t.p.northover

Subscribers: rovka, kristof.beyls, guyblank, llvm-commits

Differential Revision: https://reviews.llvm.org/D33626

llvm-svn: 305783
2017-06-20 08:54:17 +00:00
Max Kazantsev
c0bcdacb00 [SCEV][NFC] Fix a misleading description of AddOpsInlineThreshold
The description of this option was copy-pasted from another one and does not
correspond to reality.

Differential Revision: https://reviews.llvm.org/D34390

llvm-svn: 305782
2017-06-20 08:37:31 +00:00
Igor Breger
3c1f43a412 [GlobalISel][X86] add legalizer mir tests. NFC
llvm-svn: 305781
2017-06-20 08:30:48 +00:00
NAKAMURA Takumi
f47dcd2ae3 WasmObjectWriter.cpp: Tweak a comment line. [-Wdocumentation]
llvm-svn: 305777
2017-06-20 07:21:19 +00:00
Alexandros Lamprineas
4796e0f03c [ARM] Support constant pools in data when generating execute-only code.
Resubmission of r305387, which was reverted at r305390. The Address
Sanitizer caught a stack-use-after-scope of a Twine variable. This
is now fixed by passing the Twine directly as a function parameter.

The ARM backend asserts against constant pool lowering when it generates
execute-only code in order to prevent the generation of constant pools in
the text section. It appears that target independent optimizations might
generate DAG nodes that represent constant pools. By lowering such nodes
as global addresses we don't violate the semantics of execute-only code
and also it is guaranteed that execute-only behaves correct with the
position-independent addressing modes that support execute-only code.

Differential Revision: https://reviews.llvm.org/D33773

llvm-svn: 305776
2017-06-20 07:20:52 +00:00
Max Kazantsev
178450709e [SelectionDAG] Get rid of recursion in CalcNodeSethiUllmanNumber
The recursive implementation of CalcNodeSethiUllmanNumber may
overflow stack on extremely long pred chains. This patch replaces it
with an equivalent iterative implementation.

Differential Revision: https://reviews.llvm.org/D33769

llvm-svn: 305775
2017-06-20 07:07:09 +00:00
Sam Clegg
22ea3d5964 Fix unused function build error in lld
The lld-x86_64-darwin13 is failing with:
 error: unused function 'operator<<'

Wrap the declation in ifndef NDEBUG, which matches
what is done in MipsELFObjectWriter.cpp.

Differential Revision: https://reviews.llvm.org/D34384

llvm-svn: 305771
2017-06-20 05:05:10 +00:00
Sam Clegg
3393d8be1b [WebAssembly] Fix build failures introduced in r305769
This fixes two build failures that only occur in certain
configurations:
- error: unused function 'operator<<'
- error: control reaches end of non-void function

Differential Revision: https://reviews.llvm.org/D34382

llvm-svn: 305770
2017-06-20 04:47:58 +00:00
Sam Clegg
add57cc355 [WebAssembly] Add support for weak symbols in the binary format
This also introduces the updated format for the
"linking" section which can represent extra
symbol information.  See:
https://github.com/WebAssembly/tool-conventions/pull/10

Differential Revision: https://reviews.llvm.org/D34019

llvm-svn: 305769
2017-06-20 04:04:59 +00:00
Nirav Dave
2d9d97ed85 [DAG] Simplify BaseIndexOffset. NFCI.
Remove tail calls and cleanup codeflow.

llvm-svn: 305768
2017-06-20 02:48:39 +00:00
Vedant Kumar
5dd7f329b9 [Coverage] PR33517: Check for failure to load func records
With PR33517, it became apparent that symbol table creation can fail
when presented with malformed inputs. This patch makes that sort of
error detectable, so llvm-cov etc. can fail more gracefully.

Specifically, we now check that function records loaded from corrupted coverage
mapping data are rejected, e.g when the recorded function name is garbage.

Testing: check-{llvm,clang,profile}, some unit test updates.
llvm-svn: 305767
2017-06-20 02:05:35 +00:00
Vedant Kumar
30059fc639 [ProfileData] PR33517: Check for failure of symtab creation
With PR33517, it became apparent that symbol table creation can fail
when presented with malformed inputs. This patch makes that sort of
error detectable, so llvm-cov etc. can fail more gracefully.

Specifically, we now check that function names within the symbol table
aren't empty.

Testing: check-{llvm,clang,profile}, some unit test updates.
llvm-svn: 305765
2017-06-20 01:38:56 +00:00
Pengxuan Zheng
4bf7cb91e6 [test-release.sh] Enable Polly by default
Reviewers: grosser, hans, zinob, bollu

Reviewed By: grosser, hans

Subscribers: tstellar, llvm-commits

Differential Revision: https://reviews.llvm.org/D34306

llvm-svn: 305763
2017-06-20 01:04:25 +00:00
Kevin Enderby
3a465194e0 The change to llvm-nm in r305733 added fields to the struct NMSymbol
that are not set on the main path.  This diff does a memset to 0 the structs
so this change is to hopefully fix the sanitizer-x86_64-linux-fast bot.

llvm-svn: 305762
2017-06-20 00:41:04 +00:00
Matt Arsenault
07bc25efff AMDGPU: Fix scratch wave offset relative FI expansion
The offset may not be an inline immediate, so this needs
to be materialized into a register. The post-RA run of
SIShrinkInstructions is able to fold it later if it can.

llvm-svn: 305761
2017-06-19 23:47:21 +00:00
Eugene Zelenko
b39b18061f [ExecutionEngine] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).
llvm-svn: 305760
2017-06-19 23:37:52 +00:00
Stanislav Mekhanoshin
a2f5f5f7c9 [AMDGPU] Add infer address spaces pass before SROA
It adds it for the target after inlining but before SROA where
we can get most out of it.

Differential Revision: https://reviews.llvm.org/D34366

llvm-svn: 305759
2017-06-19 23:17:36 +00:00
Eugene Zelenko
027b1deacd [Target] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).
llvm-svn: 305757
2017-06-19 22:43:19 +00:00
Sanjoy Das
3d994828fb Fix machine instruction in test case
The AMD64rm instruction used in the test case was incorrect.  Since
the first input register to AND64rm is tied to output register, they
must be the same.

Thanks for Jesper Antonsson for pointing this out!

llvm-svn: 305756
2017-06-19 22:35:48 +00:00
Eugene Zelenko
537a4b7ebe [IR] Fix some Clang-tidy modernize-use-using warnings; other minor fixes (NFC).
llvm-svn: 305755
2017-06-19 22:05:08 +00:00
Zachary Turner
90731bf011 Mark LLVMTestingSupport as not installed in LLVMBuild.
This is causing downstream issues with llvm-config.

llvm-svn: 305754
2017-06-19 22:01:50 +00:00
Zachary Turner
49affd87fd Try to fix uninitialized read in unit test.
llvm-svn: 305753
2017-06-19 21:59:09 +00:00
Geoff Berry
ad34e35a7f [AArch64][Falkor] Fix MOVZ sched predicate to not assert on non-imm operands (e.g. blockaddress).
llvm-svn: 305752
2017-06-19 21:57:44 +00:00
Geoff Berry
3d87ec3654 [AArch64][Kryo] Add missing write latency for LDAXP, LDXP second destination.
Fixes PR33491 and PR33512.

llvm-svn: 305751
2017-06-19 21:57:42 +00:00
Geoff Berry
880ca11fdd [AArch64][Falkor] Refine load/store increment latencies.
Also fix LDXP & LDAXP write latency to avoid similar assert as PR33491 and PR33512.

llvm-svn: 305750
2017-06-19 21:56:21 +00:00
Matt Arsenault
4985027a8e Fix typos
llvm-svn: 305749
2017-06-19 21:54:25 +00:00
Matt Arsenault
1b9121f71c AMDGPU: Cleanup CreateLiveInRegister
llvm-svn: 305748
2017-06-19 21:52:45 +00:00
Kevin Enderby
dbfe579a76 Fix a FIXME in llvm-objdump for the -exports-trie option that was not adding
in the base address.

Without this Mach-O files, like 64-bit executables, don’t have the correct
addresses printed for their exports.  As the default is to link at address
0x100000000 not zero.

llvm-svn: 305744
2017-06-19 21:23:07 +00:00
Peter Collingbourne
3b89f3ca38 Revert r305598, "utils: Add a git-r utility for mapping svn revisions to git revisions in the monorepo."
$ git revert `git r 305598`

We need to decide whether we want development tools to be written in
Go first.

llvm-svn: 305741
2017-06-19 20:43:09 +00:00
Xin Tong
704d43f5cc [BDCE] Add comments. NFC
llvm-svn: 305739
2017-06-19 20:10:41 +00:00
Ana Pazos
a93403ab41 [PATCH] [PGO] Fixed cast operation in emIntrinsicVisitor::instrumentOneMemIntrinsic.
Reviewers: xur, efriedma, davidxl

Reviewed By: davidxl

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D34293

llvm-svn: 305737
2017-06-19 20:04:33 +00:00
Nico Weber
03baa7ddbb Revert r305382, it caused PR33513.
llvm-svn: 305735
2017-06-19 19:48:59 +00:00