Jim Laskey
92eccb9901
Changed code gen for int to f32 to use rounding. This makes FP results
...
consistent with gcc.
llvm-svn: 22791
2005-08-15 17:14:19 +00:00
Nate Begeman
54423e60c6
Fix last night's PPC32 regressions by
...
1. Not selecting the false value of a select_cc in the false arm, which
isn't legal for nested selects.
2. Actually returning the node we created and Legalized in the FP_TO_UINT
Expander.
llvm-svn: 22789
2005-08-14 18:38:32 +00:00
Nate Begeman
2426bb6589
Make FP_TO_UINT Illegal. This allows us to generate significantly better
...
codegen for FP_TO_UINT by using the legalizer's SELECT variant.
Implement a codegen improvement for SELECT_CC, selecting the false node in
the MBB that feeds the phi node. This allows us to codegen:
void foo(int *a, int b, int c) { int d = (a < b) ? 5 : 9; *a = d; }
as:
_foo:
li r2, 5
cmpw cr0, r4, r3
bgt .LBB_foo_2 ; entry
.LBB_foo_1: ; entry
li r2, 9
.LBB_foo_2: ; entry
stw r2, 0(r3)
blr
insted of:
_foo:
li r2, 5
li r5, 9
cmpw cr0, r4, r3
bgt .LBB_foo_2 ; entry
.LBB_foo_1: ; entry
or r2, r5, r5
.LBB_foo_2: ; entry
stw r2, 0(r3)
blr
llvm-svn: 22784
2005-08-14 01:17:16 +00:00
Jim Laskey
6b95280f3c
Fix for 2005-08-12-rlwimi-crash.ll. Make allowance for masks being shifted to
...
zero.
llvm-svn: 22773
2005-08-12 23:52:46 +00:00
Jim Laskey
7b32c9131d
1. This changes handles the cases of (~x)&y and x&(~y) yielding ANDC, and
...
(~x)|y and x|(~y) yielding ORC.
llvm-svn: 22771
2005-08-12 23:38:02 +00:00
Jim Laskey
c79447e1ec
1. Added the function isOpcWithIntImmediate to simplify testing of operand with
...
specified opcode and an integer constant right operand.
2. Modified ISD::SHL, ISD::SRL, ISD::SRA to use rlwinm when applied after a mask.
llvm-svn: 22761
2005-08-11 21:59:23 +00:00
Chris Lattner
4d353459a3
Tidied up the use of dyn_cast<ConstantSDNode> by using isIntImmediate more.
...
Patch by Jim Laskey.
llvm-svn: 22760
2005-08-11 17:56:50 +00:00
Chris Lattner
5cba0bb5bb
Use a more efficient method of creating integer and float virtual registers
...
(avoids an extra level of indirection in MakeReg).
defined MakeIntReg using RegMap->createVirtualRegister(PPC32::GPRCRegisterClass)
defined MakeFPReg using RegMap->createVirtualRegister(PPC32::FPRCRegisterClass)
s/MakeReg(MVT::i32)/MakeIntReg/
s/MakeReg(MVT::f64)/MakeFPReg/
Patch by Jim Laskey!
llvm-svn: 22759
2005-08-11 17:15:31 +00:00
Nate Begeman
23479935cc
Make SELECT illegal on PPC32, switch to using SELECT_CC, which more closely
...
reflects what the hardware is capable of. This significantly simplifies
the CC handling logic throughout the ISel.
llvm-svn: 22756
2005-08-10 20:52:09 +00:00
Chris Lattner
512a5e507e
Changes for PPC32ISelPattern.cpp
...
1. Clean up how SelectIntImmediateExpr handles use counts.
2. "Subtract from" was not clearing hi 16 bits.
Patch by Jim Laskey
llvm-svn: 22754
2005-08-10 18:11:33 +00:00
Chris Lattner
91f83576d8
Changed the XOR case to use the isOprNot predicate.
...
Patch by Jim Laskey!
llvm-svn: 22750
2005-08-10 16:35:46 +00:00
Chris Lattner
ad6d368eee
1. Refactored handling of integer immediate values for add, or, xor and sub.
...
New routine: ISel::SelectIntImmediateExpr
2. Now checking use counts of large constants. If use count is > 2 then drop
thru so that the constant gets loaded into a register.
Source:
int %test1(int %a) {
entry:
%tmp.1 = add int %a, 123456789 ; <int> [#uses=1]
%tmp.2 = or int %tmp.1, 123456789 ; <int> [#uses=1]
%tmp.3 = xor int %tmp.2, 123456789 ; <int> [#uses=1]
%tmp.4 = sub int %tmp.3, -123456789 ; <int> [#uses=1]
ret int %tmp.4
}
Did Emit:
.machine ppc970
.text
.align 2
.globl _test1
_test1:
.LBB_test1_0: ; entry
addi r2, r3, -13035
addis r2, r2, 1884
ori r2, r2, 52501
oris r2, r2, 1883
xori r2, r2, 52501
xoris r2, r2, 1883
addi r2, r2, 52501
addis r3, r2, 1883
blr
Now Emits:
.machine ppc970
.text
.align 2
.globl _test1
_test1:
.LBB_test1_0: ; entry
lis r2, 1883
ori r2, r2, 52501
add r3, r3, r2
or r3, r3, r2
xor r3, r3, r2
add r3, r3, r2
blr
Patch by Jim Laskey!
llvm-svn: 22749
2005-08-10 16:34:52 +00:00
Chris Lattner
74acf5edc8
Fix a bug compiling: select (i32 < i32), f32, f32
...
llvm-svn: 22747
2005-08-10 03:40:09 +00:00
Chris Lattner
1277703a48
Update the targets to the new SETCC/CondCodeSDNode interfaces.
...
llvm-svn: 22729
2005-08-09 20:21:10 +00:00
Chris Lattner
1552a40112
Minor cleanup patch, no functionality changes. Written by Jim Laskey.
...
llvm-svn: 22727
2005-08-09 18:29:55 +00:00
Chris Lattner
b3baf30fdd
Fix CodeGen/Generic/div-neg-power-2.ll, a regression from last night.
...
llvm-svn: 22726
2005-08-09 18:08:41 +00:00
Nate Begeman
6b842b4883
Factor out some common code, and be smarter about when to emit load hi/lo
...
code sequences.
llvm-svn: 22719
2005-08-08 22:22:56 +00:00
Chris Lattner
afd68f8f76
Remove getImmediateForOpcode, which is now dead.
...
Patch by Jim Laskey.
llvm-svn: 22716
2005-08-08 21:34:13 +00:00
Chris Lattner
f0eb0b2af5
Add new immediate handling support for mul/div.
...
Patch by Jim Laskey!
llvm-svn: 22715
2005-08-08 21:33:23 +00:00
Chris Lattner
8efdc3c8d4
Add support for OR/XOR/SUB immediates that are handled with the new immediate
...
way. This allows ORI/ORIS pairs, for example.
llvm-svn: 22714
2005-08-08 21:30:29 +00:00
Chris Lattner
051d45ce3c
Modify the ISD::AND opcode case to use new immediate constant predicates.
...
Includes wider support for rotate and mask cases.
Patch by Jim Laskey.
I've requested that Jim add new regression tests the newly handled cases.
llvm-svn: 22712
2005-08-08 21:24:57 +00:00
Chris Lattner
3b23144fc0
Modify the ISD::ADD opcode case to use new immediate constant predicates.
...
Includes support for 32-bit constants using addi/addis.
Patch by Jim Laskey.
llvm-svn: 22711
2005-08-08 21:21:03 +00:00
Chris Lattner
69eed9f8a7
Modify existing support functions to use new immediate constant predicates.
...
Patch by Jim Laskey
llvm-svn: 22710
2005-08-08 21:12:35 +00:00
Chris Lattner
fab821d774
Add support predicates for future immediate constant changes.
...
Patch by Jim Laskey
llvm-svn: 22709
2005-08-08 21:10:27 +00:00
Chris Lattner
f6320ae69a
Move IsRunOfOnes to a more logical place and rename to a proper predicate form
...
(lowercase isXXX).
Patch by Jim Laskey.
llvm-svn: 22708
2005-08-08 21:08:09 +00:00
Chris Lattner
93820f4ad7
Consolidate the GPOpt stuff to all use the Subtarget, instead of still
...
depending on the command line option. Now the command line option just
sets the subtarget as appropriate. G5 opts will now default to on on
G5-enabled nightly testers among other machines.
llvm-svn: 22688
2005-08-05 22:05:03 +00:00
Misha Brukman
41a00bbfa6
Fix grammar: apostrophe-s ('s) is possessive, not plural; also iff vs. if.
...
llvm-svn: 22619
2005-08-03 17:29:52 +00:00
Chris Lattner
adfe9f12ef
minor capitalization thing, patch by Jim Laskey
...
llvm-svn: 22617
2005-08-03 16:52:22 +00:00
Chris Lattner
75a8a64de4
This hunk accidentally got dropped. Patch by Jim Laskey
...
llvm-svn: 22595
2005-08-02 19:30:55 +00:00
Chris Lattner
cc8ae687e1
Update to use the new MathExtras.h support for log2 computation.
...
Patch contributed by Jim Laskey!
llvm-svn: 22594
2005-08-02 19:26:06 +00:00
Chris Lattner
3a81e0795b
add a pass name to make debugging dumps nicer
...
llvm-svn: 22588
2005-08-02 19:07:49 +00:00
Chris Lattner
5d02e3a15e
Eliminate an extra copy from R1 that Nate noticed on function calls that
...
have to write arguments to the stack
llvm-svn: 22536
2005-07-28 05:23:43 +00:00
Chris Lattner
a9dac1cd7a
Specify the correct number of operands
...
llvm-svn: 22535
2005-07-28 04:42:11 +00:00
Nate Begeman
b125feb99f
Fold constant adds into loads and stores to frame indices.
...
For the following code:
double %ext(int %A.0__, long %A.1__) {
%A_addr = alloca %typedef.DComplex ; <%typedef.DComplex*> [#uses=2]
%tmp.1 = cast %typedef.DComplex* %A_addr to int* ; <int*> [#uses=1]
store int %A.0__, int* %tmp.1
%tmp.2 = getelementptr %typedef.DComplex* %A_addr, int 0, uint 1 ; <double*> [#uses=2]
%tmp.3 = cast double* %tmp.2 to long* ; <long*> [#uses=1]
store long %A.1__, long* %tmp.3
%tmp.5 = load double* %tmp.2 ; <double> [#uses=1]
ret double %tmp.5
}
We now generate:
_ext:
.LBB_ext_0: ;
stw r3, -12(r1)
stw r4, -8(r1)
stw r5, -4(r1)
lfd f1, -8(r1)
blr
Instead of:
_ext:
.LBB_ext_0: ;
stw r3, -12(r1)
addi r2, r1, -12
stw r4, 4(r2)
stw r5, 8(r2)
lfd f1, 4(r2)
blr
This also fires hundreds of times on MultiSource.
llvm-svn: 22533
2005-07-28 03:02:05 +00:00
Nate Begeman
d230bf7242
Fix some comments
...
llvm-svn: 22530
2005-07-27 23:11:27 +00:00
Jeff Cohen
bd51ec7461
Eliminate all remaining tabs and trailing spaces.
...
llvm-svn: 22523
2005-07-27 06:12:32 +00:00
Nate Begeman
19014db53f
Fix an optimization put in for accessing static globals. This obviates
...
the need to build PIC.
llvm-svn: 22512
2005-07-25 21:15:28 +00:00
Chris Lattner
dd14de5a1e
PowerPC no-pic code is not quite ready for prime-time
...
llvm-svn: 22507
2005-07-22 22:58:34 +00:00
Nate Begeman
7259cc60c4
Support building non-PIC
...
Remove the LoadHiAddr pseudo-instruction.
Optimization of stores to and loads from statics.
Force JIT to use new non-PIC codepaths.
llvm-svn: 22494
2005-07-21 20:44:43 +00:00
Nate Begeman
ae843fcefe
Generate mfocrf when targeting g5. Generate fsqrt/fsqrts when targetin g5.
...
8-byte align doubles.
llvm-svn: 22486
2005-07-20 22:42:00 +00:00
Nate Begeman
b83789d611
Integrate SelectFPExpr into SelectExpr. This gets PPC32 closer to being
...
automatically generated from a target description.
llvm-svn: 22470
2005-07-19 16:51:05 +00:00
Chris Lattner
ffaf40a143
Change *EXTLOAD to use an VTSDNode operand instead of being an MVTSDNode.
...
This is the last MVTSDNode.
This allows us to eliminate a bunch of special case code for handling
MVTSDNodes.
Also, remove some uses of dyn_cast that should really be cast (which is
cheaper in a release build).
llvm-svn: 22368
2005-07-10 01:56:13 +00:00
Chris Lattner
273b81e0c0
Change TRUNCSTORE to use a VTSDNode operand instead of being an MVTSTDNode
...
llvm-svn: 22366
2005-07-10 00:29:18 +00:00
Chris Lattner
199560c668
Make several cleanups to Andrews varargs change:
...
1. Pass Value*'s into lowering methods so that the proper pointers can be
added to load/stores from the valist
2. Intrinsics that return void should only return a token chain, not a token
chain/retval pair.
3. Rename LowerVAArgNext -> LowerVAArg, because VANext is long gone.
4. Now that we have Value*'s available in the lowering methods, pass them
into any load/stores from the valist that are emitted
llvm-svn: 22339
2005-07-05 19:58:54 +00:00
Chris Lattner
23a1b681d0
Fix PowerPC varargs
...
llvm-svn: 22335
2005-07-05 17:48:31 +00:00
Chris Lattner
6a865d5a22
Varargs is apparently currently broken on PPC. This hacks it so that it
...
is at least overloading the right virtual methods. The implementations
are currently wrong though. This fixes Ptrdist/bc, but not other programs
(e.g. siod).
llvm-svn: 22326
2005-07-01 23:11:56 +00:00
Nate Begeman
12cd2d8d99
Commit fix for generating conditional branch pseudo instructions that
...
avoids dereferencing the end() iterator when selecting the fallthrough
block. This requires an ilist change.
llvm-svn: 22212
2005-06-15 18:22:43 +00:00
Nate Begeman
9bb1be2eec
Commit a small improvement that is already in the x86 and ia64 backends to
...
not generate unnecessary register copies. This improves compile time by
2-5% depending on the test.
llvm-svn: 22210
2005-06-14 03:55:23 +00:00
Nate Begeman
47cd13d42a
Handle some more real world cases of rlwimi. These don't come up that
...
regularly in "normal" code, but for things like software graphics, they
make a big difference.
For the following code:
unsigned short Trans16Bit(unsigned srcA,unsigned srcB,unsigned alpha)
{
unsigned tmpA,tmpB,mixed;
tmpA = ((srcA & 0x03E0) << 15) | (srcA & 0x7C1F);
tmpB = ((srcB & 0x03E0) << 15) | (srcB & 0x7C1F);
mixed = (tmpA * alpha) + (tmpB * (32 - alpha));
return ((mixed >> 5) & 0x7C1F) | ((mixed >> 20) & 0x03E0);
}
We now generate:
_Trans16Bit:
.LBB_Trans16Bit_0: ; entry
andi. r2, r4, 31775
rlwimi r2, r4, 15, 7, 11
subfic r4, r5, 32
mullw r2, r2, r4
andi. r4, r3, 31775
rlwimi r4, r3, 15, 7, 11
mullw r3, r4, r5
add r2, r2, r3
srwi r3, r2, 5
andi. r3, r3, 31775
rlwimi r3, r2, 12, 22, 26
blr
Instead of:
_Trans16Bit:
.LBB_Trans16Bit_0: ; entry
slwi r2, r4, 15
rlwinm r2, r2, 0, 7, 11
andi. r4, r4, 31775
or r2, r2, r4
subfic r4, r5, 32
mullw r2, r2, r4
slwi r4, r3, 15
rlwinm r4, r4, 0, 7, 11
andi. r3, r3, 31775
or r3, r4, r3
mullw r3, r3, r5
add r2, r2, r3
srwi r3, r2, 5
andi. r3, r3, 31775
srwi r2, r2, 20
rlwimi r3, r2, 0, 22, 26
blr
llvm-svn: 22201
2005-06-08 04:14:27 +00:00
Chris Lattner
9fc81f1162
Fix andrews changes to fit in 80 columns
...
llvm-svn: 22064
2005-05-15 19:54:37 +00:00