Chris Lattner
9cd4e3429e
Completely eliminate def&use operands. Now a register operand is EITHER a
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def operand or a use operand.
llvm-svn: 30109
2006-09-05 02:31:13 +00:00
Chris Lattner
a2eba83561
switch the SUnit pred/succ sets from being std::sets to being smallvectors.
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This reduces selectiondag time on kc++ from 5.43s to 4.98s (9%). More
significantly, this speeds up the default ppc scheduler from ~1571ms to 1063ms,
a 33% speedup.
llvm-svn: 29743
2006-08-17 00:09:56 +00:00
Evan Cheng
0853250689
Reverse the FlaggedNodes after scanning up for flagged preds or else the order would be reversed.
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llvm-svn: 29545
2006-08-07 22:12:12 +00:00
Jim Laskey
a67adda697
Use an enumeration to eliminate data relocations.
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llvm-svn: 29249
2006-07-21 20:57:35 +00:00
Jim Laskey
d19ba2cf6c
It was pointed out that DEBUG() is only available with -debug.
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llvm-svn: 29106
2006-07-11 18:25:13 +00:00
Jim Laskey
4c0d841280
Ensure that dump calls that are associated with asserts are removed from
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non-debug build.
llvm-svn: 29105
2006-07-11 17:58:07 +00:00
Evan Cheng
07d8ccec50
Instructions with variable operands (variable_ops) can have a number required
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operands. e.g.
def CALL32r : I<0xFF, MRM2r, (ops GR32:$dst, variable_ops),
"call {*}$dst", [(X86call GR32:$dst)]>;
TableGen should emit operand informations for the "required" operands.
Added a target instruction info flag M_VARIABLE_OPS to indicate the target
instruction may have more operands in addition to the minimum required
operands.
llvm-svn: 28791
2006-06-15 07:22:16 +00:00
Evan Cheng
5b6029f577
commuteInstruction() does not always create a new MI!
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llvm-svn: 28592
2006-05-31 18:03:39 +00:00
Evan Cheng
6a09baaff4
Eliminate a memory leak.
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llvm-svn: 28585
2006-05-31 07:13:03 +00:00
Evan Cheng
00c1318055
lib/Target/Target.td
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llvm-svn: 28386
2006-05-18 20:42:07 +00:00
Chris Lattner
fdd62b9073
Move function-live-in-handling code from the sdisel code to the scheduler.
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This code should be emitted after legalize, so it can't be in sdisel.
Note that the EmitFunctionEntryCode hook should be updated to operate on the
DAG. The X86 backend is the only one currently using this hook.
llvm-svn: 28315
2006-05-16 06:10:58 +00:00
Evan Cheng
489f9bd68f
Fixing 2006-05-01-SchedCausingSpills.ll; some clean up
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llvm-svn: 28279
2006-05-13 08:22:24 +00:00
Owen Anderson
29e4d70aed
Refactor a bunch of includes so that TargetMachine.h doesn't have to include
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TargetData.h. This should make recompiles a bit faster with my current
TargetData tinkering.
llvm-svn: 28238
2006-05-12 06:33:49 +00:00
Evan Cheng
c24d0f281c
Duh. That could take a long time.
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llvm-svn: 28235
2006-05-12 06:05:18 +00:00
Evan Cheng
0b8e4bca80
Add capability to scheduler to commute nodes for profit.
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If a two-address code whose first operand has uses below, it should be commuted
when possible.
llvm-svn: 28230
2006-05-12 01:58:24 +00:00
Evan Cheng
cb2a0f392c
Refactor scheduler code. Move register-reduction list scheduler to a
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separate file. Added an initial implementation of top-down register pressure
reduction list scheduler.
llvm-svn: 28226
2006-05-11 23:55:42 +00:00
Chris Lattner
075404adaa
Remove and simplify some more machineinstr/machineoperand stuff.
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llvm-svn: 28105
2006-05-04 18:16:01 +00:00
Chris Lattner
eb41c99161
Rename MO_VirtualRegister -> MO_Register. Clean up immediate handling.
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llvm-svn: 28104
2006-05-04 18:05:43 +00:00
Chris Lattner
c779fca289
Remove a bunch more SparcV9 specific stuff
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llvm-svn: 28093
2006-05-04 01:15:02 +00:00
Owen Anderson
71bc529dfa
Refactor TargetMachine, pushing handling of TargetData into the target-specific subclasses. This has one caller-visible change: getTargetData() now returns a pointer instead of a reference.
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This fixes PR 759.
llvm-svn: 28074
2006-05-03 01:29:57 +00:00
Nate Begeman
7ed816f900
JumpTable support! What this represents is working asm and jit support for
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x86 and ppc for 100% dense switch statements when relocations are non-PIC.
This support will be extended and enhanced in the coming days to support
PIC, and less dense forms of jump tables.
llvm-svn: 27947
2006-04-22 18:53:45 +00:00
Chris Lattner
b2b32e9283
fix spello
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llvm-svn: 27053
2006-03-24 07:15:07 +00:00
Chris Lattner
9fc969612c
TargetData doesn't know the alignment of vectors :(
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llvm-svn: 26884
2006-03-20 01:51:46 +00:00
Chris Lattner
da5f77e3cf
Move some simple-sched-specific instance vars to the simple scheduler.
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llvm-svn: 26690
2006-03-10 07:42:02 +00:00
Chris Lattner
ec2c5aa0bb
prune #includes
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llvm-svn: 26689
2006-03-10 07:37:35 +00:00
Chris Lattner
808cc02983
move some simple scheduler methods into the simple scheduler
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llvm-svn: 26688
2006-03-10 07:35:21 +00:00
Chris Lattner
89a5a946f5
Make EmitNode take a SDNode instead of a NodeInfo*
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llvm-svn: 26687
2006-03-10 07:28:36 +00:00
Chris Lattner
3f870d581e
Move the VRBase field from NodeInfo to being a separate, explicit, map.
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llvm-svn: 26686
2006-03-10 07:25:12 +00:00
Chris Lattner
ed528a5652
Push PrepareNodeInfo/IdentifyGroups down the inheritance hierarchy
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llvm-svn: 26682
2006-03-10 06:34:51 +00:00
Chris Lattner
3f23d22d3f
Change the interface for getting a target HazardRecognizer to be more clean.
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llvm-svn: 26608
2006-03-08 04:25:59 +00:00
Chris Lattner
5c28fdcae8
When a hazard recognizer needs noops to be inserted, do so. This represents
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noops as null pointers in the instruction sequence.
llvm-svn: 26564
2006-03-05 23:51:47 +00:00
Evan Cheng
026fd6af96
Added an offset field to ConstantPoolSDNode.
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llvm-svn: 26371
2006-02-25 09:54:52 +00:00
Chris Lattner
22356863a0
Pass all the flags to the asm printer, not just the # operands.
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llvm-svn: 26362
2006-02-24 19:50:58 +00:00
Chris Lattner
f1e0c1f0a8
rename NumOps -> NumVals to avoid shadowing a NumOps var in an outer scope.
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Add support for addressing modes.
llvm-svn: 26361
2006-02-24 19:18:20 +00:00
Chris Lattner
e00cf77ecb
Refactor operand adding out to a new AddOperand method
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llvm-svn: 26358
2006-02-24 18:54:03 +00:00
Chris Lattner
b4951fbe82
Record all of the expanded registers in the DAG and machine instr, fixing
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several bugs in inline asm expanded operands.
llvm-svn: 26332
2006-02-23 19:21:04 +00:00
Chris Lattner
86d5e100d2
Make MachineConstantPool entries alignments explicit
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llvm-svn: 26071
2006-02-09 02:23:13 +00:00
Jeff Cohen
4f433dafa5
Fix VC++ warning.
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llvm-svn: 25975
2006-02-04 16:20:31 +00:00
Evan Cheng
062ac6e46b
Get rid of some memory leaks identified by Valgrind
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llvm-svn: 25960
2006-02-04 06:49:00 +00:00
Chris Lattner
013f5fc2fa
Add initial support for immediates. This allows us to compile this:
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int %rlwnm(int %A, int %B) {
%C = call int asm "rlwnm $0, $1, $2, $3, $4", "=r,r,r,n,n"(int %A, int %B, int 4, int 17)
ret int %C
}
into:
_rlwnm:
or r2, r3, r3
or r3, r4, r4
rlwnm r2, r2, r3, 4, 17 ;; note the immediates :)
or r3, r2, r2
blr
llvm-svn: 25955
2006-02-04 02:26:14 +00:00
Evan Cheng
f115c17f23
Allow the specification of explicit alignments for constant pool entries.
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llvm-svn: 25855
2006-01-31 22:23:14 +00:00
Chris Lattner
e113238f5c
Handle physreg input/outputs. We now compile this:
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int %test_cpuid(int %op) {
%B = alloca int
%C = alloca int
%D = alloca int
%A = call int asm "cpuid", "=eax,==ebx,==ecx,==edx,eax"(int* %B, int* %C, int* %D, int %op)
%Bv = load int* %B
%Cv = load int* %C
%Dv = load int* %D
%x = add int %A, %Bv
%y = add int %x, %Cv
%z = add int %y, %Dv
ret int %z
}
to this:
_test_cpuid:
sub %ESP, 16
mov DWORD PTR [%ESP], %EBX
mov %EAX, DWORD PTR [%ESP + 20]
cpuid
mov DWORD PTR [%ESP + 8], %ECX
mov DWORD PTR [%ESP + 12], %EBX
mov DWORD PTR [%ESP + 4], %EDX
mov %ECX, DWORD PTR [%ESP + 12]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 8]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 4]
add %EAX, %ECX
mov %EBX, DWORD PTR [%ESP]
add %ESP, 16
ret
... note the proper register allocation. :)
it is unclear to me why the loads aren't folded into the adds.
llvm-svn: 25827
2006-01-31 02:03:41 +00:00
Chris Lattner
a1769576f0
Teach the scheduler to emit the appropriate INLINEASM MachineInstr for an
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ISD::INLINEASM node.
llvm-svn: 25668
2006-01-26 23:28:04 +00:00
Evan Cheng
168b8c5b29
No need to keep track of top and bottom nodes in a group since the vector is
...
already in order. Thanks Jim for pointing it out.
llvm-svn: 25608
2006-01-25 18:54:24 +00:00
Evan Cheng
d95c4530e7
Keep track of bottom / top element of a set of flagged nodes.
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llvm-svn: 25600
2006-01-25 09:13:41 +00:00
Evan Cheng
37c62244a6
Factor out more instruction scheduler code to the base class.
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llvm-svn: 25532
2006-01-23 07:01:07 +00:00
Evan Cheng
4a57a7551f
Do some code refactoring on Jim's scheduler in preparation of the new list
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scheduler.
llvm-svn: 25493
2006-01-21 02:32:06 +00:00
Duraid Madina
b9197e021f
purity++
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llvm-svn: 25041
2005-12-29 05:59:19 +00:00
Jim Laskey
d82881490c
Disengage DEBUG_LOC from non-PPC targets.
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llvm-svn: 24919
2005-12-21 20:51:37 +00:00
Jim Laskey
2f4c62c51a
Amend comment.
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llvm-svn: 24861
2005-12-19 16:32:26 +00:00