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Commit Graph

182481 Commits

Author SHA1 Message Date
Vedant Kumar
a301a2d9c0 [IR] Consolidate fixed metadata kind definitions (NFC)
Put the list of fixed metadata kinds in one place.

Testing: check-llvm with+without LLVM_ENABLE_MODULES=On

Differential Revision: https://reviews.llvm.org/D64437

llvm-svn: 367257
2019-07-29 20:24:20 +00:00
Jinsong Ji
164191afaa [PowerPC][NFC]Fix a typo in comment.
llvm-svn: 367252
2019-07-29 19:27:54 +00:00
Craig Topper
cde5f14770 [X86] Fix typo in comment. We're looking at a right shift not a left shift. NFC
llvm-svn: 367251
2019-07-29 19:22:51 +00:00
Anusha Basana
8df3777583 [llvm-lipo] Implement -replace
Replaces specified architecture in universal binary input file with
slice from the file_name argument passed into the replace command.

Differential Revision: https://reviews.llvm.org/D65247

llvm-svn: 367248
2019-07-29 18:46:34 +00:00
Vitaly Buka
08e492dcba gn build: Merge r367071
> llvm-svn: 366289

llvm-svn: 367245
2019-07-29 17:48:02 +00:00
David Bolvansky
7065b45db3 [UpdateTestChecks] Emit warning when invalid value for -check-prefix(es) option
Summary:
The script is silent for the following issue:
FileCheck %s -check-prefix=CHECK,POPCOUNT

FileCheck will catch it later, but I think we can warn here too.

Now it warns:
 ./update_llc_test_checks.py file.ll 
WARNING: Supplied prefix 'CHECK,POPCOUNT' is invalid. Prefix must contain only alphanumeric characters, hyphens and underscores. Did you mean --check-prefixes=CHECK,POPCOUNT?



Reviewers: lebedev.ri, spatel, RKSimon, craig.topper, nikic, gbedwell

Reviewed By: RKSimon

Subscribers: llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D64589

llvm-svn: 367244
2019-07-29 17:41:00 +00:00
Francis Visoiu Mistrih
289cd6a35a [Remarks] Update error message format string
All the clang-cmake-armv{7,8} bots are failing this test. This is an
attempt to fix this.

llvm-svn: 367243
2019-07-29 17:40:34 +00:00
Peter Collingbourne
4fdbd871d6 ThinLTOBitcodeWriter: Include globals associated with type metadata globals in the merged module.
Globals that are associated with globals with type metadata need to appear
in the merged module because they will reference the global's section directly.

Differential Revision: https://reviews.llvm.org/D65312

llvm-svn: 367242
2019-07-29 17:22:40 +00:00
Simon Pilgrim
23807f6c14 [X86] resolveTargetShuffleInputs - add depth to limit recursion.
Avoids slow downs from calls to ComputeNumSignBits/computeKnownBits going too deep.

llvm-svn: 367240
2019-07-29 17:17:58 +00:00
Tom Stellard
39b9cb37fc AMDGPU/LoadStoreOptimizer: combine MMOs when merging instructions
Summary:
The LoadStoreOptimizer was creating instructions with 2
MachineMemOperands, which meant they were assumed to alias with all other instructions,
because MachineInstr:mayAlias() returns true when an instruction has multiple
MachineMemOperands.

This was preventing these instructions from being merged again, and was
giving the scheduler less freedom to reorder them.

Reviewers: arsenm, nhaehnle

Reviewed By: arsenm

Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D65036

llvm-svn: 367237
2019-07-29 16:40:58 +00:00
Sergey Dmitriev
1293d9c5d4 [llvm-objcopy] Improve --add-section argument string parsing
Differential Revision: https://reviews.llvm.org/D65346

llvm-svn: 367236
2019-07-29 16:22:40 +00:00
Jay Foad
5c82528d1a [AMDGPU] Fix typo in error message
llvm-svn: 367235
2019-07-29 16:17:13 +00:00
Cameron McInally
f3dc8beb2f [NFC][FPEnv] Pre-commit tests for canonicalize negated operand of fdiv.
llvm-svn: 367233
2019-07-29 16:09:56 +00:00
Simon Pilgrim
ce42309de5 [X86] combineX86ShufflesRecursively - start recursion at depth = 0. NFCI.
As discussed on rL367171, we have a problem where the depth recursion used in combineX86ShufflesRecursively was subtly different to computeKnownBits etc. - it starts at Depth=1 instead of Depth=0 like the others and has a different maximum recursion depth.

This NFC patch fixes the recursion depth to start at 0, so we can more easily reuse depth values in calls from combineX86ShufflesRecursively and its helper functions in computeKnownBits etc.

llvm-svn: 367232
2019-07-29 15:57:06 +00:00
Francis Visoiu Mistrih
ba092cec89 [RISCV] Fix uninitialized variable after call to evaluateConstantImm
For llvm/test/MC/RISCV/rv64i-aliases-invalid.s, UBSan reports:

lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:371:9: runtime error:
load of value 3879186881, which is not a valid value for type
'RISCVMCExpr::VariantKind'
SUMMARY: UndefinedBehaviorSanitizer: undefined-behavior
lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:371:9 in

It turns out that evaluateConstantImm does not set `VK` and it remains
unitialized when doing comparisons in `isImmXLenLI()`.

Differential Revision: https://reviews.llvm.org/D65347

llvm-svn: 367230
2019-07-29 15:52:13 +00:00
Sanjay Patel
e48fd87328 [InstCombine] fold fadd+fneg with fdiv/fmul betweena
The backend already does this via isNegatibleForFree(),
but we may want to alter the fneg IR canonicalizations
that currently exist, so we need to try harder to fold
fneg in IR to avoid regressions.

llvm-svn: 367227
2019-07-29 13:50:25 +00:00
Hideto Ueno
98b930d587 [ValueTracking] Remove volatile check in isGuaranteedToTransferExecutionToSuccessor
Summary: As clarified in D53184, volatile load and store do not trap. Therefore, we should remove volatile checks for instructions in  `isGuaranteedToTransferExecutionToSuccessor`.

Reviewers: jdoerfert, efriedma, nikic

Reviewed By: nikic

Subscribers: hiraditya, jfb, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D65375

llvm-svn: 367226
2019-07-29 13:35:34 +00:00
Sanjay Patel
c7053c7daf [InstCombine] reduce code for fadd with fneg operand; NFC
llvm-svn: 367224
2019-07-29 13:20:46 +00:00
Sanjay Patel
8bbdc1d9fe [InstCombine] add tests for fadd with negated operand; NFC
llvm-svn: 367222
2019-07-29 12:49:36 +00:00
Jay Foad
f33ab20b69 [AMDGPU] Add amdgpu_kernel for consistency with other tests
llvm-svn: 367221
2019-07-29 11:48:17 +00:00
Simon Pilgrim
3c0bd0262f [DAGCombine] narrowInsertExtractVectorBinOp - early out for binops that change value type. NFCI.
This is implicit in the value type checks in getSubVectorSrc - this just makes it upfront and obvious.

llvm-svn: 367220
2019-07-29 11:34:45 +00:00
Jay Foad
4b1a7112ea [DivergenceAnalysis] Add methods for querying divergence at use
Summary:
The existing isDivergent(Value) methods query whether a value is
divergent at its definition. However even if a value is uniform at its
definition, a use of it in another basic block can be divergent because
of divergent control flow between the def and the use.

This patch adds new isDivergent(Use) methods to DivergenceAnalysis,
LegacyDivergenceAnalysis and GPUDivergenceAnalysis.

This might allow D63953 or other similar workarounds to be removed.

Reviewers: alex-t, nhaehnle, arsenm, rtaylor, rampitec, simoll, jingyue

Reviewed By: nhaehnle

Subscribers: jfb, jvesely, wdng, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D65141

llvm-svn: 367218
2019-07-29 10:22:09 +00:00
Simon Pilgrim
ff7ffe2345 [SystemZ] Regenerate <8 x i31> store test
To help show the diffs from an upcoming SimplifyDemandedBits patch.

llvm-svn: 367216
2019-07-29 09:49:23 +00:00
Hans Wennborg
ba8165197b Mark test/MC/RISCV/rv{32,64}i-aliases-invalid.s unsupported also on Windows
Because they fail there too.

FAIL: LLVM :: MC/RISCV/rv32i-aliases-invalid.s (24397 of 32659)
******************** TEST 'LLVM :: MC/RISCV/rv32i-aliases-invalid.s' FAILED ********************
Script:
--
: 'RUN: at line 2';   not c:\src\llvm.monorepo\build.release2\bin\llvm-mc.exe C:\src\llvm.monorepo\llvm\test\MC\RISCV\rv32i-aliases-invalid.s -triple=riscv32 -riscv-no-aliases 2>&1 | c:\src\llvm.monorepo\build.release2\bin\filecheck.exe C:\src\llvm.monorepo\llvm\test\MC\RISCV\rv32i-aliases-invalid.s
: 'RUN: at line 3';   not c:\src\llvm.monorepo\build.release2\bin\llvm-mc.exe C:\src\llvm.monorepo\llvm\test\MC\RISCV\rv32i-aliases-invalid.s -triple=riscv32 2>&1 | c:\src\llvm.monorepo\build.release2\bin\filecheck.exe C:\src\llvm.monorepo\llvm\test\MC\RISCV\rv32i-aliases-invalid.s
--
Exit Code: 1

Command Output (stdout):
--
$ ":" "RUN: at line 2"
$ "not" "c:\src\llvm.monorepo\build.release2\bin\llvm-mc.exe" "C:\src\llvm.monorepo\llvm\test\MC\RISCV\rv32i-aliases-invalid.s" "-triple=riscv32" "-riscv-no-aliases"
$ "c:\src\llvm.monorepo\build.release2\bin\filecheck.exe" "C:\src\llvm.monorepo\llvm\test\MC\RISCV\rv32i-aliases-invalid.s"
C:\src\llvm.monorepo\llvm\test\MC\RISCV\rv32i-aliases-invalid.s:10:21: error: CHECK: expected string not found in input
li t4, foo # CHECK: :[[@LINE]]:8: error: immediate must be an integer in the range [-2147483648, 4294967295]
                    ^
<stdin>:5:1: note: scanning from here
li x0, -2147483649 # CHECK: :[[@LINE]]:8: error: immediate must be an integer in the range [-2147483648, 4294967295]
^
<stdin>:5:1: note: with "@LINE" equal to "10"
li x0, -2147483649 # CHECK: :[[@LINE]]:8: error: immediate must be an integer in the range [-2147483648, 4294967295]
^
<stdin>:5:38: note: possible intended match here
li x0, -2147483649 # CHECK: :[[@LINE]]:8: error: immediate must be an integer in the range [-2147483648, 4294967295]
                                     ^

error: command failed with exit status: 1

--

--
********************
Testing: 0 .. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: LLVM :: MC/RISCV/rv64i-aliases-invalid.s (24416 of 32659)
******************** TEST 'LLVM :: MC/RISCV/rv64i-aliases-invalid.s' FAILED ********************
Script:
--
: 'RUN: at line 2';   not c:\src\llvm.monorepo\build.release2\bin\llvm-mc.exe C:\src\llvm.monorepo\llvm\test\MC\RISCV\rv64i-aliases-invalid.s -triple=riscv64 -riscv-no-aliases 2>&1 | c:\src\llvm.monorepo\build.release2\bin\filecheck.exe C:\src\llvm.monorepo\llvm\test\MC\RISCV\rv64i-aliases-invalid.s
: 'RUN: at line 3';   not c:\src\llvm.monorepo\build.release2\bin\llvm-mc.exe C:\src\llvm.monorepo\llvm\test\MC\RISCV\rv64i-aliases-invalid.s -triple=riscv64 2>&1 | c:\src\llvm.monorepo\build.release2\bin\filecheck.exe C:\src\llvm.monorepo\llvm\test\MC\RISCV\rv64i-aliases-invalid.s
--
Exit Code: 1

Command Output (stdout):
--
$ ":" "RUN: at line 2"
$ "not" "c:\src\llvm.monorepo\build.release2\bin\llvm-mc.exe" "C:\src\llvm.monorepo\llvm\test\MC\RISCV\rv64i-aliases-invalid.s" "-triple=riscv64" "-riscv-no-aliases"
$ "c:\src\llvm.monorepo\build.release2\bin\filecheck.exe" "C:\src\llvm.monorepo\llvm\test\MC\RISCV\rv64i-aliases-invalid.s"
C:\src\llvm.monorepo\llvm\test\MC\RISCV\rv64i-aliases-invalid.s:6:21: error: CHECK: expected string not found in input
li t4, foo # CHECK: :[[@LINE]]:8: error: operand must be a constant 64-bit integer
                    ^
<stdin>:2:1: note: scanning from here
li t5, 0x10000000000000000 # CHECK: :[[@LINE]]:8: error: unknown operand
^
<stdin>:2:1: note: with "@LINE" equal to "6"
li t5, 0x10000000000000000 # CHECK: :[[@LINE]]:8: error: unknown operand
^
<stdin>:13:67: note: possible intended match here
C:\src\llvm.monorepo\llvm\test\MC\RISCV\rv64i-aliases-invalid.s:12:13: error: immediate must be an integer in the range [0, 63]
                                                                  ^

error: command failed with exit status: 1
llvm-svn: 367215
2019-07-29 09:49:04 +00:00
Simon Pilgrim
5b18bc5eaa [ARM] Regenerate rotation tests
llvm-svn: 367214
2019-07-29 09:48:07 +00:00
Simon Pilgrim
2df3a934db [AMDGPU] Regenerate v2i16 insertelement tests.
To help show the diffs from an upcoming SimplifyDemandedBits patch.

llvm-svn: 367213
2019-07-29 09:47:07 +00:00
Sam Parker
28aee028a4 [NFC][ARM[ParallelDSP] Cleanup of BinOpChain
- Remove some unused typedefs.
- Rename BinOpChain struct to MulCandidate.
- Remove the size method of MulCandidate.
- Store only the first input of the ValueList provided to
  MulCandidate, as it's the only value we care about. This means we
  don't have to perform any ugly (and unnecessary) iterations of the 
  list later on.

llvm-svn: 367208
2019-07-29 08:41:51 +00:00
David Stuttard
139c586a18 [AMDGPU] Enable v4f16 and above for v_pk_fma instructions
Summary:
If isel is presented with <2 x half> vectors then it will correctly select
v_pk_fma style instructions.
If isel is presented with e.g. <4 x half> vectors it will scalarize, unlike for
other instruction types (such as fadd, fmul etc.)

Added extra support to enable this. Updated one of the tests to include a test
for this (as well as extending the test to GFX9)

Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, tpr, t-tye, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D65325

Change-Id: I50a4577a3f8223fb53992af3b7d26121f65b71ee
llvm-svn: 367206
2019-07-29 08:15:10 +00:00
Sam Parker
a17489ccd4 [NFC][ARM][ParallelDSP] Remove AreSymmetrical
We explicitly search for a parallel mac and we only care about its
inputs, checking for symmetry doesn't add anything here.

llvm-svn: 367205
2019-07-29 08:12:24 +00:00
Sam Parker
7036456dcc [NFC][ARM][ParallelDSP] Remove PopulateLoads
We no longer have to check what loads are used, all this
is performed at the start of the transform, so it's not
doing anything now.

llvm-svn: 367204
2019-07-29 08:07:23 +00:00
George Rimar
a4aab3962c [obj2yaml] - Report a error when unable to resolve a sh_link reference properly.
Because of a bug we did not report a error in the case
shown in the test. With this patch we do.

Differential revision: https://reviews.llvm.org/D65214

llvm-svn: 367203
2019-07-29 07:58:29 +00:00
George Rimar
0c6435db17 [llvm-objcopy] - Reimplement strip-dwo-groups.test to stop using the precompiled object.
When llvm-copy removes .dwo sections the index of symbol table,
the indices of the symbols and the indices of the sections which go
after the removed ones changes. That affects on SHT_GROUP sections,
which needs to be updated.

Initially this test used a precompiled object, I rewrote it to use YAML
and improved a bit.

Differential revision: https://reviews.llvm.org/D65273

llvm-svn: 367202
2019-07-29 07:55:39 +00:00
Craig Topper
07f86f2ad5 [X86] Don't use PMADDWD for vector add reductions of multiplies if the mul inputs have an additional user.
The pmaddwd inserts a truncate, if that truncate would end up
creating additional instructions instead of making a zext
narrower, then we shouldn't do it.

I've restricted this to only sse4.1 targets since on prior
targets the zext will be done in stages. So the truncate will
probably not create additional instructions. Might need some
more investigation of mul shrinking and the other pmaddwd
transform to be sure this is the right decision.

There might be a slight regression on AVX1 targets due to add
splitting. Hard to say for sure. Maybe we need to look into
using the vector reduction flag to use 2 narrow loads and a
blend instead of extracting and inserting.

llvm-svn: 367198
2019-07-29 01:36:58 +00:00
Craig Topper
dc22f34998 [X86] Add test cases to show missing one use check in combineLoopMAddPattern.
llvm-svn: 367197
2019-07-29 01:36:54 +00:00
Roman Lebedev
f9e5bccad9 [NFC][InstCombine] Revisit tests in shift-amount-reassociation-with-truncation-shl.ll
llvm-svn: 367196
2019-07-28 21:31:58 +00:00
Craig Topper
ea59641915 [X86] In combineLoopMAddPattern and combineLoopSADPattern, preserve the vector reduction flag on the final add. Handle unrolled loops by letting DAG combine revisit.
This reverts r340478 and r340631 and replaces them with a simpler
method of just letting DAG combine revisit the nodes to handle
the other operand.

llvm-svn: 367195
2019-07-28 18:45:42 +00:00
Sanjay Patel
81938dd934 [InstCombine] fold fsub+fneg with fdiv/fmul between
The backend already does this via isNegatibleForFree(),
but we may want to alter the fneg IR canonicalizations
that currently exist, so we need to try harder to fold
fneg in IR to avoid regressions.

llvm-svn: 367194
2019-07-28 17:10:06 +00:00
David Green
54d39022f7 [ARM] MVE VPNOT
This adds the patterns required to transform xor P0, -1 to a VPNOT. The
instruction operands have to change a little for this, adding an in and an out
VCCR reg and using a custom DecodeMVEVPNOT for the decode.

Differential Revision: https://reviews.llvm.org/D65133

llvm-svn: 367192
2019-07-28 14:07:48 +00:00
David Green
d3183024b0 [ARM] Better patterns for fp <> predicate vectors
These are some better patterns for converting between predicates and floating
points. Much like the extends, we select "1"/"-1" or "0" depending on the
predicate value. Or we perform a compare against 0 to convert to a predicate.

Differential Revision: https://reviews.llvm.org/D65103

llvm-svn: 367191
2019-07-28 13:53:39 +00:00
Roman Lebedev
be00ed3113 [NFC][InstCombine] Shift amount reassociation: can have trunc between shl's
https://rise4fun.com/Alive/OQbM
Not so simple for lshr/ashr, so those maybe later.

https://bugs.llvm.org/show_bug.cgi?id=42391

llvm-svn: 367189
2019-07-28 13:13:46 +00:00
Hideto Ueno
64b73b960d [Attributor] Deduce "align" attribute
Summary:
Deduce "align" attribute in attributor.

Reviewers: jdoerfert, sstefan1

Reviewed By: jdoerfert

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D64152

llvm-svn: 367187
2019-07-28 07:04:01 +00:00
Hideto Ueno
1bdebca93d [IR] Fix getPointerAlignment for CallBase
Summary:
In current getPointerAlignemnt implementation, CallBase.getPointerAlignement(..) checks only parameter attriutes in the callsite.  For example,

```
declare align 8 i8* @foo()

define void @bar() {
    %a = tail call align 8 i8* @foo() ; getPointerAlignment returns 8
    %b = tail call i8* @foo() ; getPointerAlignemnt returns 0
    ret void
}
```

This patch will fix the problem.

Reviewers: jdoerfert

Reviewed By: jdoerfert

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D65281

llvm-svn: 367185
2019-07-28 06:17:46 +00:00
Hideto Ueno
97957b2f53 [FunctionAttrs] Annotate "willreturn" for intrinsics
Summary:
In D62801, new function attribute `willreturn` was introduced. In short, a function with `willreturn` is guaranteed to come back to the call site(more precise definition is in LangRef).

In this patch, willreturn is annotated for LLVM intrinsics.

Reviewers: jdoerfert

Reviewed By: jdoerfert

Subscribers: jvesely, nhaehnle, sstefan1, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D64904

llvm-svn: 367184
2019-07-28 06:09:56 +00:00
Simon Pilgrim
f05799cd65 [DAGCombine] narrowInsertExtractVectorBinOp - early out for illegal op. NFCI.
If the subvector binop is illegal then early-out and avoid the subvector searches.

llvm-svn: 367181
2019-07-27 19:42:58 +00:00
Joerg Sonnenberger
cd5d699ac4 Stricter check for the memory access.
The current pattern would trigger for scheduling changes of the
post-load computation, since those are commutable with the inline asm.
Avoid this by explicitly check the order of load vs asm block.

llvm-svn: 367180
2019-07-27 18:57:59 +00:00
Simon Pilgrim
a0b4d6a6d3 Regenerate UXTB tests
llvm-svn: 367179
2019-07-27 18:44:15 +00:00
Simon Pilgrim
f99e2191a9 [AMDGPU] Regenerate tests.
To help show the diffs from an upcoming SimplifyDemandedBits patch.

llvm-svn: 367175
2019-07-27 14:32:23 +00:00
Simon Pilgrim
8275bda10b [TargetLowering] SimplifyMultipleUseDemandedBits - add BITCAST pass through support (Reapplied)
This allows us to peek through BITCASTs, attempt to simplify the source operand, and then bitcast back.

This reapplies rL367091 which was reverted at rL367118 - we were inconsistently peeking through the bitcasts to the source value.

Fixes PR42777

llvm-svn: 367174
2019-07-27 14:11:59 +00:00
Sanjay Patel
ea33113c3e [InstSimplify] remove quadratic time looping (PR42771)
The test case from:
https://bugs.llvm.org/show_bug.cgi?id=42771
...shows a ~30x slowdown caused by the awkward loop iteration (rL207302) that is
seemingly done just to avoid invalidating the instruction iterator. We can instead
delay instruction deletion until we reach the end of the block (or we could delay
until we reach the end of all blocks).

There's a test diff here for a degenerate case with llvm.assume that is not
meaningful in itself, but serves to verify this change in logic.

This change probably doesn't result in much overall compile-time improvement
because we call '-instsimplify' as a standalone pass only once in the standard
-O2 opt pipeline currently.

Differential Revision: https://reviews.llvm.org/D65336

llvm-svn: 367173
2019-07-27 14:05:51 +00:00
Simon Pilgrim
343a2c6757 [X86][SSE] Replace PMULDQ GetDemandedBits combine with SimplifyMultipleUseDemandedBits handler (Reapplied)
Recommit rL367100 which was reverted at rL367141. Until PR42777 is fixed, we no longer get the benefits of peeking through bitcasts but it does still remove a GetDemandedBits user and gives us the equivalent combines.

llvm-svn: 367172
2019-07-27 13:30:29 +00:00