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164416 Commits

Author SHA1 Message Date
Lang Hames
a779e0266f [ORC] Lookup now returns an error if any symbols are not found.
Also tightens the behavior of ExecutionSession::failQuery. Queries can usually
only be failed by marking a symbol as failed-to-materialize, but
ExecutionSession::failQuery provides a second route, and both routes may be
executed from different threads. In the case that a query has already been
failed due to a materialization error, ExecutionSession::failQuery will
direct the error to ExecutionSession::reportError instead.

llvm-svn: 332898
2018-05-21 21:11:21 +00:00
Lang Hames
2df7bb6df6 [ORC] Remove the optional MaterializationResponsibility argument from lookup.
The lookup function provides blocking symbol resolution for JIT clients (not
layers themselves) so it does not need to track symbol dependencies via a
MaterializationResponsibility.

llvm-svn: 332897
2018-05-21 21:11:21 +00:00
Lang Hames
e81f95d26c [ORC] Add IRLayer and ObjectLayer interfaces and related MaterializationUnits.
llvm-svn: 332896
2018-05-21 21:11:13 +00:00
Craig Topper
ac8a899f0f [DAGCombiner] Use computeKnownBits to match rotate patterns that have had their amount masking modified by simplifyDemandedBits
SimplifyDemandedBits can remove bits from the masks for the shift amounts we need to see to detect rotates.

This patch uses zeroes from computeKnownBits to fill in some of these mask bits to make the match work.

As currently written this calls computeKnownBits even when the mask hasn't been simplified because it made the code simpler. If we're worried about compile time performance we can improve this.

I know we're talking about making a rotate intrinsic, but hopefully we can go ahead and do this change and just make sure the rotate intrinsic also handles it.

Differential Revision: https://reviews.llvm.org/D47116

llvm-svn: 332895
2018-05-21 21:09:18 +00:00
Sanjay Patel
93fe0f0f18 [InstCombine] regenerate checks; NFC
llvm-svn: 332894
2018-05-21 21:09:14 +00:00
Reid Kleckner
0f1c09ea4a [X86] Simplify some X86 address mode folding code, NFCI
This code should really do exactly the same thing for 32-bit x86 and
64-bit small code models, with the exception that RIP-relative
addressing can't use base and index registers.

llvm-svn: 332893
2018-05-21 21:03:19 +00:00
Craig Topper
f30a9684e6 [X86] Remove some unneeded check lines that I copy and pasted when I made vector tests from some scalar test cases.
llvm-svn: 332892
2018-05-21 21:01:13 +00:00
Craig Topper
7333222486 [X86] Remove masking from vpternlog intrinsics. Use a select in IR instead.
This removes 6 intrinsics since we no longer need separate mask and maskz intrinsics.

Differential Revision: https://reviews.llvm.org/D47124

llvm-svn: 332890
2018-05-21 20:58:09 +00:00
Peter Collingbourne
283082c7de Fix a make_unique ambiguity.
llvm-svn: 332889
2018-05-21 20:56:28 +00:00
Sanjay Patel
8e8c24d54c [InstCombine] remove fptrunc (select) code; NFCI
This pattern is handled within commonCastTransforms(),
so the code here is dead AFAICT.

llvm-svn: 332887
2018-05-21 20:39:35 +00:00
Peter Collingbourne
13afbf5f9e LTO: Replace split dwarf implementation that uses objcopy with one that uses direct emission.
Part of PR37466.

Differential Revision: https://reviews.llvm.org/D47091

llvm-svn: 332884
2018-05-21 20:26:49 +00:00
Sanjay Patel
924829434c [InstCombine] add tests for cast-of-select; NFC
In all cases, we're pulling the cast above the select.
That's not a good canonicalization if we're creating 
a select that then mismatches the operand size of its
condition.

llvm-svn: 332883
2018-05-21 20:23:58 +00:00
Peter Collingbourne
7f9b89f0e2 CodeGen: Add a dwo output file argument to addPassesToEmitFile and hook it up to dwo output.
Part of PR37466.

Differential Revision: https://reviews.llvm.org/D47089

llvm-svn: 332881
2018-05-21 20:16:41 +00:00
Reid Kleckner
fd0e6cf515 Remove CMake workaround for LLD PR24476 which is no longer needed
llvm-svn: 332880
2018-05-21 20:14:46 +00:00
Brian Gesiak
ec770fb11a [DebugInfo] Fix typo "DWARG" in test comment (NFC)
Summary:
The correct spelling is "DWARF", the debugging format, not "DWARG".
The typo is in a (not executed by lit) comment in a test file, so
fixing it does not result in any functional change.

Test Plan: check-llvm, just in case

llvm-svn: 332878
2018-05-21 19:48:27 +00:00
Peter Collingbourne
dfa516bd25 MC: Introduce an ELF dwo object writer and teach llvm-mc about it.
Part of PR37466.

Differential Revision: https://reviews.llvm.org/D47051

llvm-svn: 332875
2018-05-21 19:44:54 +00:00
Matt Arsenault
4772695a5e AMDGPU: Update GCCBuiltin names for DS FP atomic intrinsics
llvm-svn: 332874
2018-05-21 19:43:02 +00:00
Jonas Devlieghere
92f8a3c24d [DebugInfo] Use absolute addresses in location lists
Rather than relying on the user to do the address calculating in
DW_AT_location we should just dump the absolute address.

rdar://problem/38513870

Differential revision: https://reviews.llvm.org/D47152

llvm-svn: 332873
2018-05-21 19:36:54 +00:00
Craig Topper
2d0d4e82be [X86] Add test cases for D47012.
Patch by Thomasz Krupa.

llvm-svn: 332872
2018-05-21 19:33:42 +00:00
Peter Collingbourne
191b23121c MC: Extract a derived class from ELFObjectWriter. NFCI.
This class will be used to create regular, non-split ELF files.

Part of PR37466.

Differential Revision: https://reviews.llvm.org/D47049

llvm-svn: 332870
2018-05-21 19:30:59 +00:00
Craig Topper
fdc2f308f7 [X86] Add test cases for missed vector rotate matching due to SimplifyDemandedBits interfering with the AND masks
As requested in D47116

llvm-svn: 332869
2018-05-21 19:27:50 +00:00
Peter Collingbourne
799b49b89d MC: Separate creating a generic object writer from creating a target object writer. NFCI.
With this we gain a little flexibility in how the generic object
writer is created.

Part of PR37466.

Differential Revision: https://reviews.llvm.org/D47045

llvm-svn: 332868
2018-05-21 19:20:29 +00:00
Peter Collingbourne
defdefcf7f MC: Extract ELFObjectWriter's ELF writing functionality into an ELFWriter class. NFCI.
The idea is that we will be able to use this class to create multiple
files.

Differential Revision: https://reviews.llvm.org/D47048

llvm-svn: 332867
2018-05-21 19:18:28 +00:00
Peter Collingbourne
492891ef83 Fix ubsan bounds check failure.
llvm-svn: 332866
2018-05-21 19:09:47 +00:00
Craig Topper
58b84296b9 [EarlyCSE] Improve EarlyCSE of some absolute value cases.
Change matchSelectPattern to return X and -X for ABS/NABS in a well defined order. Adjust EarlyCSE to account for this. Ensure the SPF result is some kind of min/max and not abs/nabs in one place in InstCombine that made me nervous.

Prevously we returned the two operands of the compare part of the abs pattern. The RHS is always going to be a 0i, 1 or -1 constant. This isn't a very meaningful thing to return for any one. There's also some freedom in the abs pattern as to what happens when the value is equal to 0. This freedom led to early cse failing to match when different constants were used in otherwise equivalent operations. By returning the input and its negation in a defined order we can ensure an exact match. This also makes sure both patterns use the exact same subtract instruction for the negation. I believe CSE should evebntually make this happen and properly merge the nsw/nuw flags. But I'm not familiar with CSE and what order it does things in so it seemed like it might be good to really enforce that they were the same.

Differential Revision: https://reviews.llvm.org/D47037

llvm-svn: 332865
2018-05-21 18:42:42 +00:00
Peter Collingbourne
a801850e26 MC: Remove stream and output functions from MCObjectWriter. NFCI.
Part of PR37466.

Differential Revision: https://reviews.llvm.org/D47043

llvm-svn: 332864
2018-05-21 18:28:57 +00:00
Peter Collingbourne
c40026e33c MC: Have the object writers return the number of bytes written. NFCI.
This removes the last external use of the stream.

Part of PR37466.

Differential Revision: https://reviews.llvm.org/D47042

llvm-svn: 332863
2018-05-21 18:23:50 +00:00
Stanislav Mekhanoshin
7e50efd55e [AMDGPU] Add divergence analysis as a dependency for ISel
AMDGPUDAGToDAGISel adds DivergenceAnalysis in getAnalysisUsage
but does not list it in pass dependencies which may lead to
crash.

Differential Revision: https://reviews.llvm.org/D47151

llvm-svn: 332862
2018-05-21 18:18:52 +00:00
Peter Collingbourne
c6202abed0 MC: Change object writers to use endian::Writer. NFCI.
Part of PR37466.

Differential Revision: https://reviews.llvm.org/D47040

llvm-svn: 332861
2018-05-21 18:17:42 +00:00
Diego Caballero
300aaa4d61 [VPlan] Reland r332654 and silence unused func warning
r332654 was reverted due to an unused function warning in
release build. This commit includes the same code with the
warning silenced.

Differential Revision: https://reviews.llvm.org/D44338

llvm-svn: 332860
2018-05-21 18:14:23 +00:00
Peter Collingbourne
8c1bb0e1c2 MC: Change MCAssembler::writeSectionData and writeFragmentPadding to take a raw_ostream. NFCI.
Also clean up a couple of hacks where we were writing the section
contents to another stream by setting the object writer's stream,
writing and setting it back.

Part of PR37466.

Differential Revision: https://reviews.llvm.org/D47038

llvm-svn: 332858
2018-05-21 18:11:35 +00:00
Peter Collingbourne
caacbd9d09 MC: Change MCAsmBackend::writeNopData() to take a raw_ostream instead of an MCObjectWriter. NFCI.
To make this work I needed to add an endianness field to MCAsmBackend
so that writeNopData() implementations know which endianness to use.

Part of PR37466.

Differential Revision: https://reviews.llvm.org/D47035

llvm-svn: 332857
2018-05-21 17:57:19 +00:00
Tom Stellard
7c3584c4d4 AMDGPU/GlobalISel: Address post-commit review comments for r332379
MCRegisterInfo::getPhysRegSize() will be deprecated.

llvm-svn: 332856
2018-05-21 17:49:31 +00:00
Alexey Bataev
dd30f2354a [InstCombine] Fix PR37526: MinMax patterns produce an infinite loop.
Summary:
This patch fixes PR37526 by simplifying the newly generated LoadInst
instructions. If the pointer address is a bitcast from the pointer to
the NewType, we can just remove this extra bitcast instead of creating
the new one. This fixes the PR37526 + may speed up the whole compilation
process.

Reviewers: spatel, RKSimon, hfinkel

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D47144

llvm-svn: 332855
2018-05-21 17:46:34 +00:00
Andrea Di Biagio
36a508f010 [llvm-mca] Removed an empty line generated by the timeline view. NFC.
Also, regenerate all tests.

llvm-svn: 332853
2018-05-21 17:11:56 +00:00
Andrea Di Biagio
d65d55551b [X86][BtVer2] Add a 'J' prefix to the PRF/RCU defs. NFC
This is to keep the Jaguar model's naming convention. Processor resources all
have a 'J' prefix in the BtVer2 scheduling model.

llvm-svn: 332851
2018-05-21 16:30:26 +00:00
Robert Widmann
bfecd2d56d [LLVM-C] Add DIBuilder Bindings For ObjC Classes
Summary: Add LLVMDIBuilderCreateObjCIVar, LLVMDIBuilderCreateObjCProperty, and LLVMDIBuilderCreateInheritance to allow declaring metadata for Objective-C class hierarchies and their associated properties and instance variables.

Reviewers: whitequark, deadalnix

Reviewed By: whitequark

Subscribers: harlanhaskins, llvm-commits

Differential Revision: https://reviews.llvm.org/D47123

llvm-svn: 332850
2018-05-21 16:27:35 +00:00
Lama Saba
1bc8b49d1c [X86] - Avoid SFB pass - fix bug in updating the offsets for newly created copies
Change-Id: I169ab6fe7e187727c0298c2a1e2868a683f3e688
llvm-svn: 332849
2018-05-21 16:23:16 +00:00
James Henderson
19abcdf38f [DWARF] Refactor callback usage for .debug_line error handling
Change the "recoverable" error callback to take an Error instaed of a
string.

Reviewed by: JDevlieghere

Differential Revision: https://reviews.llvm.org/D46831

llvm-svn: 332845
2018-05-21 15:30:54 +00:00
Simon Pilgrim
7479a1b6ec [X86][SSE] Add an assert to ensure that rotation amount is converted to a scale
Missed in rL332832 where we added SSE v4i32 rotations for PR37426.

llvm-svn: 332844
2018-05-21 15:17:23 +00:00
Tim Northover
080f8761dc ARM: be conservative when asked load/store alignment of weird type.
Chances are we'll be asked again after type legalization, but before that point
it's better to claim misaligned accesses aren't allowed than to assert.

llvm-svn: 332840
2018-05-21 12:43:54 +00:00
Nico Weber
ebee76c11b revert r332610, it breaks cfi, see D46326
llvm-svn: 332838
2018-05-21 11:44:39 +00:00
Aleksandar Beserminji
363263c8be [mips] Revert Merge MipsLongBranch and MipsHazardSchedule passes
Revert this patch due buildbot failure.

Differential Revision: https://reviews.llvm.org/D46641

llvm-svn: 332837
2018-05-21 11:38:52 +00:00
David Green
1168eccd43 [CVP] Require DomTree for new Pass Manager
We were previously using a DT in CVP through SimplifyQuery, but not requiring it in
the new pass manager. Hence it would crash if DT was not already available. This now
gets DT directly and plumbs it through to where it is used (instead of using it
through SQ).

llvm-svn: 332836
2018-05-21 11:06:28 +00:00
Eric Christopher
8dbb727709 Fix up a few grammar issues.
llvm-svn: 332835
2018-05-21 10:27:36 +00:00
Aleksandar Beserminji
56d716f1af [mips] Merge MipsLongBranch and MipsHazardSchedule passes
MipsLongBranchPass and MipsHazardSchedule passes are joined to one pass
because of mutual conflict. When MipsHazardSchedule inserts 'nop's, it
potentially breaks some jumps, so they have to be expanded to long
branches. When some branch is expanded to long branch, it potentially
creates a hazard situation, which should be fixed by adding nops.
New pass is called MipsBranchExpansion, it combines these two passes,
and runs them alternately until one of them reports no changes were made.

Differential Revision: https://reviews.llvm.org/D46641

llvm-svn: 332834
2018-05-21 10:20:02 +00:00
Simon Pilgrim
8df0d84f3d [X86][SSE] Support v4i32 rotations (PR37426)
As suggested by Fabian on PR37426, we can use PMULUDQ to perform v4i32 vector rotations as the upper 32bits of the multiply will contain the 'wrapped' bits of the rotation.

v8i16/v16i8 rotations would be straightforward to add to lowerRotate in the future - ideally we'd mostly share code with the vector shifts lowering.

Differential Revision: https://reviews.llvm.org/D46954

llvm-svn: 332832
2018-05-21 09:45:59 +00:00
Nico Weber
ad933787f8 win: try more to fix dia tests with newer msvc versions
llvm-svn: 332828
2018-05-21 02:55:41 +00:00
Nico Weber
2d4abf2ddf win: try to fix dia tests with newer msvc versions
llvm-svn: 332827
2018-05-21 02:09:57 +00:00
Robert Widmann
805c1d4c97 [LLVM-C] Improve Bindings For Aliases
Summary: Add wrappers for a module's alias iterators and a getter and setter for the aliasee value.

Reviewers: whitequark, deadalnix

Reviewed By: whitequark

Subscribers: llvm-commits, harlanhaskins

Differential Revision: https://reviews.llvm.org/D46808

llvm-svn: 332826
2018-05-20 23:49:08 +00:00