RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-25 04:02:41 +01:00
Code Issues Projects Releases Wiki Activity
61,148 Commits 4 Branches 5 Tags 704 MiB
a96eaed21d
Commit Graph

61148 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Bill Wendling
a96eaed21d Create new accessors to get arguments for call/invoke instructions. It breaks 
encapsulation to force the users of these classes to know about the internal
data structure of the Operands structure. It also can lead to errors, like in
the MSIL writer.

llvm-svn: 105539
 2010-06-07 19:05:06 +00:00
Rafael Espindola
b93be14fa0 Misc cleanups to the gold plugin. 
llvm-svn: 105534
 2010-06-07 16:45:22 +00:00
Nate Begeman
477813692f clang codegen support 
llvm-svn: 105531
 2010-06-07 16:00:37 +00:00
Kenneth Uildriks
73367eb575 Partial specialization was not checking the callsite to make sure it was using the same constants as the specialization, leading to calls to the wrong specialization. Patch by Takumi Nakamura\! 
llvm-svn: 105528
 2010-06-05 14:50:21 +00:00
Duncan Sands
d74ac1ebe7 This bug is also present in MSVC10. Requested by Elrood on IRC. 
llvm-svn: 105527
 2010-06-05 12:40:43 +00:00
Chris Lattner
33d0622cdc revert r105521, which is breaking the buildbots with stuff like this: 
In file included from X86InstrInfo.cpp:16:
X86GenInstrInfo.inc:2789: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2790: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2792: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2793: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2808: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2809: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2816: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2817: error: integer constant is too large for 'long' type

llvm-svn: 105524
 2010-06-05 04:17:30 +00:00
Bruno Cardoso Lopes
b05131d907 Initial AVX support for some instructions. No patterns matched 
yet, only assembly encoding support.

llvm-svn: 105521
 2010-06-05 03:53:24 +00:00
Bruno Cardoso Lopes
b811561aac Teach tablegen to support 'defm' inside multiclasses. 
llvm-svn: 105519
 2010-06-05 02:11:52 +00:00
Dan Gohman
884aaf23ee Make MachineFunctionPass::createPrinterPass private, as no subclasses 
should be calling it.

llvm-svn: 105517
 2010-06-05 01:19:12 +00:00
Dale Johannesen
df4dc9ed33 Improvements to tail call code. No functional effect 
unless using -arm-tail-calls.

llvm-svn: 105515
 2010-06-05 00:51:39 +00:00
Dan Gohman
eea56e5bd8 getFoldedOffsetOf no longer does anything special with vector types. 
llvm-svn: 105514
 2010-06-05 00:47:34 +00:00
Dan Gohman
a4614e30ec No need to special-case structs here; structs are first-class now. 
llvm-svn: 105513
 2010-06-05 00:42:29 +00:00
Stuart Hastings
37ed2a9663 Revert 105492 & 105493 due to a testcase regression. Radar 7424645. 
llvm-svn: 105511
 2010-06-05 00:39:29 +00:00
Dan Gohman
1865db1b89 LSR needs to remember inserted instructions even in postinc mode, because 
there could be multiple subexpressions within a single expansion which
require insert point adjustment. This fixes PR7306.

llvm-svn: 105510
 2010-06-05 00:33:07 +00:00
Dale Johannesen
ae0a144c39 Fix some liveout handling related to tail calls, see comments. 
I don't think this ever resulted in problems on x86, but it
would on ARM.

llvm-svn: 105509
 2010-06-05 00:30:45 +00:00
Dan Gohman
e1853a7473 Implement operator== and operator!= for SetVector. 
llvm-svn: 105508
 2010-06-05 00:26:02 +00:00
Devang Patel
b8bc51b307 test case for r105504. 
Radar 8055687.

llvm-svn: 105505
 2010-06-04 23:47:41 +00:00
Evan Cheng
0fb8a935a5 Re-apply 105308 with fix. 
llvm-svn: 105502
 2010-06-04 23:28:13 +00:00
Dan Gohman
17ad6b5d21 Don't track users of undef values; they aren't interesting for 
register pressure.

llvm-svn: 105501
 2010-06-04 23:16:05 +00:00
Jim Grosbach
8e3fbf47cb Make if-conversion ignore dbg_value instructions in its analysis. rdar://7797940 
llvm-svn: 105498
 2010-06-04 23:01:26 +00:00
Nate Begeman
7a41bddd2c Handle multi-vector returns and args. 
llvm-svn: 105496
 2010-06-04 22:53:30 +00:00
Devang Patel
65088cc742 Update docs to reflect new DISubprogram elements. 
llvm-svn: 105495
 2010-06-04 22:49:55 +00:00
Stuart Hastings
eb78f8db98 Support for nested functions/classes in debug output. Radar 7424645. 
llvm-svn: 105492
 2010-06-04 22:36:03 +00:00
Devang Patel
8bf4434e6e Copy location info for current function argument from dbg.declare if respective store instruction does not have any location info. 
llvm-svn: 105490
 2010-06-04 22:27:30 +00:00
Nate Begeman
60df12eda6 Additional fixes to BuiltinsARM.def generator, on to clang codegen. 
llvm-svn: 105488
 2010-06-04 21:36:00 +00:00
Dale Johannesen
fc3c949f68 More tail call removal. 
llvm-svn: 105485
 2010-06-04 21:14:24 +00:00
Jim Grosbach
f72dafe970 Skip dbg_value instructions when scanning instructions in register scavenging. 
llvm-svn: 105481
 2010-06-04 20:18:30 +00:00
Dan Gohman
332b06bd4f Fix normalization and de-normalization of non-affine SCEVs. 
llvm-svn: 105480
 2010-06-04 19:16:34 +00:00
Jakob Stoklund Olesen
90af6a44c3 Keep track of the call instructions whose clobber lists were skipped during fast 
register allocation.

Process all of the clobber lists at the end of the function, marking the
registers as used in MachineRegisterInfo.

This is necessary in case the calls clobber callee-saved registers (sic).

llvm-svn: 105473
 2010-06-04 18:08:29 +00:00
Dale Johannesen
f47a852290 More thoroughly disable tails calls by default. 
8060143, although this doesn't fix the real problem with tail call.

llvm-svn: 105472
 2010-06-04 18:04:24 +00:00
Jim Grosbach
ab666c3d62 Another fix to prevent debug info from affecting codegen. rdar://7797940 
llvm-svn: 105470
 2010-06-04 17:57:34 +00:00
Nate Begeman
8275ffe1df Progress on generating BuiltinsARM.def, still some duplicates to work out. 
llvm-svn: 105461
 2010-06-04 07:11:25 +00:00
Nate Begeman
766330952e BuiltinsARM.def emitter, still needs a substantial bit of tweaking to lighten the load on clang. 
llvm-svn: 105456
 2010-06-04 01:26:15 +00:00
Jim Grosbach
b9367dadcf more dbg_value adjustments so debug info doesn't affect codegen 
llvm-svn: 105454
 2010-06-04 01:23:30 +00:00
Mon P Wang
f83cdf3d18 Fixed a bug during widening where we would avoid legalizing a node. When we 
replace an OpA with a widened OpB, it is possible to get new uses of OpA due to CSE
when recursively updating nodes.  Since OpA has been processed, the new uses are
not examined again.  The patch checks if this occurred and it it did, updates the
new uses of OpA to use OpB.

llvm-svn: 105453
 2010-06-04 01:20:10 +00:00
Dale Johannesen
f03ef32e4e Remove more tail calls. 
llvm-svn: 105450
 2010-06-04 01:01:24 +00:00
Dale Johannesen
0c967c579f Remove a tail call, and move some CHECKs to the 
functions where they belong.

llvm-svn: 105449
 2010-06-04 01:01:04 +00:00
Nate Begeman
b5c41fee97 Mangle __builtin_neon_* names appropriately. 
Add skeleton of support for emitting the list of prototypes for BuiltinsARM.def

llvm-svn: 105443
 2010-06-04 00:21:41 +00:00
Dan Gohman
b03730d276 No need to special-case structs here; structs are first-class now. 
llvm-svn: 105442
 2010-06-04 00:18:06 +00:00
Jim Grosbach
4064cf20dd fix typo 
llvm-svn: 105441
 2010-06-04 00:15:00 +00:00
Dan Gohman
bbd309edaa This test doesn't need the ssp attribute. 
llvm-svn: 105440
 2010-06-04 00:14:48 +00:00
Bob Wilson
2945a0ac66 For NEON vectors with 32- or 64-bit elements, select BUILD_VECTORs and 
VECTOR_SHUFFLEs to REG_SEQUENCE instructions.  The standard ISD::BUILD_VECTOR
node corresponds closely to REG_SEQUENCE but I couldn't use it here because
its operands do not get legalized.  That is pretty awful, but I guess it
makes sense for other targets.  Instead, I have added an ARM-specific version
of BUILD_VECTOR that will have its operands properly legalized.
This fixes the rest of Radar 7872877.

llvm-svn: 105439
 2010-06-04 00:04:02 +00:00
Dale Johannesen
3492389308 Remove tail call. A tail call version will follow. 
llvm-svn: 105438
 2010-06-04 00:03:37 +00:00
Bob Wilson
f28f6f03a2 Add some missing checks in TwoAddressInstructionPass::CoalesceExtSubRegs. 
Check that all the instructions are in the same basic block, that the
EXTRACT_SUBREGs write to the same subregs that are being extracted, and that
the source and destination registers are in the same regclass.  Some of
these constraints can be relaxed with a bit more work.  Jakob suggested
that the loop that checks for subregs when NewSubIdx != 0 should use the
"nodbg" iterator, so I made that change here, too.

llvm-svn: 105437
 2010-06-03 23:53:58 +00:00
Jim Grosbach
686f10e4f0 Cleanup 80-column and trim trailing whitespace 
llvm-svn: 105435
 2010-06-03 23:49:57 +00:00
Jim Grosbach
5d75d732ae Teach the ARM load-store optimizer to deal with dbg_value instructions. 
llvm-svn: 105427
 2010-06-03 22:41:15 +00:00
Dale Johannesen
f80ca136ca Remove tail call to preserve this test. A tail 
call version will follow.

llvm-svn: 105422
 2010-06-03 21:57:48 +00:00
Dale Johannesen
f49af36017 Make this test not use tail calls. A tail call 
version will follow.

llvm-svn: 105419
 2010-06-03 21:53:01 +00:00
Nate Begeman
6483dc5067 Add some additional capabilities to the neon emitter 
llvm-svn: 105416
 2010-06-03 21:35:22 +00:00
Rafael Espindola
ee11d1e6a5 Add a emit-llvm option to the plugin and make the path argument to also-emit-llvm optional. 
llvm-svn: 105414
 2010-06-03 21:11:20 +00:00