1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-24 19:52:54 +01:00
Commit Graph

3286 Commits

Author SHA1 Message Date
Evan Cheng
aa0ff1ae01 Fix an inverted condition.
llvm-svn: 106330
2010-06-18 22:17:13 +00:00
Jakob Stoklund Olesen
a1d49fabaf When using ADDri to get the address of a stack object, 255 is a conservative
limit on the offset that can be materialized without using the register
scavenger.

llvm-svn: 106312
2010-06-18 20:59:25 +00:00
Dale Johannesen
a441c8fd45 Enable tail calls on ARM by default, with some
basic tests.

This has been well tested on Darwin but not elsewhere.
It should work provided the linker correctly resolves
  B.W  <label in other function>
which it has not seen before, at least from llvm-based
compilers.  I'm leaving the arm-tail-calls switch in
until I see if there's any problems because of that;
it might need to be disabled for some environments.

llvm-svn: 106299
2010-06-18 19:00:18 +00:00
Jakob Stoklund Olesen
6c387d99ca Treat the ARM inline asm {cc} constraint as a physreg (%CPSR), just like X86
does for {flags}. If we create virtual registers of the CCR class, RegAllocFast
may try to spill them, and we can't do that.

llvm-svn: 106289
2010-06-18 16:49:33 +00:00
Dan Gohman
9d7cf23808 Don't maintain a set of deleted nodes; instead, use a HandleSDNode
to track a node over CSE events. This fixes PR7368.

llvm-svn: 106266
2010-06-18 01:24:29 +00:00
Dan Gohman
8185674354 Fold the ShrinkDemandedOps pass into the regular DAGCombiner pass,
which is faster, simpler, and less surprising.

llvm-svn: 106263
2010-06-18 01:05:21 +00:00
Dan Gohman
08da31dc83 Make this test less fragile.
llvm-svn: 106255
2010-06-18 00:06:03 +00:00
Rafael Espindola
d7a63bead9 Remove arm_apcscc from the test files. It is the default and doing this
matches what llvm-gcc and clang now produce.

llvm-svn: 106221
2010-06-17 15:18:27 +00:00
Jakob Stoklund Olesen
4f5d1d7004 Allow a register to be redefined multiple times in a basic block.
LiveVariableAnalysis was a bit picky about a register only being redefined once,
but that really isn't necessary.

Here is an example of chained INSERT_SUBREGs that we can handle now:

68      %reg1040<def> = INSERT_SUBREG %reg1040, %reg1028<kill>, 14
                register: %reg1040 +[70,134:0)
76      %reg1040<def> = INSERT_SUBREG %reg1040, %reg1029<kill>, 13
                register: %reg1040 replace range with [70,78:1) RESULT: %reg1040,0.000000e+00 = [70,78:1)[78,134:0)  0@78-(134) 1@70-(78)
84      %reg1040<def> = INSERT_SUBREG %reg1040, %reg1030<kill>, 12
                register: %reg1040 replace range with [78,86:2) RESULT: %reg1040,0.000000e+00 = [70,78:1)[78,86:2)[86,134:0)  0@86-(134) 1@70-(78) 2@78-(86)
92      %reg1040<def> = INSERT_SUBREG %reg1040, %reg1031<kill>, 11
                register: %reg1040 replace range with [86,94:3) RESULT: %reg1040,0.000000e+00 = [70,78:1)[78,86:2)[86,94:3)[94,134:0)  0@94-(134) 1@70-(78) 2@78-(86) 3@86-(94)

rdar://problem/8096390

llvm-svn: 106152
2010-06-16 21:29:40 +00:00
Jim Grosbach
02a6b7e02e modify so the test doesn't drop an output file in the test source directory.
The test should also likely have some FileCheck bits to validate the
output(?).

llvm-svn: 106146
2010-06-16 21:07:06 +00:00
Evan Cheng
46b89e05fd Make post-ra scheduling, anti-dep breaking, and register scavenger (conservatively) aware of predicated instructions. This enables ARM to move if-conversion before post-ra scheduler.
llvm-svn: 106091
2010-06-16 07:35:02 +00:00
Bill Wendling
9b8de6dcec Create a more targeted fix for not sinking instructions into a range where it
will conflict with another live range. The place which creates this scenerio is
the code in X86 that lowers a select instruction by splitting the MBBs. This
eliminates the need to check from the bottom up in an MBB for live pregs.

llvm-svn: 106066
2010-06-15 23:46:31 +00:00
Jakob Stoklund Olesen
7fe0620525 Remove the local register allocator.
Please use the fast allocator instead.

llvm-svn: 106051
2010-06-15 21:58:33 +00:00
Rafael Espindola
90fa7d6460 Set the mtriple in some tests so that they use AAPCS.
llvm-svn: 106041
2010-06-15 20:42:00 +00:00
Mon P Wang
ee17c1140b Fixed vector widening of binary instructions that can trap. Patch by Visa Putkinen!
llvm-svn: 106038
2010-06-15 20:29:05 +00:00
Chris Lattner
48961d3ca6 fix fastisel to handle GS and FS relative pointers. Patch by
Nelson Elhage!

llvm-svn: 106031
2010-06-15 19:08:40 +00:00
Rafael Espindola
ab5183047b Remove the arm_aapcscc marker from the tests. It is the default
for the linux targets.

llvm-svn: 106029
2010-06-15 19:04:29 +00:00
Jakob Stoklund Olesen
88e1f2b2b5 Avoid processing early clobbers twice in RegAllocFast.
Early clobbers defining a virtual register were first alocated to a physreg and
then processed as a physreg EC, spilling the virtreg.

This fixes PR7382.

llvm-svn: 105998
2010-06-15 16:20:57 +00:00
Jakob Stoklund Olesen
f9a94f9154 Add CoalescerPair helper class.
Given a copy instruction, CoalescerPair can determine which registers to
coalesce in order to eliminate the copy. It deals with all the subreg fun to
determine a tuple (DstReg, SrcReg, SubIdx) such that:

- SrcReg is a virtual register that will disappear after coalescing.
- DstReg is a virtual or physical register whose live range will be extended.
- SubIdx is 0 when DstReg is a physical register.
- SrcReg can be joined with DstReg:SubIdx.

CoalescerPair::isCoalescable() determines if another copy instruction is
compatible with the same tuple. This fixes some NEON miscompilations where
shuffles are getting coalesced as if they were copies.

The CoalescerPair class will replace a lot of the spaghetti logic in JoinCopy
later.

llvm-svn: 105997
2010-06-15 16:04:21 +00:00
Bob Wilson
56555deb30 Generalize the pre-coalescing of extract_subregs feeding reg_sequences,
replacing the overly conservative checks that I had introduced recently to
deal with correctness issues.  This makes a pretty noticable difference
in our testcases where reg_sequences are used.  I've updated one test to
check that we no longer emit the unnecessary subreg moves.

llvm-svn: 105991
2010-06-15 05:56:31 +00:00
Chris Lattner
45c451acae apparently lots of dupes.
llvm-svn: 105956
2010-06-14 20:19:03 +00:00
Chris Lattner
3fd8e8a2f5 fix a nasty bug where we were not treating available_externally
symbols as declarations in the X86 backend.  This would manifest
on darwin x86-32 as errors like this with -fvisibility=hidden:

symbol '__ZNSbIcED1Ev' can not be undefined in a subtraction expression

This fixes PR7353.

llvm-svn: 105954
2010-06-14 20:11:56 +00:00
Chris Lattner
add4d84c77 remove old test.
llvm-svn: 105953
2010-06-14 20:07:43 +00:00
Chris Lattner
f2d0008dce rename test
llvm-svn: 105952
2010-06-14 20:07:34 +00:00
Bob Wilson
470551e0ef Add a missing bitcast. This code used to only handle conversions between
i64 and f64 types, but now it also handle Neon vector types, so the f64 result
of VMOVDRR may need to be converted to a Neon type.  Radar 8084742.

llvm-svn: 105845
2010-06-11 22:45:25 +00:00
Bill Wendling
0e4d704f16 Testcase for r105741.
llvm-svn: 105750
2010-06-09 20:30:22 +00:00
Jakob Stoklund Olesen
9611ad3317 Mark physregs defined by inline asm as implicit.
This is a bit of a hack to make inline asm look more like call instructions.
It would be better to produce correct dead flags during isel.

llvm-svn: 105749
2010-06-09 20:05:00 +00:00
Kalle Raiskila
392de86bb5 Fix SPU to cope with vector insertelement to an undef position.
We default to inserting to lane 0.

llvm-svn: 105722
2010-06-09 09:58:17 +00:00
Kalle Raiskila
b547a95a7b Handle loading from/storing to undef pointers on SPU by inserting a
random load/store, rather than crashing llc.

llvm-svn: 105710
2010-06-09 08:29:41 +00:00
Dan Gohman
1865db1b89 LSR needs to remember inserted instructions even in postinc mode, because
there could be multiple subexpressions within a single expansion which
require insert point adjustment. This fixes PR7306.

llvm-svn: 105510
2010-06-05 00:33:07 +00:00
Evan Cheng
0fb8a935a5 Re-apply 105308 with fix.
llvm-svn: 105502
2010-06-04 23:28:13 +00:00
Dale Johannesen
fc3c949f68 More tail call removal.
llvm-svn: 105485
2010-06-04 21:14:24 +00:00
Dan Gohman
332b06bd4f Fix normalization and de-normalization of non-affine SCEVs.
llvm-svn: 105480
2010-06-04 19:16:34 +00:00
Mon P Wang
f83cdf3d18 Fixed a bug during widening where we would avoid legalizing a node. When we
replace an OpA with a widened OpB, it is possible to get new uses of OpA due to CSE
when recursively updating nodes.  Since OpA has been processed, the new uses are
not examined again.  The patch checks if this occurred and it it did, updates the
new uses of OpA to use OpB.

llvm-svn: 105453
2010-06-04 01:20:10 +00:00
Dale Johannesen
f03ef32e4e Remove more tail calls.
llvm-svn: 105450
2010-06-04 01:01:24 +00:00
Dale Johannesen
0c967c579f Remove a tail call, and move some CHECKs to the
functions where they belong.

llvm-svn: 105449
2010-06-04 01:01:04 +00:00
Dan Gohman
bbd309edaa This test doesn't need the ssp attribute.
llvm-svn: 105440
2010-06-04 00:14:48 +00:00
Dale Johannesen
3492389308 Remove tail call. A tail call version will follow.
llvm-svn: 105438
2010-06-04 00:03:37 +00:00
Dale Johannesen
f80ca136ca Remove tail call to preserve this test. A tail
call version will follow.

llvm-svn: 105422
2010-06-03 21:57:48 +00:00
Dale Johannesen
f49af36017 Make this test not use tail calls. A tail call
version will follow.

llvm-svn: 105419
2010-06-03 21:53:01 +00:00
Dan Gohman
ab8153cf58 Fix SimplifyDemandedBits' AssertZext logic to demand all the bits. It
needs to demand the high bits because it's asserting that they're zero.

llvm-svn: 105406
2010-06-03 20:21:33 +00:00
Bob Wilson
15a21b6b97 Revert 105308.
llvm-svn: 105399
2010-06-03 18:28:31 +00:00
Bill Wendling
077afde4bf Machine sink could potentially sink instructions into a block where the physical
registers it defines then interfere with an existing preg live range.

For instance, if we had something like these machine instructions:

BB#0
  ... = imul ... EFLAGS<imp-def,dead>
  test ..., EFLAGS<imp-def>
  jcc BB#2 EFLAGS<imp-use>

BB#1
  ... ; fallthrough to BB#2

BB#2
  ... ; No code that defines EFLAGS
  jcc ... EFLAGS<imp-use>

Machine sink will come along, see that imul implicitly defines EFLAGS, but
because it's "dead", it assumes that it can move imul into BB#2. But when it
does, imul's "dead" imp-def of EFLAGS is raised from the dead (a zombie) and
messes up the condition code for the jump (and pretty much anything else which
relies upon it being correct).

The solution is to know which pregs are live going into a basic block. However,
that information isn't calculated at this point. Nor does the LiveVariables pass
take into account non-allocatable physical registers. In lieu of this, we do a
*very* conservative pass through the basic block to determine if a preg is live
coming out of it.

llvm-svn: 105387
2010-06-03 07:54:20 +00:00
Eric Christopher
00f399e90a One underscore, not two.
llvm-svn: 105379
2010-06-03 04:02:59 +00:00
Eli Friedman
60c8122bb0 Implement expansion in type legalization for add/sub with overflow. The
expansion is the same as that used by LegalizeDAG.

The resulting code sucks in terms of performance/codesize on x86-32 for a
64-bit operation; I haven't looked into whether different expansions might be
better in general.

llvm-svn: 105378
2010-06-03 03:49:50 +00:00
Evan Cheng
b137439a0a Enable machine cse of instructions which define physical registers.
llvm-svn: 105308
2010-06-02 01:08:27 +00:00
Dan Gohman
3a3a65dadc Fill in missing support for ISD::FEXP, ISD::FPOWI, and friends.
llvm-svn: 105283
2010-06-01 18:35:14 +00:00
Kalle Raiskila
ed7364d3e1 Fix handling of 'load' nodes.
llvm-svn: 105269
2010-06-01 13:34:47 +00:00
Chris Lattner
14bf35ae45 fix PR6623: when optimizing for size, don't inline memcpy/memsets
that are too large.  This causes the freebsd bootloader to be too
large apparently.

It's unclear if this should be an -Os or -Oz thing.  Thoughts welcome.

llvm-svn: 105228
2010-05-31 17:30:14 +00:00
Chris Lattner
e8b65c0352 upgrade and filecheckize this test.
llvm-svn: 105227
2010-05-31 17:27:17 +00:00