Jim Grosbach
ab639b8c36
ARM assembly 'cmp lr, #0 ' should not encode using 'cmn'.
...
The CMP->CMN alias was matching for an immediate of zero when it
should only match for negative values.
rdar://11129224
llvm-svn: 153689
2012-03-29 21:19:52 +00:00
Richard Barton
201661d4bc
Fixup VST1.32 with writeback instruction. Also re-factor non-writeback version.
...
llvm-svn: 153573
2012-03-28 10:18:11 +00:00
Eli Bendersky
3ef88c1833
Continue cleanup of LIT, getting rid of the remaining artifacts from dejagnu
...
* Removed test/lib/llvm.exp - it is no longer needed
* Deleted the dg.exp reading code from test/lit.cfg. There are no dg.exp files
left in the test suite so this code is no longer required. test/lit.cfg is
now much shorter and clearer
* Removed a lot of duplicate code in lit.local.cfg files that need access to
the root configuration, by adding a "root" attribute to the TestingConfig
object. This attribute is dynamically computed to provide the same
information as was previously provided by the custom getRoot functions.
* Documented the config.root attribute in docs/CommandGuide/lit.pod
llvm-svn: 153408
2012-03-25 09:02:19 +00:00
Kevin Enderby
b87e1e0bfd
Fix assembling ARM vst2 instructions with double-spaced registers.
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llvm-svn: 153099
2012-03-20 17:41:51 +00:00
Jim Grosbach
af19922301
ARM ldm/stm register lists can be out of order.
...
It's not a good style idea, as the registers will be laid down in memory in
numerical order, not the order they're in the list, but it's legal. vldm/vstm
are stricter.
rdar://11064740
llvm-svn: 152943
2012-03-16 20:48:38 +00:00
Jim Grosbach
a5d57ea09e
ARM optional operand on MRC/MCR assembly instructions.
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rdar://11058464
llvm-svn: 152883
2012-03-16 00:45:58 +00:00
Jim Grosbach
77151885af
ARM vmrs system registers mvfr0 and mvfr1 handling.
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rdar://11058464
llvm-svn: 152881
2012-03-16 00:27:18 +00:00
Jim Grosbach
3812c82b92
ARM case-insensitive checking for APSR_nzcv.
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rdar://11056591
llvm-svn: 152846
2012-03-15 21:34:14 +00:00
Kristof Beyls
5f7d669c67
Fix VCVT decoding (between floating-point and fixed-point, Floating-point). Patch by Richard Barton.
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llvm-svn: 152814
2012-03-15 17:50:29 +00:00
Jim Grosbach
91314c2db6
ARM vpush/vpop assembler mnemonics accept an optional size suffix.
...
rdar://10988114
llvm-svn: 152068
2012-03-05 23:16:31 +00:00
Jim Grosbach
02bf78f5ca
ARM BL/BLX instruction fixups should use relocations.
...
We on the linker to resolve calls to the appropriate BL/BLX instruction
to make interworking function correctly. It uses the symbol in the
relocation to do that, so we need to be careful about being too clever.
To enable this for ARM mode, split the BL/BLX fixup kind off from the
unconditional-branch fixups.
rdar://10927209
llvm-svn: 151571
2012-02-27 21:36:23 +00:00
Eli Bendersky
4afdeeb682
Replace all instances of dg.exp file with lit.local.cfg, since all tests are run with LIT now and now Dejagnu. dg.exp is no longer needed.
...
Patch reviewed by Daniel Dunbar. It will be followed by additional cleanup patches.
llvm-svn: 150664
2012-02-16 06:28:33 +00:00
James Molloy
b586b7c9c7
Ensure .AliasedSymbol() is called on all uses of getSymbol(). Affects ARM and MIPS ELF backends.
...
Fixes PR11877
llvm-svn: 149180
2012-01-28 15:58:32 +00:00
James Molloy
402abeda73
Add support for the R_ARM_TARGET1 relocation, which should be given to relocations applied to all C++ constructors and destructors.
...
This enables the linker to match concrete relocation types (absolute or relative) with whatever library or C++ support code is being linked against.
llvm-svn: 149057
2012-01-26 09:25:43 +00:00
Jim Grosbach
20a6580dff
ARM assemly parsing and validation of IT instruction.
...
"Although a Thumb2 instruction, the IT mnemonic shall be permitted in
ARM mode, and the condition verified to match the condition code(s)
on the following instruction(s)."
PR11853
llvm-svn: 148969
2012-01-25 19:52:01 +00:00
Jim Grosbach
e8095f3b49
NEON VLD4(all lanes) assembly parsing and encoding.
...
llvm-svn: 148884
2012-01-25 00:01:08 +00:00
Jim Grosbach
f478b2a706
NEON VLD3(all lanes) assembly parsing and encoding.
...
llvm-svn: 148882
2012-01-24 23:47:04 +00:00
Jim Grosbach
e151b15949
NEON VST4(one lane) assembly parsing and encoding.
...
llvm-svn: 148836
2012-01-24 18:53:13 +00:00
Jim Grosbach
a78348fcda
NEON VLD4(one lane) assembly parsing and encoding.
...
llvm-svn: 148832
2012-01-24 18:37:25 +00:00
Jim Grosbach
f3607eac5d
NEON Two-operand assembly aliases for VSRA.
...
llvm-svn: 148821
2012-01-24 17:55:36 +00:00
Jim Grosbach
47f7ce80b8
Remove redundant test file.
...
llvm-svn: 148820
2012-01-24 17:55:32 +00:00
Jim Grosbach
630dd380c7
NEON Two-operand assembly aliases for VSLI.
...
llvm-svn: 148819
2012-01-24 17:49:15 +00:00
Jim Grosbach
42c0f99aa0
NEON Two-operand assembly aliases for VSRI.
...
llvm-svn: 148818
2012-01-24 17:46:58 +00:00
Jim Grosbach
703b0bb646
Tidy up.
...
llvm-svn: 148817
2012-01-24 17:46:54 +00:00
Jim Grosbach
3be662b372
NEON VST4(multiple 4 element structures) assembly parsing.
...
llvm-svn: 148764
2012-01-24 00:58:13 +00:00
Jim Grosbach
ca32a49eb5
NEON VLD4(multiple 4 element structures) assembly parsing.
...
llvm-svn: 148762
2012-01-24 00:43:17 +00:00
Jim Grosbach
a4687dcf5a
NEON VST3(single element from one lane) assembly parsing.
...
llvm-svn: 148755
2012-01-24 00:07:41 +00:00
Jim Grosbach
048162ddf9
NEON VST3(multiple 3-element structures) assembly parsing.
...
llvm-svn: 148748
2012-01-23 23:45:44 +00:00
Jim Grosbach
8035fac461
NEON VLD3(multiple 3-element structures) assembly parsing.
...
llvm-svn: 148745
2012-01-23 23:20:46 +00:00
Jim Grosbach
dd667a11d3
NEON VLD3 lane-indexed assembly parsing and encoding.
...
llvm-svn: 148734
2012-01-23 21:53:26 +00:00
Jim Grosbach
0eeacbfe2e
Simplify some NEON assembly pseudo definitions.
...
Let the generic token alias definitions handle the data subtype
suffices. We don't need explicit versions for each.
llvm-svn: 148718
2012-01-23 19:39:08 +00:00
Jim Grosbach
4579f05f36
NEON use vmov.i32 to splat some f32 values into vectors.
...
For bit patterns that aren't representable using the 8-bit floating point
representation for vmov.f32, but are representable via vmov.i32, treat
the .f32 syntax as an alias. Most importantly, this covers the case
'vmov.f32 Vd, #0.0'.
rdar://10616677
llvm-svn: 148556
2012-01-20 18:09:51 +00:00
Jim Grosbach
b7ab9edb4e
Thumb2 alternate syntax for LDR(literal) and friends.
...
Explicit pc-relative syntax. For example, "ldrb r2, [pc, #-22]".
rdar://10250964
llvm-svn: 148432
2012-01-18 22:46:46 +00:00
Jim Grosbach
a678ad9ecc
ARM VFP assembly parsing and encoding for VCVT(float <--> fixed point).
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rdar://10558523
llvm-svn: 147189
2011-12-22 22:19:05 +00:00
Rafael Espindola
eba1c0eb00
Fix incorrect relocation generation. Patch by Kristof Beyls.
...
Fixes PR11214.
llvm-svn: 147180
2011-12-22 21:36:43 +00:00
Jim Grosbach
100e3aaffa
ARM assembler should accept shift-by-zero for any shifted-immediate operand.
...
Just treat it as-if the shift wasn't there at all. 'as' compatibility.
rdar://10604767
llvm-svn: 147153
2011-12-22 18:04:04 +00:00
Jim Grosbach
7d31680e2d
ARM VFP optional data type on VMOV GPR<-->SPR.
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llvm-svn: 147104
2011-12-21 23:24:15 +00:00
Jim Grosbach
2bbc41fa26
Thumb2 assembly parsing of 'mov rd, rn, rrx'.
...
Maps to the RRX instruction. Missed this case earlier.
rdar://10615373
llvm-svn: 147096
2011-12-21 21:04:19 +00:00
Jim Grosbach
91faf5d15f
Thumb2 assembly parsing of 'mov(register shifted register)' aliases.
...
These map to the ASR, LSR, LSL, ROR instruction definitions.
rdar://10615373
llvm-svn: 147094
2011-12-21 20:54:00 +00:00
Jim Grosbach
f7236d1084
ARM NEON assmebly parsing for VLD2 to all lanes instructions.
...
llvm-svn: 147069
2011-12-21 19:40:55 +00:00
Jim Grosbach
6bd1044b03
ARM NEON VLD2 assembly parsing for structure to all lanes, non-writeback.
...
llvm-svn: 147025
2011-12-21 00:38:54 +00:00
Jim Grosbach
0768f2c420
Enable and fix a test.
...
llvm-svn: 147011
2011-12-20 23:20:00 +00:00
Jim Grosbach
8978194025
ARM assembly parsing and encoding for VST2 single-element, double spaced.
...
llvm-svn: 146990
2011-12-20 20:46:29 +00:00
Jim Grosbach
3f48367a1b
ARM enable a few more tests.
...
llvm-svn: 146985
2011-12-20 20:03:00 +00:00
Jim Grosbach
8156a5dcee
ARM assembly parsing and encoding for VLD2 single-element, double spaced.
...
llvm-svn: 146983
2011-12-20 19:21:26 +00:00
Jim Grosbach
3f5493c136
ARM assembly shifts by zero should be plain 'mov' instructions.
...
"mov r1, r2, lsl #0 " should assemble as "mov r1, r2" even though it's
not strictly legal UAL syntax. It's a common extension and the friendly
thing to do.
rdar://10604663
llvm-svn: 146937
2011-12-20 00:59:38 +00:00
Jim Grosbach
343f270350
ARM assembly parsing and encoding support for LDRD(label).
...
rdar://9932658
llvm-svn: 146921
2011-12-19 23:06:24 +00:00
Jim Grosbach
797a88284c
ARM NEON two-operand aliases for VPADD.
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rdar://10602276
llvm-svn: 146895
2011-12-19 19:51:03 +00:00
Jim Grosbach
520db82971
ARM NEON implied destination aliases for VMAX/VMIN.
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llvm-svn: 146885
2011-12-19 18:57:38 +00:00
Jim Grosbach
f4ca84a7ab
ARM NEON relax parse time diagnostics for alignment specifiers.
...
There's more variation that we need to handle. Error checking will need
to be on operand predicates.
llvm-svn: 146884
2011-12-19 18:31:43 +00:00