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21391 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen
b27db3628f Extract some pointer hacking to a function. 
Switch to MCSuperRegIterator while we're there.

llvm-svn: 157717
 2012-05-30 22:40:03 +00:00
Eric Christopher
c2eb5a6ee6 Add support for the mips inline asm 'm' output modifier. 
Patch by Jack Carter.

llvm-svn: 157709
 2012-05-30 19:05:19 +00:00
Jakob Stoklund Olesen
2dca201f54 Fix some uses of getSubRegisters() to use getSubReg() instead. 
It is better to address sub-registers directly by name instead of
relying on their position in the sub-register list.

llvm-svn: 157703
 2012-05-30 18:40:49 +00:00
Chris Lattner
1d39403e7b it's pointed out that R11 can be used for magic things, and doing things just for 64-bit registers is silly. Just optimize 3 more. 
llvm-svn: 157699
 2012-05-30 18:08:02 +00:00
Chris Lattner
505bcf70a0 Extend the (abi-irrelevant) return convention to be able to return more than two values in 
integer registers.  This is already supported by the fastcc convention, but it doesn't
hurt to support it in the standard conventions as well.

In cases where we can cheat at the calling convention, this allows us to avoid returning
things through memory in more cases.

llvm-svn: 157698
 2012-05-30 17:50:14 +00:00
Chad Rosier
80159b26a5 [arm-fast-isel] Add support for the llvm.frameaddress() intrinsic. 
Patch by Jush Lu <jush.msn@gmail.com>.

llvm-svn: 157696
 2012-05-30 17:23:22 +00:00
Benjamin Kramer
11fa8a91e7 Port support for SSE4a extrq/insertq to the old jit code emitter. 
llvm-svn: 157685
 2012-05-30 09:13:55 +00:00
Benjamin Kramer
0c823ae0ed Add intrinsics, code gen, assembler and disassembler support for the SSE4a extrq and insertq instructions. 
This required light surgery on the assembler and disassembler
because the instructions use an uncommon encoding. They are
the only two instructions in x86 that use register operands
and two immediates.

llvm-svn: 157634
 2012-05-29 19:05:25 +00:00
Nicolas Geoffray
caed2e95b1 Update CPPBackend to new API for AttrListPtr::get. 
llvm-svn: 157624
 2012-05-29 15:07:18 +00:00
Stepan Dyatkovskiy
23fa9fd605 ConstantRangesSet renamed to IntegersSubset. CRSBuilder renamed to IntegersSubsetMapping. 
llvm-svn: 157612
 2012-05-29 12:26:47 +00:00
Akira Hatanaka
0a61e3a69b Fix predicate HasStandardEncoding in MipsInstrInfo.td per suggestion of 
Benjamin Kramer.

llvm-svn: 157504
 2012-05-25 22:15:15 +00:00
Akira Hatanaka
2be7cb0794 Delete MipsExpandPseudo.cpp. 
llvm-svn: 157496
 2012-05-25 20:54:48 +00:00
Akira Hatanaka
2d05968e4e Move the code in MipsExpandPseudo to MipsInstrInfo::expandPostRAPseudo. 
Delete MipsExpandPseudo.

llvm-svn: 157495
 2012-05-25 20:52:52 +00:00
Akira Hatanaka
6af9e8ba7d Remove the code that expands MIPS' .cpload directive. 
llvm-svn: 157494
 2012-05-25 20:46:52 +00:00
Akira Hatanaka
3514125a37 Remove the code that emits MIPS' .cprestore directive. 
llvm-svn: 157493
 2012-05-25 20:42:55 +00:00
Akira Hatanaka
40236c8d6c Remove pseudo instructions that are no longer used. 
llvm-svn: 157492
 2012-05-25 20:37:40 +00:00
Justin Holewinski
77c4679dae Change interface for TargetLowering::LowerCallTo and TargetLowering::LowerCall 
to pass around a struct instead of a large set of individual values.  This
cleans up the interface and allows more information to be added to the struct
for future targets without requiring changes to each and every target.

NV_CONTRIB

llvm-svn: 157479
 2012-05-25 16:35:28 +00:00
Eli Friedman
d89582030a Simplify code for calling a function where CanLowerReturn fails, fixing a small bug in the process. 
llvm-svn: 157446
 2012-05-25 00:09:29 +00:00
Jakob Stoklund Olesen
d695e1cc67 Shrink. 
llvm-svn: 157433
 2012-05-24 22:17:44 +00:00
Justin Holewinski
ee3de35dee Remove the PTX back-end and all of its artifacts (triple, etc.) 
This back-end was deprecated in favor of the NVPTX back-end.

NV_CONTRIB

llvm-svn: 157417
 2012-05-24 21:38:21 +00:00
Akira Hatanaka
a169c70246 Turn on mips16 pseudo op when compiling for mips16. 
Expand test case for this.

Patch by Reed Kotler.

llvm-svn: 157410
 2012-05-24 18:37:43 +00:00
Akira Hatanaka
44ebe6c79d Enable Mips16 compiler to compile a null program. 
First code from the Mips16 compiler. Includes trivial test program.

Patch by Reed Kotler.

llvm-svn: 157408
 2012-05-24 18:32:33 +00:00
Craig Topper
155599cf7a Convert assert(0) to llvm_unreachable. 
llvm-svn: 157380
 2012-05-24 07:02:50 +00:00
Craig Topper
c7b86c787d Use uint16_t to store registers in static tables. Matches other tables. 
llvm-svn: 157375
 2012-05-24 06:09:56 +00:00
Craig Topper
c5bd0cba8f Use uint16_t to store register number in static tables to match other tables. 
llvm-svn: 157374
 2012-05-24 05:55:47 +00:00
Craig Topper
082149564d Make some opcode tables static and const. Allows code to avoid making copies to pass the tables around. 
llvm-svn: 157373
 2012-05-24 05:17:00 +00:00
Craig Topper
ed31fb2ec5 Mark a couple arrays as static and const. Use array_lengthof instead of sizeof/sizeof. 
llvm-svn: 157369
 2012-05-24 04:22:05 +00:00
Craig Topper
a34cbd451f Mark a static array as const. 
llvm-svn: 157368
 2012-05-24 04:11:15 +00:00
Craig Topper
2efe750a91 Mark a static table as const. Shrink opcode size in static tables to uint16_t. Simplify loop iterating over one of those tables. No functional change intended. 
llvm-svn: 157367
 2012-05-24 03:59:11 +00:00
Chad Rosier
b11b7f8b69 Tidy up naming for consistency and other cleanup. No functional change intended. 
llvm-svn: 157358
 2012-05-23 23:45:10 +00:00
Chad Rosier
d9dca3aef3 [arm-fast-isel] Add support for non-global callee. 
Patch by Jush Lu <jush.msn@gmail.com>.

llvm-svn: 157336
 2012-05-23 18:38:57 +00:00
Craig Topper
49c52dde2b Tidy up spacing. 
llvm-svn: 157313
 2012-05-23 05:44:51 +00:00
Craig Topper
5161134794 Fix indentation of wrapped line for readability. No functional change. 
llvm-svn: 157309
 2012-05-23 03:59:53 +00:00
NAKAMURA Takumi
ef6f526307 ARMDisassembler.cpp: Fix utf8 char in comments. 
llvm-svn: 157292
 2012-05-22 21:47:02 +00:00
Craig Topper
0fe3f1297b Fix constant used for pshufb mask when lowering v16i8 shuffles. Bug introduced in r157043. Fixes PR12908. 
llvm-svn: 157236
 2012-05-22 06:09:38 +00:00
Akira Hatanaka
2a600ff5f4 This patch adds a predicate to existing mips32 and mips64 so that those 
instruction encodings can be excluded during mips16 processing.

This revision fixes the issue raised by Jim Grosbach.

bool hasStandardEncoding() const { return !inMips16Mode(); }

When micromips is added it will be

bool StandardEncoding() const { return !inMips16Mode()&&  !inMicroMipsMode(); }

No additional testing is needed other than to assure that there is no regression
from this patch.

Patch by Reed Kotler.

llvm-svn: 157234
 2012-05-22 03:10:09 +00:00
Jim Grosbach
6e9ef9c931 ARM: .end_data_region mismatch in Thumb2. 
32-bit offset jump tables just use real branch instructions and so aren't
marked as data regions. We were still emitting the .end_data_region
marker though, which assert()ed.

rdar://11499158

llvm-svn: 157221
 2012-05-21 23:34:42 +00:00
Jim Grosbach
85edf59851 Thumb2: RSB source register should be rGRP not GPRnopc. 
t2RSB defined the operand correctly, but tRSBS didn't.

llvm-svn: 157200
 2012-05-21 17:57:17 +00:00
Craig Topper
57d54b1831 Allow 256-bit shuffles to still be split even if only half of the shuffle comes from two 128-bit pieces. 
llvm-svn: 157175
 2012-05-21 06:40:16 +00:00
Jakob Stoklund Olesen
e9ba1b5df0 Make the global base reg GR32_NOSP. 
It can sometimes be used in addressing modes that don't support %ESP.

llvm-svn: 157165
 2012-05-20 18:43:00 +00:00
Hal Finkel
9fad4cf803 Add a missing PPC 64-bit stwu pattern. 
This seems to fix the remaining compile-time failures on PPC64 when
compiling with -enable-ppc-preinc.

llvm-svn: 157159
 2012-05-20 17:11:24 +00:00
Jakob Stoklund Olesen
bedc5bbb62 Use the right register class for LDRrs. 
llvm-svn: 157152
 2012-05-20 06:38:47 +00:00
Jakob Stoklund Olesen
3bee83c3a5 Transfer memory operands to the right instruction. 
They need to go on the PICLDR as the verifier points out.

llvm-svn: 157151
 2012-05-20 06:38:42 +00:00
Hal Finkel
259ded3876 Add a FIXME about access to negative stack-pointer offsets on PPC32. 
The current code will generate a prologue which starts with something like:
        mflr 0
        stw 31, -4(1)
        stw 0, 4(1)
        stwu 1, -16(1)

But under the PPC32 SVR4 ABI, access to negative offsets from R1 is not allowed.

This was pointed out by Peter Bergner.

llvm-svn: 157133
 2012-05-19 21:52:55 +00:00
Nadav Rotem
a46c75d9a7 On Haswell, perfer storing YMM registers using a single instruction. 
llvm-svn: 157129
 2012-05-19 20:30:08 +00:00
Nadav Rotem
441318ee29 Add support for additional in-reg vbroadcast patterns 
llvm-svn: 157127
 2012-05-19 19:57:37 +00:00
Craig Topper
55b5aa4042 Tidy up some spacing and inconsistent use of pre/post increment. No functional change intended. 
llvm-svn: 157122
 2012-05-19 19:14:18 +00:00
Stepan Dyatkovskiy
45e3003f3c Ordinary PR1255 patch: DifferenceEngine and CPPBackend adopted to the new SwitchInst methods. 
llvm-svn: 157112
 2012-05-19 13:14:30 +00:00
Craig Topper
3f21aba382 Copy some AVX support from MCJIT to JIT. Maybe will fix PR12748. 
llvm-svn: 157109
 2012-05-19 08:28:17 +00:00
Eric Christopher
2d50bc73f8 Add support for the 'd' mips inline asm output modifier. 
Patch by Jack Carter.

llvm-svn: 157093
 2012-05-19 00:51:56 +00:00