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12358 Commits

Author SHA1 Message Date
Bill Wendling
3e4dd02a1e Modify note. 
llvm-svn: 85331
 2009-10-27 22:40:45 +00:00
Bill Wendling
3edf1d3854 Add a note. 
llvm-svn: 85329
 2009-10-27 22:34:43 +00:00
Chris Lattner
34c90ce60d cppbackend support for indbr 
llvm-svn: 85312
 2009-10-27 21:24:48 +00:00
Chris Lattner
f21034d6c3 CBE support for indbr. 
llvm-svn: 85311
 2009-10-27 21:21:06 +00:00
Johnny Chen
b746e248cd Similar to r85280, do not clear the "S" bit for RSBri and RSBrs. 
llvm-svn: 85299
 2009-10-27 20:51:49 +00:00
Johnny Chen
d63b06e0f6 Set condition code bits of BL and BLr9 to 0b1110 (ALways) to distinguish between 
BL_pred and BLr9_pred.

llvm-svn: 85297
 2009-10-27 20:45:15 +00:00
Evan Cheng
151726ad30 Do away with addLegalFPImmediate. Add a target hook isFPImmLegal which returns true if the fp immediate can be natively codegened by target. 
llvm-svn: 85281
 2009-10-27 19:56:55 +00:00
Bob Wilson
5ca76e601f Do not clear the "S" bit for RSCri and RSCrs. They inherit from the "sI" 
instruction format that already takes care of setting this.

llvm-svn: 85280
 2009-10-27 19:52:03 +00:00
Johnny Chen
528c66b30c Explicitly specify 0b00, i.e, zero rotation, as the rotate filed (Inst{11-10}) 
for the r/rr fragment of the multiclass AI_unary_rrot/AI_bin_rrot.

llvm-svn: 85271
 2009-10-27 18:44:24 +00:00
Sanjiv Gupta
c690360ed5 Remove unnecessary gotos to fall-thru successors. 
llvm-svn: 85257
 2009-10-27 17:40:24 +00:00
Johnny Chen
37851c95e8 Test commit. Added '.' to the comment line. 
llvm-svn: 85255
 2009-10-27 17:25:15 +00:00
Chris Lattner
5596e0eb77 apparently the X86 JIT isn't fully contextized, it is still using getGlobalContext() :( 
llvm-svn: 85252
 2009-10-27 17:01:03 +00:00
Rafael Espindola
7eb2a8fb0b Correctly align double arguments in the stack. 
llvm-svn: 85235
 2009-10-27 14:09:44 +00:00
Evan Cheng
032eef9720 Now VFP instructions. 
llvm-svn: 85186
 2009-10-27 00:20:49 +00:00
Evan Cheng
f30e5556ba Change Thumb1 and Thumb2 instructions to separate opcode from operands with a tab instead of a space. 
llvm-svn: 85184
 2009-10-27 00:08:59 +00:00
Evan Cheng
a883c2ebb7 Change ARM asm strings to separate opcode from operands with a tab instead of a space. 
llvm-svn: 85178
 2009-10-26 23:45:59 +00:00
Victor Hernandez
673c036bc7 Remove FreeInst. 
Remove LowerAllocations pass.
Update some more passes to treate free calls just like they were treating FreeInst.

llvm-svn: 85176
 2009-10-26 23:43:48 +00:00
Bob Wilson
5a870f848e Try to get ahead of Johnny Chen and pro-actively add some more ARM encoding 
bits.  Johnny, please review -- I do not have a good track record of getting
these right.

llvm-svn: 85173
 2009-10-26 22:59:12 +00:00
Bob Wilson
ace97183c7 Fix ARM encoding typo: Opcod3 is not passed to ASuI parent class. 
Patch by Johnny Chen.

llvm-svn: 85169
 2009-10-26 22:42:13 +00:00
Bob Wilson
32ee4ee163 Add more ARM instruction encodings for 's' bit set and "rs" register encoding 
bits.  Patch by Johnny Chen.

llvm-svn: 85167
 2009-10-26 22:34:44 +00:00
Ted Kremenek
acb9fe806e Update CMake files. 
llvm-svn: 85161
 2009-10-26 22:06:01 +00:00
Anton Korobeynikov
4f40949874 Revert r85134, it breaks mingw build 
llvm-svn: 85138
 2009-10-26 18:40:24 +00:00
Sanjiv Gupta
7ea628e8db Make PIC16 overlay a loadable pass. 
llvm-svn: 85134
 2009-10-26 18:22:59 +00:00
David Goodwin
f6199e95b0 Break anti-dependence breaking out into its own class. 
llvm-svn: 85127
 2009-10-26 16:59:04 +00:00
Chandler Carruth
766362c707 Move DataTypes.h to include/llvm/System, update all users. This breaks the last 
direct inclusion edge from System to Support.

llvm-svn: 85086
 2009-10-26 01:35:46 +00:00
Jim Grosbach
eae0e509c0 of -> or 
llvm-svn: 85065
 2009-10-25 19:14:48 +00:00
Jim Grosbach
29b842a6c1 80-column cleanup 
llvm-svn: 85064
 2009-10-25 18:55:46 +00:00
Sanjiv Gupta
18574b11b0 Reapply 85006 with a minor fix. 
llvm-svn: 85052
 2009-10-25 08:14:11 +00:00
Evan Cheng
d748ce45ab Add ARM getMatchingSuperRegClass to handle S / D / Q cross regclass coalescing. 
llvm-svn: 85049
 2009-10-25 07:53:28 +00:00
Evan Cheng
77ecc0adc5 Don't forget subreg indices when folding load / store. 
llvm-svn: 85048
 2009-10-25 07:52:27 +00:00
Nick Lewycky
2b8400628d Remove includes of Support/Compiler.h that are no longer needed after the 
VISIBILITY_HIDDEN removal.

llvm-svn: 85043
 2009-10-25 06:57:41 +00:00
Nick Lewycky
711c726c97 Remove VISIBILITY_HIDDEN from class/struct found inside anonymous namespaces. 
Chris claims we should never have visibility_hidden inside any .cpp file but
that's still not true even after this commit.

llvm-svn: 85042
 2009-10-25 06:33:48 +00:00
Chris Lattner
81c06b943c this is done. 
llvm-svn: 85041
 2009-10-25 06:17:51 +00:00
Nick Lewycky
cacdc4d65a Remove ICmpInst::isSignedPredicate which was a reimplementation 
CmpInst::isSigned.

llvm-svn: 85037
 2009-10-25 05:20:17 +00:00
Sanjiv Gupta
ec0d345a46 Revert back 85006 for now as it breaks PIC16 tests. 
llvm-svn: 85008
 2009-10-24 18:19:41 +00:00
Sanjiv Gupta
1fcb847e01 Adding support for placing global objects in shared data memory. 
llvm-svn: 85006
 2009-10-24 18:02:44 +00:00
Evan Cheng
0e5c6b3b69 80 col violation. 
llvm-svn: 84986
 2009-10-24 02:07:42 +00:00
Jim Grosbach
e295e49760 Restrict Thumb1 register allocation to low registers, even for instructions that 
can access the hi regs. Our prologue and epilogue code doesn't know how to
properly handle save/restore of the hi regs, so things go badly when we alloc
them.

llvm-svn: 84982
 2009-10-24 00:19:24 +00:00
Jim Grosbach
5b5a404677 FIXME no longer applies. R12 and R3 are available for allocation 
llvm-svn: 84977
 2009-10-23 23:07:42 +00:00
Chris Lattner
d1dbcae98f some stuff is done, we still have constantexpr simplification to do. 
llvm-svn: 84943
 2009-10-23 07:00:55 +00:00
Evan Cheng
0db11ae5a2 X86 needs critical path anti-dependency breaking. 
llvm-svn: 84931
 2009-10-23 05:57:35 +00:00
David Goodwin
82c1dd9754 Allow the target to select the level of anti-dependence breaking that should be performed by the post-RA scheduler. The default is none. 
llvm-svn: 84911
 2009-10-22 23:19:17 +00:00
Bob Wilson
8f4f73da55 Revert 84843. Evan, this was breaking some of the if-conversion tests. 
llvm-svn: 84868
 2009-10-22 16:52:21 +00:00
Benjamin Kramer
b159c164d2 Shift art to the right to keep GCC from complaining about multi-line comments. 
llvm-svn: 84849
 2009-10-22 09:28:49 +00:00
Evan Cheng
2edd1efa46 Move if-conversion before post-regalloc scheduling so the predicated instruction get scheduled properly. 
llvm-svn: 84843
 2009-10-22 06:48:32 +00:00
Evan Cheng
d411ac1267 Load / store multiple was missing opportunites when the load / store bundles are at the end of the bb. Test case is already in, the bug is exposed by subsequent commit. 
llvm-svn: 84842
 2009-10-22 06:47:35 +00:00
Evan Cheng
0c6aa52214 Trim more includes. 
llvm-svn: 84832
 2009-10-22 05:11:00 +00:00
Evan Cheng
166f455456 Trim include. 
llvm-svn: 84831
 2009-10-22 05:08:49 +00:00
Chris Lattner
e0932e92e9 fix warning. 
llvm-svn: 84826
 2009-10-22 03:42:27 +00:00
Evan Cheng
8fdd1661fa Don't generate sbfx / ubfx with negative lsb field. Patch by David Conrad. 
llvm-svn: 84813
 2009-10-22 00:40:00 +00:00
Anton Korobeynikov
bbc637e96d Use special DAG-to-DAG preprocessing to allow mem-mem instructions to be selected. 
Yay for ASCII graphics!

llvm-svn: 84808
 2009-10-22 00:16:00 +00:00
Jim Grosbach
f79f9afb91 Missing piece of the ARM frame index post-scavenging conditionalization 
llvm-svn: 84798
 2009-10-21 23:40:56 +00:00
Jim Grosbach
363a67d9c5 Conditionalize ARM/T2 frame index post-scavenging while working out fixes 
for a few bugs.

llvm-svn: 84791
 2009-10-21 22:59:24 +00:00
Bob Wilson
26a4580439 Most of the NEON shuffle instructions do not support 64-bit element types. 
llvm-svn: 84785
 2009-10-21 21:36:27 +00:00
Anton Korobeynikov
141a4a2f42 Revert r84764, it breaks mingw build 
llvm-svn: 84783
 2009-10-21 21:15:18 +00:00
Jim Grosbach
452de96b04 Improve handling of immediates by splitting 32-bit immediates into two 16-bit 
immediate operands when they will fit into the using instruction.

llvm-svn: 84778
 2009-10-21 20:44:34 +00:00
Anton Korobeynikov
23ea13afbb Add DAG printing for RMW stuff debugging 
llvm-svn: 84776
 2009-10-21 19:18:28 +00:00
Anton Korobeynikov
d233af8049 RMW preprocessing stuff was incorrect. Grab the stuff from x86 backend and disable some tests until it will be clever enough to handle them. 
llvm-svn: 84775
 2009-10-21 19:17:55 +00:00
Anton Korobeynikov
6329ddd231 Implement branch folding 
llvm-svn: 84774
 2009-10-21 19:17:18 +00:00
Anton Korobeynikov
c9ed87ea9a Cosmetic changes, no functionality changes 
llvm-svn: 84773
 2009-10-21 19:16:49 +00:00
Bob Wilson
41f94edfb0 Fix NEON VST2LN instruction encoding. 
Patch by Johnny Chen.

llvm-svn: 84767
 2009-10-21 17:54:01 +00:00
Bob Wilson
5f9ea75e2b Revert 84732. It was the wrong fix. 
llvm-svn: 84766
 2009-10-21 17:52:34 +00:00
Sanjiv Gupta
9e78b53be3 Build shared lib instead of an archive. 
llvm-svn: 84764
 2009-10-21 17:27:23 +00:00
Sanjiv Gupta
d6fd961c5c Add a pass to overlay pic16 data sections for function frame and automatic 
variables. This pass can be invoked by llvm-ld or opt to traverse over the call graph 
to detect what function frames and their automatic variables can be overlaid.
Currently this builds an archive , but needs to be changed to a loadable module.

llvm-svn: 84753
 2009-10-21 10:42:44 +00:00
Evan Cheng
275a09e55d Match more patterns to movt. 
llvm-svn: 84751
 2009-10-21 08:15:52 +00:00
Chris Lattner
690911b253 tidy 
llvm-svn: 84738
 2009-10-21 04:10:24 +00:00
Bob Wilson
02d3df4a87 Fix some more NEON instruction encoding problems. 
Thanks to Johnny Chen for discovering the problem.

llvm-svn: 84732
 2009-10-21 02:27:20 +00:00
Bob Wilson
e85a3142bc Leave some NEON instruction encoding bits unspecified instead of setting 
a default value of zero.  This is important for decoding the instructions.
Patch by Johnny Chen, with some changes from me, too.

llvm-svn: 84730
 2009-10-21 02:15:46 +00:00
Chris Lattner
2363ec8194 IPSCCP is missing stuff. 
llvm-svn: 84725
 2009-10-21 01:10:37 +00:00
Anton Korobeynikov
7c7a801467 Add note 
llvm-svn: 84713
 2009-10-21 00:14:15 +00:00
Anton Korobeynikov
f7e27bb17e Be crazy and assert in case of unsupported modifier passed. 
llvm-svn: 84712
 2009-10-21 00:13:58 +00:00
Anton Korobeynikov
3b90c55321 Handle external symbols 
llvm-svn: 84711
 2009-10-21 00:13:42 +00:00
Anton Korobeynikov
d104087bfe Distinguish between pcrel imm operands and 'normal' ones. Fix fixes gross weirdness of asmprinting. 
llvm-svn: 84710
 2009-10-21 00:13:25 +00:00
Anton Korobeynikov
c35bd58bd5 Add basic block operands & jump kinds 
llvm-svn: 84709
 2009-10-21 00:13:05 +00:00
Anton Korobeynikov
2bcb24c40b Ignore all implicit reg operands 
llvm-svn: 84708
 2009-10-21 00:12:44 +00:00
Anton Korobeynikov
f3003dfcd1 Add a workaround for different memops prefixes 
llvm-svn: 84707
 2009-10-21 00:12:27 +00:00
Anton Korobeynikov
af4c4ee8f5 Checkpoint MCInst printer. We (almostly) able to print global / JT / constpool entries 
llvm-svn: 84706
 2009-10-21 00:12:08 +00:00
Anton Korobeynikov
5a6771aab2 Add simple operand printing stuff 
llvm-svn: 84704
 2009-10-21 00:11:27 +00:00
Anton Korobeynikov
8b01906b63 Add experimental MSP430 MCInstLowering stuff 
llvm-svn: 84703
 2009-10-21 00:11:08 +00:00
Anton Korobeynikov
0c059394ac Wire up MSP430 printMCInst() method 
llvm-svn: 84702
 2009-10-21 00:10:47 +00:00
Anton Korobeynikov
a534ef3f63 Add MSP430 InstPrinter stub 
llvm-svn: 84701
 2009-10-21 00:10:30 +00:00
Anton Korobeynikov
8dc97f136b Use proper target data 
llvm-svn: 84700
 2009-10-21 00:10:00 +00:00
Daniel Dunbar
502e00c5b9 Fix -Asserts warning. 
llvm-svn: 84687
 2009-10-20 22:10:05 +00:00
Jim Grosbach
8a182902ef Disable by default while debugging 
llvm-svn: 84669
 2009-10-20 20:31:31 +00:00
Jim Grosbach
5f9188c873 add cmd line opt to disable frame index reuse for ARM and T2. debug aid. 
llvm-svn: 84664
 2009-10-20 20:19:50 +00:00
Dan Gohman
6b54c70e78 Following r84485, add Defs = [EFLAGS] to the 32-bit lock instructions too. 
llvm-svn: 84652
 2009-10-20 18:14:49 +00:00
Dan Gohman
e0ace5c4eb Make TranslateX86CC return COND_INVALID instead of aborting when it 
encounters an OEQ or UNE comparison, and update its callers to check
for this return status and recover. This fixes a problem resulting from
the LowerOperation hooks being called from LegalizeVectorOps, because
LegalizeVectorOps only lowers vectors, so OEQ and UNE comparisons may
still be at large. This fixes PR5092.

llvm-svn: 84640
 2009-10-20 16:22:37 +00:00
Benjamin Kramer
dee347a8e8 Random #include pruning. 
llvm-svn: 84632
 2009-10-20 11:44:38 +00:00
Sanjiv Gupta
28330ebddc This file is replaeced by PIC16Section.h. 
llvm-svn: 84628
 2009-10-20 09:16:32 +00:00
Chris Lattner
2a04686991 implement some more easy hooks. 
llvm-svn: 84614
 2009-10-20 06:22:33 +00:00
Chris Lattner
8137f1aef2 Implement some hooks, make printOperand abort if unknown modifiers are 
present.

llvm-svn: 84613
 2009-10-20 06:15:28 +00:00
Chris Lattner
dfe75a5667 t2MOVi32imm is currently always lowered by the Thumb2ITBlockPass. 
llvm-svn: 84611
 2009-10-20 05:58:02 +00:00
Daniel Dunbar
87b361d3d6 Wire up the ARM MCInst printer, for llvm-mc. 
llvm-svn: 84600
 2009-10-20 05:15:36 +00:00
Jim Grosbach
ea8ab9a323 Now that all ARM subtargets use frame index scavenging, the Thumb1 requires* 
functions are not needed.

llvm-svn: 84587
 2009-10-20 01:32:47 +00:00
Jim Grosbach
c4acd85bfd Enable post-pass frame index register scavenging for ARM and Thumb2 
llvm-svn: 84585
 2009-10-20 01:26:58 +00:00
Chris Lattner
8b2fb5c12a lower ARM::MOVi32imm properly. 
llvm-svn: 84583
 2009-10-20 01:11:37 +00:00
Chris Lattner
b345825d9e add support for external symbols. The mc instprinter can now handle 
reasonable code like Codegen/ARM/2009-02-27-SpillerBug.ll, producing 
identical output except for superior formatting of constant pool entries.

llvm-svn: 84582
 2009-10-20 00:56:16 +00:00
Chris Lattner
510ca3ebd7 get fancy: support basic block operands. Yay for jumps. 
llvm-svn: 84579
 2009-10-20 00:52:47 +00:00
Chris Lattner
279abd0841 add supprort for the 'sbit' operand, MOVi apparently has one. 
llvm-svn: 84577
 2009-10-20 00:46:11 +00:00
Chris Lattner
18bc7716d6 add support for instruction predicates. 
llvm-svn: 84575
 2009-10-20 00:42:49 +00:00
Chris Lattner
976978de4a implement printSORegOperand, add lowering for the nasty and despicable MOVi2pieces :) 
llvm-svn: 84573
 2009-10-20 00:40:56 +00:00
Jim Grosbach
ea7293494f Refs: A8-598. 
Leave Inst{11-8}, which represents the starting byte index of the extracted
result in the concatenation of the operands and is left unspecified.

Patch by Johnny Chen.

llvm-svn: 84572
 2009-10-20 00:38:19 +00:00
Jim Grosbach
aaa0e97800 Add missing encoding bits to NLdSt class of instructions. 
Patch by Johnny Chen.

llvm-svn: 84570
 2009-10-20 00:19:08 +00:00
Chris Lattner
db0e4f883d X86 should ignore implicit regs when lowering to MCInst also, 
no functionality change.

llvm-svn: 84567
 2009-10-19 23:35:57 +00:00
Chris Lattner
8a38b12ffe handle addmode4 modifiers, fix a fixme in printRegisterList 
by ignoring all implicit regs when lowering.

llvm-svn: 84566
 2009-10-19 23:31:43 +00:00
Chris Lattner
5630502650 simplify by using the twine form of GetOrCreateSymbol 
llvm-svn: 84565
 2009-10-19 23:05:23 +00:00
Jim Grosbach
2fb5eb1264 Enable allocation of R3 in Thumb1 
llvm-svn: 84563
 2009-10-19 22:57:03 +00:00
Chris Lattner
24d265dae3 use EmitLabel instead of text emission 
llvm-svn: 84562
 2009-10-19 22:51:16 +00:00
Chris Lattner
df848440d1 add a twine version of MCContext::GetOrCreateSymbol. 
llvm-svn: 84561
 2009-10-19 22:49:00 +00:00
Chris Lattner
47131861be lower the ARM::CONSTPOOL_ENTRY pseudo op, giving us constant pool entries 
like:

@ BB#1:
	.align	2
LCPI1_0:
	.long	L_.str-(LPC0+8)

Note that proper indentation of the label :)

llvm-svn: 84558
 2009-10-19 22:33:05 +00:00
Jim Grosbach
c813cf9649 Adjust the scavenge register spilling to allow the target to choose an 
appropriate restore location for the spill as well as perform the actual
save and restore.

The Thumb1 target uses this to make sure R12 is not clobbered while a spilled
scavenger register is live there.

llvm-svn: 84554
 2009-10-19 22:27:30 +00:00
Chris Lattner
ce9e652b8a add MCInstLower support for lowering ARM::PICADD, a pseudo op for pic stuffola. 
llvm-svn: 84553
 2009-10-19 22:23:04 +00:00
Chris Lattner
d7d7fee3fe add register list and hacked up addrmode #4 support, we now get this: 
_main:
	stmsp! sp!, {r7, lr}
	mov r7, sp
	sub sp, sp, #4
	mov r0, #0
	str r0, [sp]
	ldr r0, LCPI1_0
	bl _printf
	ldr r0, [sp]
	mov sp, r7
	ldmsp! sp!, {r7, pc}

Note the unhappy ldm/stm because of modifiers being ignored.

llvm-svn: 84546
 2009-10-19 22:09:23 +00:00
Chris Lattner
8124977463 revert r84540, fixing build breakage I didn't see because of 
broken makefile deps :(

llvm-svn: 84544
 2009-10-19 21:59:25 +00:00
Chris Lattner
30baeae77d add addrmode2 support, getting us up to: 
_main:
	stm , 
	mov r7, sp
	sub sp, sp, #4
	mov r0, #0
	str r0, [sp]
	ldr r0, LCPI1_0
	bl _printf
	ldr r0, [sp]
	mov sp, r7
	ldm , 

llvm-svn: 84543
 2009-10-19 21:57:05 +00:00
Chris Lattner
ec500c80c6 add jump tables, constant pools and some trivial global 
lowering stuff.  We can now compile hello world to:

_main:
	stm , 
	mov r7, sp
	sub sp, sp, #4
	mov r0, #0
	str r0, 
	ldr r0, 
	bl _printf
	ldr r0, 
	mov sp, r7
	ldm , 

Almost looks like arm code :)

llvm-svn: 84542
 2009-10-19 21:53:00 +00:00
Chris Lattner
4b35be3f3b pass mangler in as a reference instead of a pointer. 
llvm-svn: 84540
 2009-10-19 21:45:31 +00:00
Chris Lattner
3755b735a0 reduce #includes 
llvm-svn: 84536
 2009-10-19 21:23:15 +00:00
Chris Lattner
4318ab8ce7 add printing support for SOImm operands, getting us to: 
_main:
	stm , 
	mov r7, sp
	sub sp, sp, #4
	mov r0, #0
	str r0, 

llvm-svn: 84535
 2009-10-19 21:21:39 +00:00
Chris Lattner
241c56bee6 wire up some basic printOperand goodness, giving us stuff like this before 
we abort:

_main:
	stm , 
	mov r7, sp
	sub sp, sp, 
	mov r0, 
	str r0, 

llvm-svn: 84532
 2009-10-19 20:59:55 +00:00
Chris Lattner
cd8bd77b64 add the files that go with the previous rev 
llvm-svn: 84531
 2009-10-19 20:21:05 +00:00
Chris Lattner
72c89de0e0 wire up skeletal support for having llc print instructions 
through mcinst lowering -> mcinstprinter, when llc is passed
the -enable-arm-mcinst-printer flag.  Currently this
is very "aborty".

llvm-svn: 84530
 2009-10-19 20:20:46 +00:00
Chris Lattner
d2f263e74f wire up ARM's printMCInst method. Now llvm-mc should be able to produce 
"something" when printing MCInsts, it will just be missing all the 
operand info.

llvm-svn: 84528
 2009-10-19 19:59:05 +00:00
Chris Lattner
11fcbad759 stub out a minimal ARMInstPrinter. 
llvm-svn: 84527
 2009-10-19 19:56:26 +00:00
Chris Lattner
cf8c23d554 remove strings from instructions who are never asmprinted. 
All of these "subreg32" modifier instructions are handled
explicitly by the MCInst lowering phase.  If they got to
the asmprinter, they would explode.  They should eventually
be replace with correct use of subregs.

llvm-svn: 84526
 2009-10-19 19:51:42 +00:00
Chris Lattner
e3469a4209 simplify code, reducing string thrashing. 
llvm-svn: 84521
 2009-10-19 18:49:14 +00:00
Chris Lattner
1816e314c6 switch hidden gv stubs to use MachineModuleInfoMachO instead of a custom map. 
llvm-svn: 84520
 2009-10-19 18:44:38 +00:00
Chris Lattner
b73edceec4 use MachineModuleInfoMachO for non-lazy gv stubs instead of a private map. 
llvm-svn: 84519
 2009-10-19 18:38:33 +00:00
Chris Lattner
e7ea33c824 remove dead map 
llvm-svn: 84513
 2009-10-19 18:11:25 +00:00
Chris Lattner
1598caa700 don't bother trying to avoid emitting redundant constant pool alignment directives. 
llvm-svn: 84512
 2009-10-19 18:08:02 +00:00
Chris Lattner
385ca4ca8a remove accidental comment. 
llvm-svn: 84510
 2009-10-19 18:03:41 +00:00
Chris Lattner
bddb00eadd emit .subsections_via_symbols through MCStreamer instead of textually. 
llvm-svn: 84509
 2009-10-19 18:03:08 +00:00
Chris Lattner
e53fff883a cleanup doFinalization -> EmitEndOfAsmFile. 
llvm-svn: 84508
 2009-10-19 17:59:19 +00:00
Nate Begeman
181b8fae1b PR 5245 - The imediate size target flag was not set on 3A-prefixed SSSE3 instructions. 
llvm-svn: 84506
 2009-10-19 17:31:16 +00:00
Torok Edwin
e6df0e6397 Fix PR5247, "lock addq" pattern (and other atomics), it DOES modify EFLAGS. 
LLC was scheduling compares before the adds causing wrong branches to be taken
in programs, resulting in misoptimized code wherever atomic adds where used.

llvm-svn: 84485
 2009-10-19 11:00:58 +00:00
Nate Begeman
1308a36647 Add support for matching shuffle patterns with palignr. 
llvm-svn: 84459
 2009-10-19 02:17:23 +00:00
Evan Cheng
eb82c3743a Turn on post-alloc scheduling for x86. 
llvm-svn: 84431
 2009-10-18 19:57:27 +00:00
Evan Cheng
1f32fa84b0 Oops. I forgot to change the tests first. Disable post-alloc scheduling. 
llvm-svn: 84425
 2009-10-18 18:31:31 +00:00
Evan Cheng
e921ebe70d -Revert parts of 84326 and 84411. Distinquishing between fixed and non-fixed 
stack slots and giving them different PseudoSourceValue's did not fix the
problem of post-alloc scheduling miscompiling llvm itself.
- Apply Dan's conservative workaround by assuming any non fixed stack slots can
alias other memory locations. This means a load from spill slot #1 cannot 
move above a store of spill slot #2. 
- Enable post-alloc scheduling for x86 at optimization leverl Default and above.

llvm-svn: 84424
 2009-10-18 18:16:27 +00:00
Evan Cheng
b40322ac49 Only fixed stack objects and spill slots should be get FixedStack PseudoSourceValue. 
llvm-svn: 84411
 2009-10-18 06:27:36 +00:00
Evan Cheng
5ab1ccfaee Distinquish stack slots from other stack objects. They (and fixed objects) get FixedStack PseudoSourceValues. 
llvm-svn: 84326
 2009-10-17 09:20:14 +00:00
Evan Cheng
d941e8b23a Revert 84315 for now. Re-thinking the patch. 
llvm-svn: 84321
 2009-10-17 07:53:04 +00:00
Evan Cheng
12dd96e2f8 Rename getFixedStack to getStackObject. The stack objects represented are not 
necessarily fixed. Only those will negative frame indices are "fixed."

llvm-svn: 84315
 2009-10-17 06:22:26 +00:00
Victor Hernandez
a25a2890fa Remove MallocInst from LLVM Instructions. 
llvm-svn: 84299
 2009-10-17 01:18:07 +00:00
Evan Cheng
e1fbdc5244 Change createPostRAScheduler so it can be turned off at llc -O1. 
llvm-svn: 84273
 2009-10-16 21:06:15 +00:00
Benjamin Kramer
9975abcc38 Update CMake file. 
llvm-svn: 84252
 2009-10-16 10:29:08 +00:00
Sanjiv Gupta
f516a9b2a4 Cleaned up some code. No functionality change. 
llvm-svn: 84251
 2009-10-16 08:58:34 +00:00
Evan Cheng
4df1ac5722 I am no spelling bee. 
llvm-svn: 84250
 2009-10-16 06:18:09 +00:00
Evan Cheng
b1580b5c48 Enable post-alloc scheduling for all ARM variants except for Thumb1. 
llvm-svn: 84249
 2009-10-16 06:11:08 +00:00
Evan Cheng
8685a8ec0c Add comment. 
llvm-svn: 84246
 2009-10-16 05:33:58 +00:00
Bob Wilson
c415e33929 Fix more NEON instruction encodings. 
Patch by Johnny Chen.

llvm-svn: 84243
 2009-10-16 03:58:44 +00:00
Bob Wilson
60ffc7b6b9 Revert svn r80498 and replace it with a different solution. The only problem 
I can see with the original code was that I forgot that this runs after
type legalization and hence the result type will always be i32. (Custom
legalization of EXTRACT_VECTOR_ELT is only enabled for vector types with
8- and 16-bit elements.)

Regarding the FIXME comment: any information about sign and zero-extension
should be captured by separate extension operations.  The DAG combiner should
handle those to produce either VGETLANEu or VGETLANEs, and that seems to be
working now.  If there are cases that we're missing, let me know.

llvm-svn: 84218
 2009-10-15 23:12:05 +00:00
Anton Korobeynikov
7d6c12de5b Dllexport stuff cleanup: 
1. Emit external function type information for all COFF targets since it's
a feature of object format
2. Emit linker directives only for cygming (since this is ld-specific stuff)

llvm-svn: 84214
 2009-10-15 22:36:18 +00:00
Sandeep Patel
c0762ba283 Branches must be the last instruction in a Thumb2 IT block. Approved by Evan Cheng. 
llvm-svn: 84212
 2009-10-15 22:25:32 +00:00
Bob Wilson
aa08dec009 Fix encoding bits for N3VLInt3_QHS multiclass with 8-bit elements. 
Patch by Johnny Chen.

llvm-svn: 84206
 2009-10-15 21:57:47 +00:00
Kevin Enderby
f2a8226515 Fix ARM memory operand parsing of post indexing with just a base register, that 
is just "[Rn]" and no tailing comma with an offset, etc.

llvm-svn: 84205
 2009-10-15 21:42:45 +00:00
Bob Wilson
cea08d0d4a Fix a potential performance problem in placing ARM constant pools. 
In the case where there are no good places to put constants and we fall back
upon inserting unconditional branches to make new blocks, allow all constant
pool references in range of those blocks to put constants there, even if that
means resetting the "high water marks" for those references.  This will still
terminate because you can't keep splitting blocks forever, and in the bad
cases where we have to split blocks, it is important to avoid splitting more
than necessary.

llvm-svn: 84202
 2009-10-15 20:49:47 +00:00
Kevin Enderby
48a0aac679 More bits of the ARM target assembler for llvm-mc, code added to parse labels 
as expressions, code for parsing a few arm specific directives (still needs
the MCStreamer calls for these).  Some clean up of the operand parsing code
and adding some comments.

llvm-svn: 84201
 2009-10-15 20:48:48 +00:00
Evan Cheng
0a57c7d459 Remove X86Subtarget::IsLinux. It's no longer being used. 
llvm-svn: 84200
 2009-10-15 20:23:21 +00:00
Benjamin Kramer
44c164e005 Add files Sanjiv forgot. 
llvm-svn: 84196
 2009-10-15 19:46:34 +00:00
Sanjiv Gupta
d279da3360 Re-apply 84180 with the fixed test case. 
llvm-svn: 84195
 2009-10-15 19:26:25 +00:00
Jakob Stoklund Olesen
311774b780 Move Blackfin intrinsics into the Target/Blackfin directory. 
llvm-svn: 84194
 2009-10-15 18:50:52 +00:00
Jakob Stoklund Olesen
2fe044dcb7 Clean up TargetIntrinsicInfo API. Add pure virtual methods. 
llvm-svn: 84192
 2009-10-15 18:49:26 +00:00
Daniel Dunbar
609b7287b8 Revert "Complete Rewrite of AsmPrinter, TargetObjectFile based on new 
PIC16Section class", it breaks globals.ll.

llvm-svn: 84184
 2009-10-15 15:02:14 +00:00
Sanjiv Gupta
feff117097 Complete Rewrite of AsmPrinter, TargetObjectFile based on new PIC16Section class 
derived from MCSection.

llvm-svn: 84180
 2009-10-15 10:10:43 +00:00
Sanjiv Gupta
cd427f0fbc Few changes to comply with new DebugInfo Metadata representation. 
llvm-svn: 84179
 2009-10-15 09:48:25 +00:00
Bob Wilson
53689872bd Be smarter about reusing constant pool entries. 
llvm-svn: 84173
 2009-10-15 05:52:29 +00:00
Bob Wilson
bfaed16c37 Fix another problem with ARM constant pools. Radar 7303551. 
When ARMConstantIslandPass cannot find any good locations (i.e., "water") to
place constants, it falls back to inserting unconditional branches to make a
place to put them.  My recent change exposed a problem in this area.  We may
sometimes append to the same block more than one unconditional branch.  The
symptoms of this are that the generated assembly has a branch to an undefined
label and running llc with -debug will cause a seg fault.

This happens more easily since my change to prevent CPEs from moving from
lower to higher addresses as the algorithm iterates, but it could have
happened before.  The end of the block may be in range for various constant
pool references, but the insertion point for new CPEs is not right at the end
of the block -- it is at the end of the CPEs that have already been placed
at the end of the block.  The insertion point could be out of range.  When
that happens, the fallback code will always append another unconditional
branch if the end of the block is in range.

The fix is to only append an unconditional branch if the block does not
already end with one.  I also removed a check to see if the constant pool load
instruction is at the end of the block, since that is redundant with
checking if the end of the block is in-range.

There is more to be done here, but I think this fixes the immediate problem.

llvm-svn: 84172
 2009-10-15 05:10:36 +00:00
Bob Wilson
db95c227fa Fix instruction encoding bits for NEON VPADAL. 
Patch by Johnny Chen.

llvm-svn: 84146
 2009-10-14 21:43:17 +00:00
Bob Wilson
1554029c7c Remove unused variables to fix build warning. 
llvm-svn: 84144
 2009-10-14 21:40:45 +00:00
Jim Grosbach
d86f233722 Inst{11-8} for vshl should be 0b0101, not 0b1111. 
Refs: A7-17 & A8-750.

Patch by Johnny Chen.

llvm-svn: 84131
 2009-10-14 20:31:01 +00:00
Bob Wilson
c9b704f66c Set instruction encoding bits 4 and 7 for ARM register-register and 
register-shifted-register instructions.  Patch by Johnny Chen.

llvm-svn: 84124
 2009-10-14 19:00:24 +00:00
Bob Wilson
320891060f Refactor code to select NEON VST intrinsics. 
llvm-svn: 84122
 2009-10-14 18:32:29 +00:00
Bob Wilson
2b19bbea06 Refactor code to select NEON VLD intrinsics. 
llvm-svn: 84117
 2009-10-14 17:28:52 +00:00
Bob Wilson
5dbe1c0143 More refactoring. NEON vst lane intrinsics can share almost all the code for 
vld lane intrinsics.

llvm-svn: 84110
 2009-10-14 16:46:45 +00:00
Bob Wilson
7623a1ce5c Refactor code for selecting NEON load lane intrinsics. 
llvm-svn: 84109
 2009-10-14 16:19:03 +00:00
Dan Gohman
76221cc874 Make isSafeToClobberEFLAGS more aggressive. Teach it to scan backwards 
(for uses marked kill and defs marked dead) a few instructions in
addition to forwards. Also, increase the maximum number of instructions
to scan, as it appears to help in a fair number of cases.

llvm-svn: 84061
 2009-10-14 00:08:59 +00:00
Kevin Enderby
8d8e57983a Correct comment about ARM immediates using '#' not '$' and TODO for modifiers. 
llvm-svn: 84055
 2009-10-13 23:33:38 +00:00
Devang Patel
72f708ec2f s/DebugLoc.CompileUnit/DebugLoc.Scope/g 
s/DebugLoc.InlinedLoc/DebugLoc.InlinedAtLoc/g

llvm-svn: 84054
 2009-10-13 23:28:53 +00:00
Bob Wilson
a98883deaa More Neon clean-up: avoid the need for custom-lowering vld/st-lane intrinsics 
by creating TargetConstants during instruction selection instead of during
legalization.

llvm-svn: 84042
 2009-10-13 22:29:24 +00:00
Kevin Enderby
959ec973ad More bits of the ARM target assembler for llvm-mc to parse immediates. 
Also fixed a couple of coding style things that crept in.  And added more
to the temporary hacked up ARMAsmParser::MatchInstruction() method for testing.

llvm-svn: 84040
 2009-10-13 22:19:02 +00:00
Bob Wilson
88df19e49a NEON VLD/VST are now fully implemented. For operations that expand to 
multiple instructions, the expansion is done during selection so there is
no need to do anything special during legalization.

llvm-svn: 84036
 2009-10-13 21:55:24 +00:00
Bob Wilson
d66a3fd73b Revise ARM inline assembly memory operands to require the memory address to 
be in a register.  The previous use of ARM address mode 2 was completely
arbitrary and inappropriate for Thumb.  Radar 7137468.

llvm-svn: 84022
 2009-10-13 20:50:28 +00:00
Sandeep Patel
af459ed32d Fix method name in comment, per Bob Wilson. 
llvm-svn: 84017
 2009-10-13 20:25:58 +00:00
Sandeep Patel
1584038783 Add ARMv6T2 SBFX/UBFX instructions. Approved by Anton Korobeynikov. 
llvm-svn: 84009
 2009-10-13 18:59:48 +00:00
Ted Kremenek
1f746d5df3 Update CMake file (lexically order files). 
llvm-svn: 84008
 2009-10-13 18:57:27 +00:00
Bob Wilson
747a6c0795 Add some ARM instruction encoding bits. 
Patch by Johnny Chen.

llvm-svn: 83983
 2009-10-13 17:35:30 +00:00
Bob Wilson
60d40281d3 Fix regression introduced by r83894. 
llvm-svn: 83982
 2009-10-13 17:29:13 +00:00
Bob Wilson
53fb652143 Fix a tab. Thanks to Johnny Chen for pointing it out. 
llvm-svn: 83973
 2009-10-13 15:27:23 +00:00
Kevin Enderby
c4125fbeb8 Fix two warnings about unused variables that are only used in assert() calls. 
llvm-svn: 83917
 2009-10-12 22:51:49 +00:00
Bob Wilson
3259a4106f Delete a comment that makes no sense to me. The statement that moving a CPE 
before its reference is only supported on ARM has not been true for a while.
In fact, until recently, that was only supported for Thumb.  Besides that,
CPEs are always a multiple of 4 bytes in size, so inserting a CPE should have
no effect on Thumb alignment.

llvm-svn: 83916
 2009-10-12 22:49:05 +00:00
Kevin Enderby
29f78ac638 Fix a problem in the code where ARMAsmParser::ParseShift() second argument 
should have been a pointer to a reference.

llvm-svn: 83915
 2009-10-12 22:39:54 +00:00
Bob Wilson
59435f24b1 Change CreateNewWater method to return NewMBB by reference. 
llvm-svn: 83905
 2009-10-12 21:39:43 +00:00
Bob Wilson
47c68e5cdf Last week, ARMConstantIslandPass was failing to converge for the 
MultiSource/Benchmarks/MiBench/automotive-susan test.  The failure has
since been masked by an unrelated change (just randomly), so I don't have
a testcase for this now.  Radar 7291928.

The situation where this happened is that a constant pool entry (CPE) was
placed at a lower address than the load that referenced it.  There were in
fact 2 CPEs placed at adjacent addresses and referenced by 2 loads that were
close together in the code.  The distance from the loads to the CPEs was
right at the limit of what they could handle, so that only one of the CPEs
could be placed within range.  On every iteration, the first CPE was found
to be out of range, causing a new CPE to be inserted.  The second CPE had
been in range but the newly inserted entry pushed it too far away.  Thus the
second CPE was also replaced by a new entry, which in turn pushed the first
CPE out of range.  Etc.

Judging from some comments in the code, the initial implementation of this
pass did not support CPEs placed _before_ their references.  In the case
where the CPE is placed at a higher address, the key to making the algorithm
terminate is that new CPEs are only inserted at the end of a group of adjacent
CPEs.  This is implemented by removing a basic block from the "WaterList"
once it has been used, and then adding the newly inserted CPE block to the
list so that the next insertion will come after it.  This avoids the ping-pong
effect where CPEs are repeatedly moved to the beginning of a group of
adjacent CPEs.  This does not work when going backwards, however, because the
entries at the end of an adjacent group of CPEs are closer than the CPEs
earlier in the group.

To make this pass terminate, we need to maintain a property that changes can
only happen in some sort of monotonic fashion.  The fix used here is to require
that the CPE for a particular constant pool load can only move to lower
addresses.  This is a very simple change to the code and should not cause
any significant degradation in the results.

llvm-svn: 83902
 2009-10-12 21:23:15 +00:00
Bob Wilson
de5c640673 Another minor clean-up. 
llvm-svn: 83897
 2009-10-12 20:45:53 +00:00
Bob Wilson
4c946b403f Remove redundant parameter. 
llvm-svn: 83894
 2009-10-12 20:37:23 +00:00
Bob Wilson
64169bce3d Use early exit to reduce indentation. 
llvm-svn: 83874
 2009-10-12 19:04:03 +00:00
Bob Wilson
13ae442741 Change to return a value by reference. 
llvm-svn: 83873
 2009-10-12 19:01:12 +00:00
Bob Wilson
2079cf41c5 Add a typedef for an iterator. 
llvm-svn: 83872
 2009-10-12 18:52:13 +00:00
Dale Johannesen
38c9b68ccf Revert the kludge in 76703. I got a clean 
bootstrap of FSF-style PPC, so there is some
reason to believe the original bug (which was
never analyzed) has been fixed, probably by
82266.

llvm-svn: 83871
 2009-10-12 18:49:00 +00:00
Dan Gohman
b5a0207b98 Don't forget to mark RAX as live-out of the function when arranging for 
it to hold the address of an sret return value, for x86-64 ABI purposes.

Also, fix the test that was originally intended to test this to actually
test it, using FileCheck.

llvm-svn: 83853
 2009-10-12 16:36:12 +00:00
Chris Lattner
667c067ee0 Fix PR5087, patch by Jakub Staszak! 
llvm-svn: 83822
 2009-10-12 04:22:44 +00:00
Anton Korobeynikov
deadc3ed2d Add missed mem-mem move patterns 
llvm-svn: 83812
 2009-10-11 23:03:53 +00:00
Anton Korobeynikov
986885b62e Add MSP430 mem-mem insts support. Patch by Brian Lucas with some my refinements 
llvm-svn: 83811
 2009-10-11 23:03:28 +00:00
Anton Korobeynikov
329def1675 Implement 'm' memory operand properly 
llvm-svn: 83785
 2009-10-11 19:14:21 +00:00
Anton Korobeynikov
4465f90db6 Implement proper asmprinting for the globals. This eliminates bogus "call" modifier and also adds support for offsets wrt globals. 
llvm-svn: 83784
 2009-10-11 19:14:02 +00:00
Anton Korobeynikov
1ca8655151 Implement asm printing for inline asm memory operands 
llvm-svn: 83783
 2009-10-11 19:13:34 +00:00
Anton Korobeynikov
1f9ff55cbc It seems that OR operation does not affect status reg at all. 
Remove impdef of SRW. This fixes PR4779

llvm-svn: 83739
 2009-10-10 22:17:47 +00:00
Dan Gohman
84a61978de Remove a no-longer-necessary #include. 
llvm-svn: 83697
 2009-10-10 00:36:09 +00:00
Dan Gohman
177b8de981 Replace X86's CanRematLoadWithDispOperand by calling the target-independent 
MachineInstr::isInvariantLoad instead, which has the benefit of being
more complete.

llvm-svn: 83696
 2009-10-10 00:34:18 +00:00
Dan Gohman
168ae2c7d5 Mark the LDR instruction with isReMaterializable, as it is rematerializable 
when loading from an invariant memory location.

llvm-svn: 83688
 2009-10-09 23:28:27 +00:00
Dan Gohman
14aaff93fc Add a const qualifier. 
llvm-svn: 83677
 2009-10-09 22:09:05 +00:00
Kevin Enderby
430e05312d Added another bit of the ARM target assembler to llvm-mc to parse register 
lists.  Changed ARMAsmParser::MatchRegisterName to return -1 instead of 0 on
errors so 0-15 values could be returned as register numbers.  Also added the
rest of the arm register names to the currently hacked up version to allow more
testing.  Some changes to ARMAsmParser::ParseOperand to give different errors
for things not yet supported and some additions to the hacked
ARMAsmParser::MatchInstruction to allow more testing for now.

llvm-svn: 83673
 2009-10-09 21:12:28 +00:00
Dan Gohman
f2ae9c6220 Fix the x86 test-shrink optimization so that it doesn't shrink comparisons 
when one of the bits being tested would end up being the sign bit in the
narrower type, and a signed comparison is being performed, since this would
change the result of the signed comparison. This fixes PR5132.

llvm-svn: 83670
 2009-10-09 20:35:19 +00:00
Dan Gohman
4fe1a982ed Add basic infrastructure and x86 support for preserving MachineMemOperand 
information when unfolding memory references.

llvm-svn: 83656
 2009-10-09 18:10:05 +00:00
Bob Wilson
8092fef09a Add codegen support for NEON vst4lane intrinsics with 128-bit vectors. 
llvm-svn: 83600
 2009-10-09 00:01:36 +00:00
Bob Wilson
979cb24a81 Add codegen support for NEON vst3lane intrinsics with 128-bit vectors. 
llvm-svn: 83598
 2009-10-08 23:51:31 +00:00
Bob Wilson
233992bc56 Add codegen support for NEON vst2lane intrinsics with 128-bit vectors. 
llvm-svn: 83596
 2009-10-08 23:38:24 +00:00
Bob Wilson
5b96a53ffe Add codegen support for NEON vld4lane intrinsics with 128-bit vectors. 
Also fix some copy-and-paste errors in previous changes.

llvm-svn: 83590
 2009-10-08 22:53:57 +00:00
Bob Wilson
7209d78713 Add codegen support for NEON vld3lane intrinsics with 128-bit vectors. 
llvm-svn: 83585
 2009-10-08 22:27:33 +00:00
Anton Korobeynikov
f9c811c948 Use lower16 / upper16 imm modifiers to asmprint 32-bit imms splitted via movt/movw pair. 
llvm-svn: 83572
 2009-10-08 20:43:22 +00:00
Bob Wilson
3a55fe2105 Add codegen support for NEON vld2lane intrinsics with 128-bit vectors. 
llvm-svn: 83568
 2009-10-08 18:56:10 +00:00
Bob Wilson
0159d0d864 Clean up some unnecessary initializations. 
llvm-svn: 83566
 2009-10-08 18:52:56 +00:00
Bob Wilson
c62c9946e2 Clean up a comment (indentation was wrong). 
llvm-svn: 83565
 2009-10-08 18:51:31 +00:00
Richard Osborne
5e56dfa489 Add missing names for the XCore specific LADD and LSUB nodes. 
llvm-svn: 83556
 2009-10-08 17:14:57 +00:00
Richard Osborne
1719935e3f Add some peepholes for signed comparisons using ashr X, X, 32. 
llvm-svn: 83549
 2009-10-08 15:38:17 +00:00
Bob Wilson
276bdabb9a Add codegen support for NEON vst4 intrinsics with <1 x i64> vectors. 
llvm-svn: 83526
 2009-10-08 05:18:18 +00:00
Jim Grosbach
9f57f9bee6 Cleanup up unused R3LiveIn tracking. 
llvm-svn: 83522
 2009-10-08 01:50:26 +00:00
Jim Grosbach
a3e1149941 Re-enable register scavenging in Thumb1 by default. 
llvm-svn: 83521
 2009-10-08 01:46:59 +00:00
Bob Wilson
8aa1d328b5 Add codegen support for NEON vst3 intrinsics with <1 x i64> vectors. 
llvm-svn: 83518
 2009-10-08 00:28:28 +00:00
Bob Wilson
958e4ae815 Add codegen support for NEON vst2 intrinsics with <1 x i64> vectors. 
llvm-svn: 83513
 2009-10-08 00:21:01 +00:00
Bob Wilson
729cd181a2 Add codegen support for NEON vld4 intrinsics with <1 x i64> vectors. 
llvm-svn: 83508
 2009-10-07 23:54:04 +00:00
Bob Wilson
3cbf156518 Add codegen support for NEON vld3 intrinsics with <1 x i64> vectors. 
llvm-svn: 83506
 2009-10-07 23:39:57 +00:00
Bob Wilson
0ffa9679a5 Add codegen support for NEON vld2 intrinsics with <1 x i64> vectors. 
llvm-svn: 83502
 2009-10-07 22:57:01 +00:00
Jim Grosbach
cb905d28a8 reverting thumb1 scavenging default due to test failure while I figure out what's up. 
llvm-svn: 83501
 2009-10-07 22:49:41 +00:00
Dale Johannesen
ba62bb565d Fix handling of x86 'R' constraint. 
llvm-svn: 83499
 2009-10-07 22:47:20 +00:00
Jim Grosbach
a9d83ba92c Enable thumb1 register scavenging by default. 
llvm-svn: 83494
 2009-10-07 22:26:14 +00:00
Bob Wilson
e7173601a3 Add some instruction encoding bits for NEON load/store instructions. 
llvm-svn: 83490
 2009-10-07 21:53:04 +00:00
Bob Wilson
cee91108da Add codegen support for NEON vst4 intrinsics with 128-bit vectors. 
llvm-svn: 83486
 2009-10-07 20:49:18 +00:00
Bob Wilson
af14187764 Add codegen support for NEON vst3 intrinsics with 128-bit vectors. 
llvm-svn: 83484
 2009-10-07 20:30:08 +00:00
Bob Wilson
62a3e55cea Add codegen support for NEON vst2 intrinsics with 128-bit vectors. 
llvm-svn: 83482
 2009-10-07 18:47:39 +00:00
Bob Wilson
9bb47b3e5d Add codegen support for NEON vld4 intrinsics with 128-bit vectors. 
llvm-svn: 83479
 2009-10-07 18:09:32 +00:00
Kevin Enderby
c0d0a1ec58 Add another bit of the ARM target assembler to llvm-mc to parse registers 
with writeback, things like "sp!", etc.  Also added some more stuff to the
temporarily hacked methods ARMAsmParser::MatchRegisterName and
ARMAsmParser::MatchInstruction to allow more parser testing.

llvm-svn: 83477
 2009-10-07 18:01:35 +00:00
Dan Gohman
b95136e649 Replace TargetInstrInfo::isInvariantLoad and its target-specific 
implementations with a new MachineInstr::isInvariantLoad, which uses
MachineMemOperands and is target-independent. This brings MachineLICM
and other functionality to targets which previously lacked an
isInvariantLoad implementation.

llvm-svn: 83475
 2009-10-07 17:38:06 +00:00
Bob Wilson
b38401ccef Add codegen support for NEON vld3 intrinsics with 128-bit vectors. 
llvm-svn: 83471
 2009-10-07 17:24:55 +00:00
Bob Wilson
a77f6a7814 Rearrange code for selecting vld2 intrinsics. No functionality change. 
This is just to be more consistent with the forthcoming code for vld3/4.

llvm-svn: 83470
 2009-10-07 17:23:09 +00:00
Jim Grosbach
61c5ce1bde Add register-reuse to frame-index register scavenging. When a target uses 
a virtual register to eliminate a frame index, it can return that register
and the constant stored there to PEI to track. When scavenging to allocate
for those registers, PEI then tracks the last-used register and value, and
if it is still available and matches the value for the next index, reuses
the existing value rather and removes the re-materialization instructions.
Fancier tracking and adjustment of scavenger allocations to keep more
values live for longer is possible, but not yet implemented and would likely
be better done via a different, less special-purpose, approach to the
problem.

eliminateFrameIndex() is modified so the target implementations can return
the registers they wish to be tracked for reuse.

ARM Thumb1 implements and utilizes the new mechanism. All other targets are
simply modified to adjust for the changed eliminateFrameIndex() prototype.

llvm-svn: 83467
 2009-10-07 17:12:56 +00:00
Anton Korobeynikov
aba66ae89b Add PseudoSourceValues for constpool stuff on ELF (Darwin should use something similar) 
and register spills.

llvm-svn: 83435
 2009-10-07 00:06:35 +00:00
Kevin Enderby
2c772c1ae9 Added bits of the ARM target assembler to llvm-mc to parse some load instruction 
operands.  Some parsing of arm memory operands for preindexing and postindexing
forms including with register controled shifts.  This is a work in progress.

llvm-svn: 83424
 2009-10-06 22:26:42 +00:00
Bob Wilson
8cd1ea81c4 Add codegen support for NEON vld2 operations on quad registers. 
llvm-svn: 83422
 2009-10-06 22:01:59 +00:00