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218 Commits

Author SHA1 Message Date
Jim Grosbach
f4442c2ca2 Cosmetic cleanup. No functional change. 
llvm-svn: 104974
 2010-05-28 17:51:20 +00:00
Jim Grosbach
2eb2c2d257 make sure accesses to set up the jmpbuf don't get moved after it by the scheduler. Add a missing \n. 
llvm-svn: 104967
 2010-05-28 17:37:40 +00:00
Jim Grosbach
b004e2cf0f Update the saved stack pointer in the sjlj function context following either 
an alloca() or an llvm.stackrestore(). rdar://8031573

llvm-svn: 104900
 2010-05-27 23:49:24 +00:00
Jim Grosbach
95c228acb0 fix off by 1 (insn) error in eh.sjlj.setjmp thumb code sequence. 
llvm-svn: 104661
 2010-05-26 01:22:21 +00:00
Jim Grosbach
b6cc69c655 Implement eh.sjlj.longjmp for ARM. Clean up the intrinsic a bit. 
Followups: docs patch for the builtin and eh.sjlj.setjmp cleanup to match
longjmp.

llvm-svn: 104419
 2010-05-22 01:06:18 +00:00
Evan Cheng
6f52107b12 t2LEApcrel and tLEApcrel are re-materializable. This makes it possible to hoist more loads during machine LICM. 
llvm-svn: 104115
 2010-05-19 07:28:01 +00:00
Evan Cheng
0aa58d5b69 Mark pattern-less mayLoad / mayStore instructions neverHasSideEffects. These do not have other un-modeled side effects. 
llvm-svn: 104111
 2010-05-19 06:07:03 +00:00
Evan Cheng
23fb523b44 Mark a few more pattern-less instructions with neverHasSideEffects. This is especially important on instructions like t2LEApcreal which are prime candidate for machine LICM. 
llvm-svn: 104102
 2010-05-19 01:52:25 +00:00
Bob Wilson
a748ca62cc Fix a regression in 464.h264 for thumb1 and thumb2 nightly tests. 
Obvious in retrospect but not fun to debug.

llvm-svn: 103969
 2010-05-17 20:31:13 +00:00
Anton Korobeynikov
a63555c10d Chris said that the comment char should be escaped. Fix all the occurences of "@" in *.td 
llvm-svn: 103903
 2010-05-16 09:15:36 +00:00
Anton Korobeynikov
4f8b48d8c6 "trap" pseudo-op turned out to be apple-local. 
Temporary emit it as raw bytes until it will be added to binutils as well.

llvm-svn: 103878
 2010-05-15 17:19:20 +00:00
Evan Cheng
11130a0a22 Select @llvm.trap to the special B with 1111 condition (i.e. trap) instruction. 
llvm-svn: 103459
 2010-05-11 07:26:32 +00:00
Chris Lattner
896b393fab set SDNPVariadic on nodes throughout the rest of the targets that 
need them.

llvm-svn: 98937
 2010-03-19 05:33:51 +00:00
Bob Wilson
279818d473 Remove the writeback flag from ARM's address mode 4. Now that we have separate 
instructions for ld/st with writeback, the flag is completely redundant.

llvm-svn: 98643
 2010-03-16 17:46:45 +00:00
Bob Wilson
0e8a3d7a13 Change ARM ld/st multiple instructions to have variant instructions for 
writebacks to the address register.  This gets rid of the hack that the
first register on the list was the magic writeback register operand.  There
was an implicit constraint that if that operand was not reg0 it had to match
the base register operand.  The post-RA scheduler's antidependency breaker
did not understand that constraint and sometimes changed one without the
other.  This also fixes Radar 7495976 and should help the verifier work
better for ARM code.

There are now new ld/st instructions explicit writeback operands and explicit
constraints that tie those registers together.

llvm-svn: 98409
 2010-03-13 01:08:20 +00:00
Johnny Chen
db62f78f10 Factored out the disassembly printing of CPS option, MSR mask, and Negative Zero 
operands into their own PrintMethod, in order not to pollute the printOperand()
impl with disassembly only Imm modifiers.

llvm-svn: 98172
 2010-03-10 18:59:38 +00:00
Johnny Chen
c903faa636 Modified the asm string of 16-bit Thumb MUL instruction so that it prints: 
MULS <Rdm>, <Rn>, <Rdm>

according to A8.6.105 MUL Encoding T1.

llvm-svn: 97675
 2010-03-03 23:15:43 +00:00
Johnny Chen
88f05c26a5 Added 32-bit Thumb instructions: CPS, SDIV, UDIV, SXTB16, SXTAB16, UXTAB16, SEL, 
SMMULR, SMMLAR, SMMLSR, TBB, TBH, and 16-bit Thumb instruction CPS for
disassembly only.

llvm-svn: 97573
 2010-03-02 18:14:57 +00:00
Dan Gohman
99c6bcbc13 The mayHaveSideEffects flag is no longer used. 
llvm-svn: 97348
 2010-02-27 23:47:46 +00:00
Johnny Chen
30a910f458 Added the following 16-bit Thumb instructions for disassembly only: YIELD, WFE, 
WFI, SEV, SETEND.

llvm-svn: 97149
 2010-02-25 17:51:03 +00:00
Johnny Chen
bbe3592817 Added tNOP for disassembly only. 
llvm-svn: 97105
 2010-02-25 03:28:51 +00:00
Johnny Chen
13b9bd479f Added tSVC and tTRAP for disassembly only. 
llvm-svn: 97098
 2010-02-25 02:21:11 +00:00
Jim Grosbach
c4ab116a90 Updated version of r96634 (which was reverted due to failing 176.gcc and 
126.gcc nightly tests. These failures uncovered latent bugs that machine DCE
could remove one half of a stack adjust down/up pair, causing PEI to assert.
This update fixes that, and the tests now pass.

llvm-svn: 96822
 2010-02-22 23:10:38 +00:00
Jim Grosbach
2acf602672 80 column cleanup 
llvm-svn: 96393
 2010-02-16 21:23:02 +00:00
Jim Grosbach
0c678d7b17 Remove trailing whitespace 
llvm-svn: 96388
 2010-02-16 21:07:46 +00:00
Johnny Chen
c6ca0de853 Added BKPT/tBKPT (breakpoint) to the instruction table for disassembly purpose. 
llvm-svn: 95884
 2010-02-11 18:12:29 +00:00
Jim Grosbach
bdc0ff13db Radar 7417921 
tMOVCCi pattern only valid for low registers, as the Thumb1 mov immediate to
register instruction only works with low registers. Allowing high registers
for the instruction resulted in the assembler choosing the wide (32-bit)
encoding for the mov, but LLVM though the instruction was only 16 bits wide,
so offset calculations for constant pools became incorrect, leading to
out of range constant pool entries.

llvm-svn: 95686
 2010-02-09 19:51:37 +00:00
Jim Grosbach
a7e098af3b tighten up eh.setjmp sequence a bit. 
llvm-svn: 95603
 2010-02-08 23:22:00 +00:00
Jim Grosbach
e96f9c1cab Adjust setjmp instruction sequence to not need 32-bit alignment padding 
llvm-svn: 94627
 2010-01-27 00:07:20 +00:00
Jim Grosbach
231a0d01a9 Fix PR5694. The CMN instructions set the flags differently from CMP, so they 
cannot be directly interchanged for comparisons against negated values.
Disable the CMN instructions for the time being.

llvm-svn: 94119
 2010-01-22 00:08:13 +00:00
Johnny Chen
a5f79a6b93 The most significant encoding bit of GPR:$src or GPR:$dst was over-specified in 
the various MOV (register) instructions (16-bit Thumb), including tBRIND (the
indirect branch).  Instead of '1', it should be specified as '?', because GPR
only specifies the register class, which includes both hi-and-lo registers.

llvm-svn: 93759
 2010-01-18 20:15:56 +00:00
Johnny Chen
a5f2e84b0c Added 16-bit Thumb Load/Store immediate instructions with encoding bits so that 
the disassembler can properly decode Load/Store register/immediate instructions.

llvm-svn: 93471
 2010-01-14 22:42:17 +00:00
Johnny Chen
08c211683b Fixed a couple of places for Thumb MOV where encoding bits are underspecified. 
llvm-svn: 93349
 2010-01-13 21:00:26 +00:00
Jakob Stoklund Olesen
2d819b93a2 Remove the JustSP single-register regclass. 
It was only being used by instructions with the t_addrmode_sp addressing mode,
and that is pattern matched in a way that guarantees SP is used. There is
never any register allocation done from this class.

llvm-svn: 93280
 2010-01-13 00:43:06 +00:00
Jakob Stoklund Olesen
9d1c8ecf05 Add a SPR register class to the ARM target. 
Certain Thumb instructions require only SP (e.g. tSTRspi).

llvm-svn: 91944
 2009-12-22 23:54:44 +00:00
Johnny Chen
04b3259f9d Renamed "tCMNZ" to "tCMNz" to be consistent with other similar namings. 
llvm-svn: 91571
 2009-12-16 23:36:52 +00:00
Johnny Chen
7339b74117 Add encoding bits for some Thumb instructions. Plus explicitly set the top two 
bytes of Inst to 0x0000 for the benefit of the Thumb decoder.

llvm-svn: 91496
 2009-12-16 02:32:54 +00:00
Johnny Chen
8ef481b5d7 Added encoding bits for the Thumb ISA. Initial checkin. 
llvm-svn: 91434
 2009-12-15 17:24:14 +00:00
Jim Grosbach
5541b5f793 Thumb1 exception handling setjmp 
llvm-svn: 90246
 2009-12-01 18:10:36 +00:00
Evan Cheng
9f57c4916e Remat VLDRD from constpool. Clean up some instruction property specifications. 
llvm-svn: 89478
 2009-11-20 19:57:15 +00:00
Evan Cheng
987b8c3d9a More consistent thumb1 asm printing. 
llvm-svn: 89328
 2009-11-19 06:57:41 +00:00
Evan Cheng
6e3e66375a - Add pseudo instructions tLDRpci_pic and t2LDRpci_pic which does a pc-relative 
load of a GV from constantpool and then add pc. It allows the code sequence to
  be rematerializable so it would be hoisted by machine licm.
- Add a late pass to break these pseudo instructions into a number of real
  instructions. Also move the code in Thumb2 IT pass that breaks up t2MOVi32imm
  to this pass. This is done before post regalloc scheduling to allow the
  scheduler to proper schedule these instructions. It also allow them to be
  if-converted and shrunk by later passes.

llvm-svn: 86304
 2009-11-06 23:52:48 +00:00
Evan Cheng
22121f4c69 The .n suffix must go after the predicate. 
llvm-svn: 86019
 2009-11-04 07:38:48 +00:00
Evan Cheng
1a06b12330 Use ldr.n to workaround a darwin assembler bug. 
llvm-svn: 85980
 2009-11-04 00:00:39 +00:00
Bob Wilson
97331f70ca For Thumb indirect branches, use "mov pc, reg" which does not switch 
between ARM/Thumb modes and does not require the low bit of the target
address to be set for Thumb.

llvm-svn: 85874
 2009-11-03 06:29:56 +00:00
Bob Wilson
3144715b53 Put BlockAddresses into ARM constant pools. 
llvm-svn: 85824
 2009-11-02 20:59:23 +00:00
Evan Cheng
de16fff3e8 Use cbz and cbnz instructions. 
llvm-svn: 85698
 2009-10-31 23:46:45 +00:00
Bob Wilson
95064e348a Add ARM codegen for indirect branches. 
clang/test/CodeGen/indirect-goto.c runs! (unoptimized)

llvm-svn: 85577
 2009-10-30 05:45:42 +00:00
Dan Gohman
3393a4c997 Rename usesCustomDAGSchedInserter to usesCustomInserter, and update a 
bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.

llvm-svn: 85517
 2009-10-29 18:10:34 +00:00
Bob Wilson
af37728221 Add a Thumb BRIND pattern. Change the ARM BRIND assembly to separate the 
opcode and operand with a tab.  Check for these instructions in the usual
places.

llvm-svn: 85411
 2009-10-28 18:26:41 +00:00
Evan Cheng
f30e5556ba Change Thumb1 and Thumb2 instructions to separate opcode from operands with a tab instead of a space. 
llvm-svn: 85184
 2009-10-27 00:08:59 +00:00
Evan Cheng
241092d89f Add hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq flags to ld / st multiple, 
ld / st pairs, etc.

llvm-svn: 83197
 2009-10-01 08:22:27 +00:00
Evan Cheng
4dd7d7156e Change ld/st multiples to explicitly model the writeback to base register. This fixes most of the -ldstopti-before-sched2 regressions. 
llvm-svn: 83191
 2009-10-01 01:33:39 +00:00
Jim Grosbach
2d057f09e8 Add "isBarrier = 1" to return instructions. 
Patch by Sylvere Teissier.

llvm-svn: 83135
 2009-09-30 01:35:11 +00:00
Evan Cheng
6c89bc0472 Remove comments which don't add much to .s readibility. 
llvm-svn: 81306
 2009-09-09 01:38:23 +00:00
David Goodwin
0dd9e9edb4 Calls clobber FPSCR. 
llvm-svn: 80956
 2009-09-03 22:12:28 +00:00
Evan Cheng
493eee1fc7 Remove .n suffix for some 16-bit opcodes now that Darwin assembler is fixed. 
llvm-svn: 80615
 2009-08-31 20:14:07 +00:00
Evan Cheng
d53546a6cd Print a nl before pic labels so they start at a new line. This makes assembly more readable. 
llvm-svn: 80350
 2009-08-28 06:59:37 +00:00
Evan Cheng
2d5d3700e9 v4, v5 does not support sxtb / sxth. 
llvm-svn: 80322
 2009-08-28 00:31:43 +00:00
Bob Wilson
9482015a0a Rename ARM "lane_cst" operands to "nohash_imm" since they are used for 
several things other than Neon vector lane numbers.  For inline assembly
operands with a "c" print code, check that they really are immediates.

llvm-svn: 79676
 2009-08-21 21:58:55 +00:00
Evan Cheng
86546fb692 Fix an obvious copy-n-paste bug. 
llvm-svn: 79535
 2009-08-20 17:01:04 +00:00
David Goodwin
d57f44783c Update Cortex-A8 instruction itineraries for integer instructions. 
llvm-svn: 79436
 2009-08-19 18:00:44 +00:00
Evan Cheng
d4d2a3d0a6 Fix revsh pattern. 
llvm-svn: 79318
 2009-08-18 05:43:23 +00:00
Evan Cheng
7d8caa143b Also shrink immediate branches; also more assembler workarounds. 
llvm-svn: 79014
 2009-08-14 18:31:44 +00:00
Evan Cheng
45d6a21e21 Shrink ADR and LDR from constantpool late during constantpool island pass. 
llvm-svn: 78970
 2009-08-14 00:32:16 +00:00
David Goodwin
dd797db6bd Finalize itineraries for cortex-a8 integer multiply 
llvm-svn: 78908
 2009-08-13 15:51:13 +00:00
David Goodwin
90e7f9873c Enhance the InstrStage object to enable the specification of an Itinerary with overlapping stages. The default is to maintain the current behavior that the "next" stage immediately follows the previous one. 
llvm-svn: 78827
 2009-08-12 18:31:53 +00:00
Evan Cheng
c369ccbe83 Shrink Thumb2 movcc instructions. 
llvm-svn: 78790
 2009-08-12 05:17:19 +00:00
Evan Cheng
410447e028 80 col violation. 
llvm-svn: 78778
 2009-08-12 02:03:03 +00:00
Evan Cheng
a29ee9f509 Shrinkify Thumb2 r = add sp, imm. 
llvm-svn: 78745
 2009-08-11 23:00:31 +00:00
Evan Cheng
783028063e Shrinkify Thumb2 load / store multiple instructions. 
llvm-svn: 78717
 2009-08-11 21:11:32 +00:00
Owen Anderson
48f2f0ae72 Split EVT into MVT and EVT, the former representing _just_ a primitive type, while 
the latter is capable of representing either a primitive or an extended type.

llvm-svn: 78713
 2009-08-11 20:47:22 +00:00
Owen Anderson
b4bce99769 Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type. 
llvm-svn: 78610
 2009-08-10 22:56:29 +00:00
Evan Cheng
ad380aa97a Add support to reduce most of 32-bit Thumb2 arithmetic instructions. 
llvm-svn: 78550
 2009-08-10 02:37:24 +00:00
Anton Korobeynikov
44fa9f179c Use subclassing to print lane-like immediates (w/o hash) eliminating 
'no_hash' modifier. Hopefully this will make Daniel happy :)

llvm-svn: 78514
 2009-08-08 23:10:41 +00:00
Evan Cheng
fb833354b6 tADDhirr should target GPR, not tGPR. 
llvm-svn: 78454
 2009-08-08 03:19:44 +00:00
Evan Cheng
5af3c8154b tBfar is bl, which clobbers LR. 
llvm-svn: 78370
 2009-08-07 05:45:07 +00:00
Evan Cheng
48b49cf5b9 It turns out most of the thumb2 instructions are not allowed to touch SP. The semantics of such instructions are unpredictable. We have just been lucky that tests have been passing. 
This patch takes pain to ensure all the PEI lowering code does the right thing when lowering frame indices, insert code to manipulate stack pointers, etc. It's also custom lowering dynamic stack alloc into pseudo instructions so we can insert the right instructions at scheduling time.

This fixes PR4659 and PR4682.

llvm-svn: 78361
 2009-08-07 00:34:42 +00:00
David Goodwin
3aafcc1dd2 Add parameter to pattern classes to enable an itinerary to be specified for instructions. For now just use the existing itineraries or NoItinerary. 
llvm-svn: 78321
 2009-08-06 16:52:47 +00:00
Evan Cheng
e366789b50 Fix part 1 of pr4682. PICADD is a 16-bit instruction even in thumb2 mode. 
llvm-svn: 78126
 2009-08-04 23:47:55 +00:00
Evan Cheng
5ef6928dff Fix Thumb2 function call isel. Thumb1 and Thumb2 should share the same 
instructions for calls since BL and BLX are always 32-bit long and BX is always
16-bit long.

Also, we should be using BLX to call external function stubs.

llvm-svn: 77756
 2009-08-01 00:16:10 +00:00
Evan Cheng
90a1ca6e17 Make sure Thumb2 uses the right call instructions. 
llvm-svn: 77507
 2009-07-29 21:26:42 +00:00
Evan Cheng
c8d3891c87 - Fix an obvious copy and paste error. 
- Darwin Thumb2 call clobbers r9.

llvm-svn: 77500
 2009-07-29 20:10:36 +00:00
Evan Cheng
cf483eb0c0 In thumb2 mode, add pc is unpredictable. Use add + mov pc instead (that is until more optimization goes in). 
llvm-svn: 77364
 2009-07-28 20:53:24 +00:00
David Goodwin
6ff3fd8021 Remove TPat. No patterns depend on just isThumb(). Must use either T1Pat (isThumb1Only()) or T2Pat (is Thumb2). 
llvm-svn: 77242
 2009-07-27 19:59:26 +00:00
Evan Cheng
a6737e21cf Rename tMOVhi2lor to tMOVgpr2tgpr. It's not moving from a high register to a low register. It's moving from a GPR register class to a more restrictive tGPR class. Also change tMOVlor2hir, and tMOVhir2hir. 
llvm-svn: 77172
 2009-07-26 23:59:01 +00:00
Evan Cheng
8997f6bfc1 Since we have moved unified assembly, switch to ADR instruction instead of a the difficult-to-read .set + add syntax to materialize pc-relative address. 
Turns out this also fixed a poor code selection on Thumb1. I have no idea why we were using a mov + add to do the same thing as ADR before.

llvm-svn: 76889
 2009-07-23 18:26:03 +00:00
Evan Cheng
4a77f28c47 Use getTargetConstant instead of getConstant since it's meant as an constant operand. 
llvm-svn: 76803
 2009-07-22 22:03:29 +00:00
Evan Cheng
34576850e1 Don't forget D16 - D31 are clobbered by calls and sjlj eh. 
llvm-svn: 76729
 2009-07-22 06:46:53 +00:00
Evan Cheng
4fdb43a89d Add R12 to the list of registers clobbered by 16-bit Thumb calls as a pre-caution. r12 could be live once we have mixed 32-bit and 16-bit instructions. 
llvm-svn: 76728
 2009-07-22 06:37:28 +00:00
Evan Cheng
192fc19379 Do not select tSXTB / tSXTH in thumb2 mode. 
llvm-svn: 76600
 2009-07-21 18:15:26 +00:00
Evan Cheng
490d2cc5a4 Fix tSUBspi operand definition. It reads and writes sp, which is a high register. 
llvm-svn: 76155
 2009-07-17 05:43:12 +00:00
Evan Cheng
b8666f7abc 1. In Thumb mode, select tBx instead of ARM variants. 
2. BX does not "use" the link register, it defines it.
3. Fix a couple more places in thumb td file that still uses pre-UAL syntax.

llvm-svn: 75585
 2009-07-14 01:49:27 +00:00
Evan Cheng
03d981d91b Smarter isel of ldrsb / ldrsh. Only make use of these when [r,r] address is feasible. 
llvm-svn: 75360
 2009-07-11 07:08:13 +00:00
Evan Cheng
268b47b1fb Major changes to Thumb (not Thumb2). Many 16-bit instructions either modifies CPSR when they are outside the IT blocks, or they can predicated when in Thumb2. Move the implicit def of CPSR to an optional def which defaults CPSR. This allows the 's' bit to be toggled dynamically. 
A side-effect of this change is asm printer is now using unified assembly. There are some minor clean ups and fixes as well.

llvm-svn: 75359
 2009-07-11 06:43:01 +00:00
Evan Cheng
74f5327e53 We don't need separate thumb1 instructions tADDSi3 etc. for addc and subc. The "normal" version always modify condition register CPSR so we should just use def : pat to match to the same instructions. 
llvm-svn: 75219
 2009-07-10 02:09:04 +00:00
Evan Cheng
24f2aefc87 Add a thumb2 pass to insert IT blocks. 
llvm-svn: 75218
 2009-07-10 01:54:42 +00:00
Evan Cheng
1b15e9611e Added Thumb IT instruction. 
llvm-svn: 75198
 2009-07-09 23:43:36 +00:00
David Goodwin
49fbd8d6b7 Use common code for both ARM and Thumb-2 instruction and register info. 
llvm-svn: 75067
 2009-07-08 23:10:31 +00:00
David Goodwin
5bdef4b3f7 Checkpoint Thumb2 Instr info work. Generalized base code so that it can be shared between ARM and Thumb2. Not yet activated because register information must be generalized first. 
llvm-svn: 75010
 2009-07-08 16:09:28 +00:00