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ca062e81db
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66 Commits

Author SHA1 Message Date
Chad Rosier
ca062e81db [AArch64] Add support for NEON scalar floating-point absolute difference. 
llvm-svn: 195803
 2013-11-27 01:45:58 +00:00
Chad Rosier
1337fcc721 [AArch64] Add support for NEON scalar floating-point to integer convert 
instructions.

llvm-svn: 195788
 2013-11-26 22:17:37 +00:00
Ana Pazos
86d72bbede Implemented Neon scalar vdup_lane intrinsics. 
Fixed scalar dup alias and added test case.

llvm-svn: 195330
 2013-11-21 08:16:15 +00:00
Hao Liu
b26dfe0306 Implement AArch64 neon instructions class SIMD lsone and SIMD lone-post. 
llvm-svn: 195078
 2013-11-19 02:17:05 +00:00
Kevin Qin
7b74269765 implement MC layer of AArch64 neon instruction PMULL and PMULL2 with 128 bit integer. 
llvm-svn: 195072
 2013-11-19 01:40:25 +00:00
Jiangning Liu
7c858f236d Add predicate for AArch64 crypto instructions. 
llvm-svn: 195071
 2013-11-19 01:38:31 +00:00
Kevin Qin
eb2e892703 [AArch64 NEON]Add mov alias for simd copy instructions. 
Set some unspecified bits of INS/DUP to zero as ARMARM requested.

llvm-svn: 194996
 2013-11-18 09:20:32 +00:00
Kevin Qin
0b4fc92580 Add test case for AArch64 NEON instruction set misc. 
llvm-svn: 194673
 2013-11-14 06:45:17 +00:00
Kevin Qin
47a3b639e3 Implement aarch64 neon instruction class SIMD misc. 
llvm-svn: 194656
 2013-11-14 02:44:13 +00:00
Jiangning Liu
5a9b5605ba Implement AArch64 NEON instruction set AdvSIMD (table). 
llvm-svn: 194648
 2013-11-14 01:57:32 +00:00
Chad Rosier
ba5d2d1be6 [AArch64] Implemented AdvSIMD scalar x indexed element format and AdvSIMD scalar 
copy in MC layer. Added the MC layer tests.  Fixed triple setting in test cases.

Patch by Ana Pazos <apazos@codeaurora.org>.

llvm-svn: 194501
 2013-11-12 19:13:08 +00:00
Chad Rosier
4848250116 [AArch64] Add support for NEON scalar floating-point convert to fixed-point instructions. 
llvm-svn: 194394
 2013-11-11 18:04:07 +00:00
Jiangning Liu
9c0eb8e7ba Implement AArch64 Neon instruction set Perm. 
llvm-svn: 194123
 2013-11-06 03:35:27 +00:00
Jiangning Liu
1cdd311f06 Implement AArch64 Neon instruction set Bitwise Extract. 
llvm-svn: 194118
 2013-11-06 02:25:49 +00:00
Jiangning Liu
59b8117b0b Implement AArch64 Neon Crypto instruction classes AES, SHA, and 3 SHA. 
llvm-svn: 194085
 2013-11-05 17:42:05 +00:00
Hao Liu
386d8dd5a6 Implement AArch64 post-index vector load/store multiple N-element structure class SIMD(lselem-post). 
Including following 14 instructions:
4 ld1 insts: post-index load multiple 1-element structure to sequential 1/2/3/4 registers.
ld2/ld3/ld4: post-index load multiple N-element structure to sequential N registers (N=2,3,4).
4 st1 insts: post-index store multiple 1-element structure from sequential 1/2/3/4 registers.
st2/st3/st4: post-index store multiple N-element structure from sequential N registers (N = 2,3,4).

llvm-svn: 194043
 2013-11-05 03:39:32 +00:00
Chad Rosier
fd7dc7524c [AArch64] Add support for NEON scalar fixed-point convert to floating-point instructions. 
llvm-svn: 193816
 2013-10-31 22:36:59 +00:00
Chad Rosier
b603d15176 [AArch64] Add diagnostic tests for NEON scalar shift immediate instructions (see: r193790). 
llvm-svn: 193798
 2013-10-31 20:11:32 +00:00
Chad Rosier
aea5ba449f [AArch64] Add support for NEON scalar shift immediate instructions. 
llvm-svn: 193790
 2013-10-31 19:28:44 +00:00
Amara Emerson
ce9bb052e5 [AArch64] Make the use of FP instructions optional, but enabled by default. 
This adds a new subtarget feature called FPARMv8 (implied by NEON), and
predicates the support of the FP instructions and registers on this feature.

llvm-svn: 193739
 2013-10-31 09:32:11 +00:00
Chad Rosier
02e430c891 [AArch64] Add support for NEON scalar floating-point compare instructions. 
llvm-svn: 193691
 2013-10-30 15:19:37 +00:00
Rafael Espindola
5f82bc3329 Convert another llc -filetype=obj test. 
llvm-svn: 193538
 2013-10-28 21:06:12 +00:00
Rafael Espindola
4272a090a0 Convert another llc -filetype=obj test. 
llvm-svn: 193537
 2013-10-28 20:59:41 +00:00
Rafael Espindola
00f2d95c0c Convert another llc -filetype=obj test. 
llvm-svn: 193536
 2013-10-28 20:54:33 +00:00
Rafael Espindola
c4c4f23851 Convert a llc -filetype=obj test into a llvm-mc test. 
llvm-svn: 193534
 2013-10-28 20:40:20 +00:00
Chad Rosier
163fdd3e73 [AArch64] Add support for NEON scalar extract narrow instructions. 
llvm-svn: 192970
 2013-10-18 14:03:24 +00:00
Chad Rosier
9a6d485c7f [AArch64] Add support for NEON scalar three register different instruction 
class.  The instruction class includes the signed saturating doubling
multiply-add long, signed saturating doubling multiply-subtract long, and
the signed saturating doubling multiply long instructions.

llvm-svn: 192908
 2013-10-17 18:12:29 +00:00
Chad Rosier
3ed3565e0f [AArch64] Add support for NEON scalar negate instruction. 
llvm-svn: 192843
 2013-10-16 21:04:39 +00:00
Chad Rosier
aaa3bb367a [AArch64] Add support for NEON scalar absolute value instruction. 
llvm-svn: 192842
 2013-10-16 21:04:34 +00:00
Chad Rosier
929e07c8ea Update comment. 
llvm-svn: 192806
 2013-10-16 16:30:10 +00:00
Chad Rosier
a195d145b8 [AArch64] Add support for NEON scalar signed saturating accumulated of unsigned 
value and unsigned saturating accumulate of signed value instructions.

llvm-svn: 192800
 2013-10-16 16:09:02 +00:00
Chad Rosier
3e791b2408 [AArch64] Add support for NEON scalar signed saturating absolute value and 
scalar signed saturating negate instructions.

llvm-svn: 192733
 2013-10-15 21:18:44 +00:00
Chad Rosier
40761dc629 [AArch64] Add support for NEON scalar integer compare instructions. 
llvm-svn: 192596
 2013-10-14 14:37:20 +00:00
Kevin Qin
e90902acc5 Implement aarch64 neon instruction set AdvSIMD (copy). 
llvm-svn: 192410
 2013-10-11 02:33:55 +00:00
Hao Liu
d0ab407a23 Implement AArch64 vector load/store multiple N-element structure class SIMD(lselem). 
Including following 14 instructions:
4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers.
ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4).
4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers.
st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4).

llvm-svn: 192361
 2013-10-10 17:00:52 +00:00
Rafael Espindola
bb93e39fe2 Revert "Implement AArch64 vector load/store multiple N-element structure class SIMD(lselem). Including following 14 instructions: 4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers. ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4). 4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers. st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4)." 
This reverts commit r192352. It broke the build.

llvm-svn: 192354
 2013-10-10 15:15:17 +00:00
Hao Liu
0ff11c9c71 Implement AArch64 vector load/store multiple N-element structure class SIMD(lselem). 
Including following 14 instructions:
4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers.
ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4).
4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers.
st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4).

llvm-svn: 192352
 2013-10-10 15:01:24 +00:00
Tim Northover
a9df6657ee AArch64: migrate ADRP relaxation test to be llvm-mc only. 
llvm-svn: 192281
 2013-10-09 07:53:49 +00:00
Chad Rosier
d30c4af71b [AArch64] Add support for NEON scalar floating-point reciprocal estimate, 
reciprocal exponent, and reciprocal square root estimate instructions.

llvm-svn: 192242
 2013-10-08 22:09:04 +00:00
Chad Rosier
e281a17b84 [AArch64] Add support for NEON scalar signed/unsigned integer to floating-point 
convert instructions.

llvm-svn: 192231
 2013-10-08 20:43:30 +00:00
Chad Rosier
128d9134e7 [AArch64] Add support for NEON scalar arithmetic instructions: 
SQDMULH, SQRDMULH, FMULX, FRECPS, and FRSQRTS.

llvm-svn: 192107
 2013-10-07 16:36:15 +00:00
Jiangning Liu
6d9b4a0e25 Implement aarch64 neon instruction set AdvSIMD (Across). 
llvm-svn: 192028
 2013-10-05 08:22:10 +00:00
Jiangning Liu
9f33a743ab Implement aarch64 neon instruction set AdvSIMD (3V elem). 
llvm-svn: 191944
 2013-10-04 09:20:44 +00:00
Jiangning Liu
5867567c41 Initial support for Neon scalar instructions. 
Patch by Ana Pazos.

1.Added support for v1ix and v1fx types.
2.Added Scalar Pairwise Reduce instructions.
3.Added initial implementation of Scalar Arithmetic instructions.

llvm-svn: 191263
 2013-09-24 02:47:27 +00:00
Kevin Qin
3be5824550 Implement 3 AArch64 neon instructions : umov smov ins. 
llvm-svn: 190839
 2013-09-17 02:21:02 +00:00
Tim Northover
5eefec9e6d AArch64: use RegisterOperand for NEON registers. 
Previously we modelled VPR128 and VPR64 as essentially identical
register-classes containing V0-V31 (which had Q0-Q31 as "sub_alias"
sub-registers). This model is starting to cause significant problems
for code generation, particularly writing EXTRACT/INSERT_SUBREG
patterns for converting between the two.

The change here switches to classifying VPR64 & VPR128 as
RegisterOperands, which are essentially aliases for RegisterClasses
with different parsing and printing behaviour. This fits almost
exactly with their real status (VPR128 == FPR128 printed strangely,
VPR64 == FPR64 printed strangely).

llvm-svn: 190665
 2013-09-13 07:26:52 +00:00
Jiangning Liu
b2cc9767e4 Implement aarch64 neon instruction set AdvSIMD (3V Diff), covering the following 26 instructions, 
SADDL, UADDL, SADDW, UADDW, SSUBL, USUBL, SSUBW, USUBW, ADDHN, RADDHN, SABAL, UABAL, SUBHN, RSUBHN, SABDL, UABDL, SMLAL, UMLAL, SMLSL, UMLSL, SQDMLAL, SQDMLSL, SMULL, UMULL, SQDMULL, PMULL

llvm-svn: 190288
 2013-09-09 02:20:27 +00:00
Hao Liu
b344ca7aa3 Inplement aarch64 neon instructions in AdvSIMD(shift). About 24 shift instructions: 
sshr,ushr,ssra,usra,srshr,urshr,srsra,ursra,sri,shl,sli,sqshlu,sqshl,uqshl,shrn,sqrshrun,sqshrn,uqshr,sqrshrn,uqrshrn,sshll,ushll
 and 4 convert instructions:
      scvtf,ucvtf,fcvtzs,fcvtzu

llvm-svn: 189925
 2013-09-04 09:28:24 +00:00
Daniel Dunbar
a496d61c01 [tests] Cleanup initialization of test suffixes. 
- Instead of setting the suffixes in a bunch of places, just set one master
   list in the top-level config. We now only modify the suffix list in a few
   suites that have one particular unique suffix (.ml, .mc, .yaml, .td, .py).

 - Aside from removing the need for a bunch of lit.local.cfg files, this enables
   4 tests that were inadvertently being skipped (one in
   Transforms/BranchFolding, a .s file each in DebugInfo/AArch64 and
   CodeGen/PowerPC, and one in CodeGen/SI which is now failing and has been
   XFAILED).

 - This commit also fixes a bunch of config files to use config.root instead of
   older copy-pasted code.

llvm-svn: 188513
 2013-08-16 00:37:11 +00:00
Hao Liu
ad6d3a3db7 Clang and AArch64 backend patches to support shll/shl and vmovl instructions and ACLE functions 
llvm-svn: 188451
 2013-08-15 08:26:11 +00:00