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Commit Graph

7677 Commits

Author SHA1 Message Date
Andrew Trick
777b242083 Update physreg live intervals during remat.
llvm-svn: 184574
2013-06-21 18:33:26 +00:00
Quentin Colombet
bdb6bfd975 ARM: Remove a (false) dependency on the memoryoperand's value as we do not use
it at the moment.
This allows to form more paired loads even when stack coloring pass destroys the
memoryoperand's value.

<rdar://problem/13978317>

llvm-svn: 184492
2013-06-20 22:51:44 +00:00
Tom Stellard
a1d0e771db R600/SI: Expand sub for v2i32 and v4i32 for SI
Also add a v2i32 test to the existing v4i32 test.

Patch by: Aaron Watry

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Aaron Watry<awatry@gmail.com>
llvm-svn: 184482
2013-06-20 21:55:37 +00:00
Tom Stellard
c419716668 R600/SI: Expand add for v2i32 and v4i32
Also add SI tests to existing file and a v2i32 test for both
R600 and SI.

Patch by: Aaron Watry

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Aaron Watry <awatry@gmail.com>
llvm-svn: 184481
2013-06-20 21:55:30 +00:00
Tom Stellard
a6ec00250a R600: Expand v2i32 load/store instead of custom lowering
The custom lowering causes llc to crash with a segfault.

Ideally, the custom lowering can be fixed, but this allows
programs which load/store v2i32 to work without crashing.

Patch by: Aaron Watry

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Aaron Watry<awatry@gmail.com>
llvm-svn: 184480
2013-06-20 21:55:23 +00:00
David Blaikie
e21853eb2f DebugInfo: don't use location lists when the location covers the whole function anyway
Fix up three tests - one that was relying on abbreviation number,
another relying on a location list in this case (& testing raw asm,
changed that to use dwarfdump on the debug_info now that that's where
the location is), and another which was added in r184368 - exposing a
bug in that fix that is exposed when we emit the location inline rather
than through a location list. Fix that bug while I'm here.

llvm-svn: 184387
2013-06-20 00:25:24 +00:00
Tim Northover
7700179b08 AArch64: remove accidental test output file.
llvm-svn: 184236
2013-06-18 21:16:53 +00:00
Quentin Colombet
337e6e6d1f During SelectionDAG building explicitly set a node to constant zero when the
value is zero.
This allows optmizations to kick in more easily.
Fix some test cases so that they remain meaningful (i.e., not completely dead
coded) when optimizations apply.

<rdar://problem/14096009> superfluous multiply by high part of zero-extended
value.

llvm-svn: 184222
2013-06-18 20:14:39 +00:00
Andrew Trick
5a345856da Reenable, improve, and add MI-Sched unit tests.
llvm-svn: 184134
2013-06-17 21:45:16 +00:00
Vincent Lejeune
e4a87c6317 R600: PV stores Reg id, not index
llvm-svn: 184117
2013-06-17 20:16:40 +00:00
Vincent Lejeune
b04cbc8058 R600: Properly set COUNT_3 bit in TEX clause initiating inst for pre EG gen.
Fixes rv7x0 bug in Heaven reported here:
https://bugs.freedesktop.org/show_bug.cgi?id=64257

llvm-svn: 184116
2013-06-17 20:16:26 +00:00
Benjamin Kramer
2934370512 Switch spill weights from a basic loop depth estimation to BlockFrequencyInfo.
The main advantages here are way better heuristics, taking into account not
just loop depth but also __builtin_expect and other static heuristics and will
eventually learn how to use profile info. Most of the work in this patch is
pushing the MachineBlockFrequencyInfo analysis into the right places.

This is good for a 5% speedup on zlib's deflate (x86_64), there were some very
unfortunate spilling decisions in its hottest loop in longest_match(). Other
benchmarks I tried were mostly neutral.

This changes register allocation in subtle ways, update the tests for it.
2012-02-20-MachineCPBug.ll was deleted as it's very fragile and the instruction
it looked for was gone already (but the FileCheck pattern picked up unrelated
stuff).

llvm-svn: 184105
2013-06-17 19:00:36 +00:00
David Blaikie
f3d2951503 Debug Info: Simplify Frame Index handling in DBG_VALUE Machine Instructions
Rather than using the full power of target-specific addressing modes in
DBG_VALUEs with Frame Indicies, simply use Frame Index + Offset. This
reduces the complexity of debug info handling down to two
representations of values (reg+offset and frame index+offset) rather
than three or four.

Ideally we could ensure that frame indicies had been eliminated by the
time we reached an assembly or dwarf generation, but I haven't spent the
time to figure out where the FIs are leaking through into that & whether
there's a good place to convert them. Some FI+offset=>reg+offset
conversion is done (see PrologEpilogInserter, for example) which is
necessary for some SelectionDAG assumptions about registers, I believe,
but it might be possible to make this a more thorough conversion &
ensure there are no remaining FIs no matter how instruction selection
is performed.

llvm-svn: 184066
2013-06-16 20:34:15 +00:00
David Blaikie
ef0e4640d7 DebugInfo: follow up to 184045 to constrain the tests further to ensure they don't contain +0 offsets
llvm-svn: 184046
2013-06-15 16:02:44 +00:00
David Blaikie
7a29358013 DebugInfo: print DBG_VALUE MachineInstrs with [] for deref and drop the offset when it's zero
llvm-svn: 184045
2013-06-15 15:52:58 +00:00
Andrew Trick
5d13fe97ed Machine Model: Add MicroOpBufferSize and resource BufferSize.
Replace the ill-defined MinLatency and ILPWindow properties with
with straightforward buffer sizes:
MCSchedMode::MicroOpBufferSize
MCProcResourceDesc::BufferSize

These can be used to more precisely model instruction execution if desired.

Disabled some misched tests temporarily. They'll be reenabled in a few commits.

llvm-svn: 184032
2013-06-15 04:49:57 +00:00
David Blaikie
d1a8512cd8 Debug Info: Don't print the display name and colon prefix for DEBUG_VALUE comments if the display name is empty
llvm-svn: 184026
2013-06-15 00:33:47 +00:00
Tom Stellard
0f71ebc5a8 R600: Add SI load support for v[24]i32 and store for v2i32
Also add a seperate vector lit test file, since r600 doesn't seem to handle
v2i32 load/store yet, but we can test both for SI.

Patch by: Aaron Watry

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Aaron Watry <awatry@gmail.com>
llvm-svn: 184021
2013-06-15 00:09:31 +00:00
Tom Stellard
428a19228a R600: Use correct encoding for Vertex Fetch instructions on Cayman
Reviewed-by: Vincent Lejeune<vljn at ovi.com>
llvm-svn: 184016
2013-06-14 22:12:30 +00:00
Tom Stellard
c25852891f R600: Use EXPORT_RAT_INST_STORE_DWORD for stores on Cayman
We were using RAT_INST_STORE_RAW, which seemed to work, but the docs
say this instruction doesn't exist for Cayman, so it's probably safer
to use a documented instruction instead.

Reviewed-by: Vincent Lejeune<vljn at ovi.com>
llvm-svn: 184015
2013-06-14 22:12:24 +00:00
Tim Northover
11fabb62e9 Mark rematerialized super/sub registers as dead.
When we're rematerializing into a not-quite-right register we already add the
real definition as an imp-def, but we should also be marking the "official"
register as dead, since nothing else is going to use it as a result of this
remat.

Not doing this can affect pressure tracking.

rdar://problem/14158833

llvm-svn: 184002
2013-06-14 20:22:21 +00:00
Stephen Lin
ccd266c666 SelectionDAG: Fix incorrect condition checks in some cases of folding FADD/FMUL combinations; also improve accuracy of comments
llvm-svn: 183993
2013-06-14 18:17:35 +00:00
Derek Schuff
4c429cad03 Make PrologEpilogInserter save/restore all callee saved registers
in functions which call __builtin_unwind_init()

__builtin_unwind_init() is an undocumented gcc intrinsic which has this effect,
and is used in libgcc_eh.

Goes part of the way toward fixing PR8541.

llvm-svn: 183984
2013-06-14 16:15:29 +00:00
Benjamin Kramer
a0c15494c5 X86: cvtpi2ps is just an SSE instruction with MMX operands. It has no AVX equivalent.
Give it the right register format so we can also emit it when AVX is enabled.

llvm-svn: 183971
2013-06-14 09:31:41 +00:00
JF Bastien
cb60eaba94 Enable FastISel on ARM for Linux and NaCl, not MCJIT
This is a resubmit of r182877, which was reverted because it broken
MCJIT tests on ARM. The patch leaves MCJIT on ARM as it was before: only
enabled for iOS. I've CC'ed people from the original review and revert.

FastISel was only enabled for iOS ARM and Thumb2, this patch enables it
for ARM (not Thumb2) on Linux and NaCl, but not MCJIT.

Thumb2 support needs a bit more work, mainly around register class
restrictions.

The patch punts to SelectionDAG when doing TLS relocation on non-Darwin
targets. I will fix this and other FastISel-to-SelectionDAG failures in
a separate patch.

The patch also forces FastISel to retain frame pointers: iOS always
keeps them for backtracking (so emitted code won't change because of
this), but Linux was getting much worse code that was incorrect when
using big frames (such as test-suite's lencod). I'll also fix this in a
later patch, it will probably require a peephole so that FastISel
doesn't rematerialize frame pointers back-to-back.

The test changes are straightforward, similar to:
  http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130513/174279.html
They also add a vararg test that got dropped in that change.

I ran all of lnt test-suite on A15 hardware with --optimize-option=-O0
and all the tests pass. All the tests also pass on x86 make check-all. I
also re-ran the check-all tests that failed on ARM, and they all seem to
pass.

llvm-svn: 183966
2013-06-14 02:49:43 +00:00
Bill Schmidt
fac3a79629 [PowerPC] Disable fast-isel for existing -O0 tests for PowerPC.
This is a preliminary patch for fast instruction selection on
PowerPC.  Code generation can differ between DAG isel and fast isel.
Existing tests that specify -O0 were written to expect DAG isel.  Make
this explicit by adding -fast-isel=false to the tests.

In some cases specifying -fast-isel=false produces different code even
when there isn't a fast instruction selector specified.  This is
because TM.Options.EnableFastISel = 1 at -O0 whether or not a FastISel
object exists.  Thus disabling fast isel can actually produce less
conservative code.  Because of this, some of the expected code
generation in the -O0 tests needs to be adjusted.

In particular, handling of function arguments is less conservative
with -fast-isel=false (see isOnlyUsedInEntryBlock() in
SelectionDAGBuilder.cpp).  This results in fewer stack accesses and,
in some cases, reduced stack size as uselessly loaded values are no
longer stored back to spill locations in the stack.

No functional change with this patch; test case adjustments only.

llvm-svn: 183939
2013-06-13 20:23:34 +00:00
Akira Hatanaka
8332c68b45 [mips] Add an IR transformation pass that optimizes calls to sqrt.
The pass emits a call to sqrt that has attribute "read-none". This call will be
converted to an ISD::FSQRT node during DAG construction, which will turn into
a mips native sqrt instruction.
 

llvm-svn: 183802
2013-06-11 22:21:44 +00:00
Tim Northover
4ba890d132 X86: Stop LEA64_32r doing unspeakable things to its arguments.
Previously LEA64_32r went through virtually the entire backend thinking it was
using 32-bit registers until its blissful illusions were cruelly snatched away
by MCInstLower and 64-bit equivalents were substituted at the last minute.

This patch makes it behave normally, and take 64-bit registers as sources all
the way through. Previous uses (for 32-bit arithmetic) are accommodated via
SUBREG_TO_REG instructions which make the types and classes agree properly.

llvm-svn: 183693
2013-06-10 20:43:49 +00:00
Justin Holewinski
fa2e2511f8 [NVPTX] Remove old CONST_NOT_GEN address space that is not being used anymore and causes constants to be emitted in the global address space
llvm-svn: 183652
2013-06-10 13:29:47 +00:00
JF Bastien
be1c9b906e Add test for ARM FastISel load/store register classes
r183624 fixed an issue that was tested indirectly. Test it directly with this new test.

llvm-svn: 183634
2013-06-10 00:35:57 +00:00
Reed Kotler
8176eeb183 Fix a regression I introduced when I expanded the complex pseudos in
the Mips16 port. A few of the psuedos could either take signed
or unsigned arguments and I did not distinguish the case and improperly
rejected some valid cases that the assembler had previously accepted
when they were pure pseudos that expanded as assembly instructions.

llvm-svn: 183633
2013-06-09 23:23:46 +00:00
Logan Chien
61f1a9f5d2 Refine the ARM EHABI test cases.
Since we have ARM unwind directive parser and assembler, we
can check the correctness in two stages:

1. From LLVM assembly (.ll) to ARM assembly (.s)
2. From ARM assembly (.s) to ELF object file (.o)

We already have several "*.s to *.o" test cases.  This CL adds
some "*.ll to *.s" test cases and removes the redundant "*.ll to *.o"
test cases.

New test cases to check "*.ll to *.s" code generator:

- ehabi.ll: Check the correctness of the generated unwind directives.
- section-name.ll: Check the section name of functions.

Removed test cases:

- ehabi-mc-cantunwind.ll
  (Covered by ehabi-cantunwind.ll, and eh-directive-cantunwind.s)
- ehabi-mc-compact-pr0.ll
  (Covered by ehabi.ll, eh-compact-pr0.s, eh-directive-save.s, and
   eh-directive-setfp.s)
- ehabi-mc-compact-pr1.ll
  (Covered by ehabi.ll, eh-compact-pr1.s, eh-directive-save.s, and
   eh-directive-setfp.s)
- ehabi-mc.ll
  (Covered by ehabi.ll, and eh-directive-integrated-test.s)
- ehabi-mc-section-group.ll
  (Covered by section-name.ll, and eh-directive-section-comdat.s)
- ehabi-mc-section.ll
  (Covered by section-name.ll, and eh-directive-section.s)
- ehabi-mc-sh_link.ll
  (Covered by eh-directive-text-section.s, and eh-directive-section.s)

llvm-svn: 183628
2013-06-09 12:36:57 +00:00
Logan Chien
fa2266ded0 Fix ARM unwind opcode assembler in several cases.
Changes to ARM unwind opcode assembler:

* Fix multiple .save or .vsave directives.  Besides, the
  order is preserved now.

* For the directives which will generate multiple opcodes,
  such as ".save {r0-r11}", the order of the unwind opcode
  is fixed now, i.e. the registers with less encoding value
  are popped first.

* Fix the $sp offset calculation.  Now, we can use the
  .setfp, .pad, .save, and .vsave directives at any order.

Changes to test cases:

* Add test cases to check the order of multiple opcodes
  for the .save directive.

* Fix the incorrect $sp offset in the test case.  The
  stack pointer offset specified in the test case was
  incorrect.  (Changed test cases: ehabi-mc-section.ll and
  ehabi-mc.ll)

* The opcode to restore $sp are slightly reordered.  The
  behavior are not changed, and the new output is same
  as the output of GNU as.  (Changed test cases:
  eh-directive-pad.s and eh-directive-setfp.s)

llvm-svn: 183627
2013-06-09 12:22:30 +00:00
Elena Demikhovsky
1c6fe6138b Removed PackedDouble domain from scalar instructions. Added more formats for the scalar stuff.
llvm-svn: 183626
2013-06-09 07:37:10 +00:00
Venkatraman Govindaraju
9767317993 [Sparc] Delete FPMover Pass and remove Fp* Pseudo-instructions from Sparc backend.
llvm-svn: 183613
2013-06-08 15:32:59 +00:00
Quentin Colombet
288faf08d2 Reapply r183552. This time, use a standard type for the option to avoid template
instantiation issue with non-standard type.

Add a backend option to warn on a given stack size limit.
Option: -mllvm -warn-stack-size=<limit>
Output (if limit is exceeded):
warning: Stack size limit exceeded (<actual size>) in <functionName>.

The longer term plan is to hook that to a clang warning.
PR:4072
<rdar://problem/13987214>.

llvm-svn: 183595
2013-06-08 00:07:54 +00:00
Vincent Lejeune
2f252fdf26 R600: Anti dep better handled in tex clause
llvm-svn: 183592
2013-06-07 23:30:26 +00:00
Jakob Stoklund Olesen
3a549110cd Add missing zextloadi1 to i64 patterns. PR16721.
llvm-svn: 183587
2013-06-07 22:55:05 +00:00
Hal Finkel
9c0ef0659d Disallow i64 div/rem in PPC32 counter loops
On PPC32, [su]div,rem on i64 types are transformed into runtime library
function calls. As a result, they are not allowed in counter-based loops (the
counter-loops verification pass caught this error; this change fixes PR16169).

llvm-svn: 183581
2013-06-07 22:16:19 +00:00
Quentin Colombet
8f78b800ab Revert commits related to stack warning.
llvm-svn: 183579
2013-06-07 22:14:50 +00:00
Quentin Colombet
4a1b82f036 Explicit triple in warn stack size test cases to not depend on OS.
llvm-svn: 183574
2013-06-07 21:09:42 +00:00
Tom Stellard
7c091ffbf7 R600: Fix calculation of stack offset in AMDGPUFrameLowering
We weren't computing structure size correctly and we were relying on
the original alloca instruction to compute the offset, which isn't
always reliable.

Reviewed-by: Vincent Lejeune <vljn@ovi.com>
llvm-svn: 183568
2013-06-07 20:52:05 +00:00
Tom Stellard
f4646ab025 R600: Fix the fetch limits for R600 generation GPUs
Reviewed-by: Vincent Lejeune <vljn@ovi.com>

https://bugs.freedesktop.org/show_bug.cgi?id=64257

llvm-svn: 183560
2013-06-07 20:28:55 +00:00
Quentin Colombet
474d9dcceb Add a backend option to warn on a given stack size limit.
Option: -mllvm -warn-stack-size=<limit>
Output (if limit is exceeded):
warning: Stack size limit exceeded (<actual size>) in <functionName>.

The longer term plan is to hook that to a clang warning.
PR:4072
<rdar://problem/13987214>

llvm-svn: 183552
2013-06-07 20:18:12 +00:00
JF Bastien
c950ffbe08 ARM FastISel integer sext/zext improvements
My recent ARM FastISel patch exposed this bug:
  http://llvm.org/bugs/show_bug.cgi?id=16178
The root cause is that it can't select integer sext/zext pre-ARMv6 and
asserts out.

The current integer sext/zext code doesn't handle other cases gracefully
either, so this patch makes it handle all sext and zext from i1/i8/i16
to i8/i16/i32, with and without ARMv6, both in Thumb and ARM mode. This
should fix the bug as well as make FastISel faster because it bails to
SelectionDAG less often. See fastisel-ext.patch for this.

fastisel-ext-tests.patch changes current tests to always use reg-imm AND
for 8-bit zext instead of UXTB. This simplifies code since it is
supported on ARMv4t and later, and at least on A15 both should perform
exactly the same (both have exec 1 uop 1, type I).

2013-05-31-char-shift-crash.ll is a bitcode version of the above bug
16178 repro.

fast-isel-ext.ll tests all sext/zext combinations that ARM FastISel
should now handle.

Note that my ARM FastISel enabling patch was reverted due to a separate
failure when dealing with MCJIT, I'll fix this second failure and then
turn FastISel on again for non-iOS ARM targets.

I've tested "make check-all" on my x86 box, and "lnt test-suite" on A15
hardware.

llvm-svn: 183551
2013-06-07 20:10:37 +00:00
Quentin Colombet
a8970e620f Teach AsmPrinter how to print odd constants.
Fix an assertion when the compiler encounters big constants whose bit width is
not a multiple of 64-bits.
Although clang would never generate something like this, the backend should be
able to handle any legal IR.

<rdar://problem/13363576>

llvm-svn: 183544
2013-06-07 18:36:03 +00:00
Roman Divacky
8439b144e6 Fix a typo in asm string of BP* family of instructions. With this fix
I am able to compile/assemble/link/run /bin/echo from FreeBSD.

llvm-svn: 183537
2013-06-07 17:46:57 +00:00
Rafael Espindola
7b8382bcbc Support OpenBSD's native frame protection conventions.
OpenBSD's stack smashing protection differs slightly from other
platforms:

  1. The smash handler function is "__stack_smash_handler(const char
     *funcname)" instead of "__stack_chk_fail(void)".

  2. There's a hidden "long __guard_local" object that gets linked
     into each executable and DSO.

Patch by Matthew Dempsky.

llvm-svn: 183533
2013-06-07 16:35:57 +00:00
Venkatraman Govindaraju
867986b1ff [Sparc]: Use cmp instruction instead of subcc to compare integers.
llvm-svn: 183463
2013-06-07 00:03:36 +00:00
Vincent Lejeune
dd2a468cbd R600: Add a pass that merge Vector Register
Previously commited @183279 but tests were failing, reverted @183286
It was broken because @183336 was missing, now it's there.

llvm-svn: 183343
2013-06-05 21:38:04 +00:00
Vincent Lejeune
cc7d08e974 R600: Schedule copy from phys register at beginning of block
It allows regalloc pass to remove them by trivially assigning associated reg

llvm-svn: 183336
2013-06-05 20:27:35 +00:00
Akira Hatanaka
b5546583ad [mips] brcond + setgt/setugt instruction selection patterns.
llvm-svn: 183334
2013-06-05 19:49:55 +00:00
Michael Liao
d464e3d65b [PATCH] Fix VGATHER* operand constraints
Add earlyclobber constaints to prevent input register being allocated as
the output register because, according to Intel spec [1], "If any pair
of the index, mask, or destination registers are the same, this
instruction results a UD fault."

---
[1] http://software.intel.com/sites/default/files/319433-014.pdf

llvm-svn: 183327
2013-06-05 18:12:26 +00:00
Tom Stellard
ecf6bd2eaa R600: Make sure to schedule AR register uses and defs in the same clause
Reviewed-by: vljn at ovi.com
llvm-svn: 183294
2013-06-05 03:43:06 +00:00
Rafael Espindola
f5e919b2e6 Revert "R600: Add a pass that merge Vector Register"
This reverts commit r183279. CodeGen/R600/texture-input-merge.ll was failing.

llvm-svn: 183286
2013-06-05 01:48:30 +00:00
Vincent Lejeune
57d56af481 R600: Add a pass that merge Vector Register
llvm-svn: 183279
2013-06-04 23:17:26 +00:00
Vincent Lejeune
7c89765008 R600: Const/Neg/Abs can be folded to dot4
llvm-svn: 183278
2013-06-04 23:17:15 +00:00
Evan Cheng
1c010771f4 Cortex-R5 can issue Thumb2 integer division instructions.
llvm-svn: 183275
2013-06-04 22:52:09 +00:00
David Majnemer
d0dc0d58f6 ARM: Fix crash in ARM backend inside of ARMConstantIslandPass
The ARM backend did not expect LDRBi12 to hold a constant pool operand.
Allow for LLVM to deal with the instruction similar to how it deals with
LDRi12.

This fixes PR16215.

llvm-svn: 183238
2013-06-04 17:46:15 +00:00
Vincent Lejeune
8d2ef79cb9 R600: Swizzle texture/export instructions
llvm-svn: 183229
2013-06-04 15:04:53 +00:00
Vincent Lejeune
e7cc832b43 R600: Add a test for r183108
llvm-svn: 183228
2013-06-04 15:03:35 +00:00
Tom Stellard
0c2bbb2a1f R600/SI: Add support for work item and work group intrinsics
llvm-svn: 183138
2013-06-03 17:40:18 +00:00
Tom Stellard
0faf53682e R600/SI: Add a calling convention for compute shaders
llvm-svn: 183137
2013-06-03 17:40:11 +00:00
Tom Stellard
47a52f3e69 R600/SI: Custom lower i64 sign_extend
llvm-svn: 183136
2013-06-03 17:40:03 +00:00
Tom Stellard
7e44e13b15 R600/SI: Add support for global loads
llvm-svn: 183131
2013-06-03 17:39:43 +00:00
Vincent Lejeune
55871f8f8a R600: use capital letter for PV channel
llvm-svn: 183107
2013-06-03 15:44:35 +00:00
Venkatraman Govindaraju
2d5d39937e Sparc: Add support for indirect branch and blockaddress in Sparc backend.
llvm-svn: 183094
2013-06-03 05:58:33 +00:00
Venkatraman Govindaraju
b47bd839e0 Sparc: When storing 0, use %g0 directly in the store instruction instead of
using two instructions (sethi and store).

llvm-svn: 183090
2013-06-03 00:21:54 +00:00
Venkatraman Govindaraju
0514a4c845 Sparc: Combine add/or/sethi instruction with restore if possible.
llvm-svn: 183088
2013-06-02 21:48:17 +00:00
Venkatraman Govindaraju
acb910b7ae Sparc: Perform leaf procedure optimization by default
llvm-svn: 183083
2013-06-02 02:24:27 +00:00
Venkatraman Govindaraju
2425aef2ad Sparc: Mark functions calling llvm.vastart and llvm.returnaddress intrinsics as non-leaf functions.
llvm-svn: 183079
2013-06-01 20:42:48 +00:00
Tim Northover
e84e621d63 Revert r183069: "TMP: LEA64_32r fixing"
Very sorry, it was committed from the wrong branch by mistake.

llvm-svn: 183070
2013-06-01 10:23:46 +00:00
Tim Northover
93287c3991 TMP: LEA64_32r fixing
llvm-svn: 183069
2013-06-01 10:21:54 +00:00
Tim Northover
8efc0e4868 X86: change MOV64ri64i32 into MOV32ri64
The MOV64ri64i32 instruction required hacky MCInst lowering because it
was allocated as setting a GR64, but the eventual instruction ("movl")
only set a GR32. This converts it into a so-called "MOV32ri64" which
still accepts a (appropriate) 64-bit immediate but defines a GR32.
This is then converted to the full GR64 by a SUBREG_TO_REG operation,
thus keeping everyone happy.

This fixes a typo in the opcode field of the original patch, which
should make the legact JIT work again (& adds test for that problem).

llvm-svn: 183068
2013-06-01 09:55:14 +00:00
Venkatraman Govindaraju
1eaf496598 [Sparc] Generate correct code for leaf functions with stack objects
llvm-svn: 183067
2013-06-01 04:51:18 +00:00
Eric Christopher
e4ab862999 Temporarily Revert "X86: change MOV64ri64i32 into MOV32ri64" as it
seems to have caused PR16192 and other JIT related failures.

llvm-svn: 183059
2013-05-31 23:30:45 +00:00
Quentin Colombet
c3a4f33cc1 Modify how the formulae are rated in Loop Strength Reduce.
Namely, check if the target allows to fold more that one register in the
addressing mode and if yes, adjust the cost accordingly.

Prior to this commit, reg1 + scale * reg2 accesses were artificially preferred
to reg1 + reg2 accesses. Indeed, the cost model wrongly assumed that reg1 + reg2
needs a temporary register for the computation, whereas it was correctly
estimated for reg1 + scale * reg2.

<rdar://problem/13973908>

llvm-svn: 183021
2013-05-31 17:20:29 +00:00
Richard Sandiford
77f91408dd [SystemZ] Don't use LOAD and STORE REVERSED for volatile accesses
Unlike most -- hopefully "all other", but I'm still checking -- memory
instructions we support, LOAD REVERSED and STORE REVERSED may access
the memory location several times.  This means that they are not suitable
for volatile loads and stores.

This patch is a prerequisite for better atomic load and store support.
The same principle applies there: almost all memory instructions we
support are inherently atomic ("block concurrent"), but LOAD REVERSED
and STORE REVERSED are exceptions.

Other instructions continue to allow volatile operands.  I will add
positive "allows volatile" tests at the same time as the "allows atomic
load or store" tests.

llvm-svn: 183002
2013-05-31 13:25:22 +00:00
Justin Holewinski
d925e36ab2 [NVPTX] Re-enable support for virtual registers in the final output
Now that 3.3 is branched, we are re-enabling virtual registers to help
iron out bugs before the next release. Some of the post-RA passes do
not play well with virtual registers, so we disable them for now. The
needed functionality of the PrologEpilogInserter pass is copied to a
new backend-specific NVPTXPrologEpilog pass.

The test for this commit is not breaking the existing tests.

llvm-svn: 182998
2013-05-31 12:14:49 +00:00
Tim Northover
8940245595 X86: change MOV64ri64i32 into MOV32ri64
The MOV64ri64i32 instruction required hacky MCInst lowering because it was
allocated as setting a GR64, but the eventual instruction ("movl") only set a
GR32. This converts it into a so-called "MOV32ri64" which still accepts a
(appropriate) 64-bit immediate but defines a GR32. This is then converted to
the full GR64 by a SUBREG_TO_REG operation, thus keeping everyone happy.

llvm-svn: 182991
2013-05-31 09:57:13 +00:00
Akira Hatanaka
13f3fde46f [mips] Big-endian code generation for atomic instructions.
Patch by Jyun-Yan You.

llvm-svn: 182984
2013-05-31 03:25:44 +00:00
Rafael Espindola
d23482285b Revert r182937 and r182877.
r182877 broke MCJIT tests on ARM and r182937 was working around another failure
by r182877.

This should make the ARM bots green.

llvm-svn: 182960
2013-05-30 20:37:52 +00:00
Benjamin Kramer
f41318934e Force a triple so we don't get bitten by windows' different regalloc.
llvm-svn: 182935
2013-05-30 15:39:35 +00:00
Benjamin Kramer
8b559051e4 Force fragile test to the atom scheduler model.
The pattern the test originally checked for doesn't occur on other -mcpu
settings. On atom it's still there though slightly differently scheduled.

llvm-svn: 182933
2013-05-30 15:22:28 +00:00
Tim Northover
2b261b4ac3 X86: allow registers 8-15 in test
This test was failing on some hosts when an unexpected register was used for a
variable. This just extends the regexp to allow the new x86-64 registers.

llvm-svn: 182929
2013-05-30 13:56:32 +00:00
Tim Northover
aa5932cde5 X86: use sub-register sequences for MOV*r0 operations
Instead of having a bunch of separate MOV8r0, MOV16r0, ... pseudo-instructions,
it's better to use a single MOV32r0 (which will expand to "xorl %reg, %reg")
and obtain other sizes with EXTRACT_SUBREG and SUBREG_TO_REG. The encoding is
smaller and partial register updates can sometimes be avoided.

Until recently, this sequence was a barrier to rematerialization though. That
should now be fixed so it's an appropriate time to make the change.

llvm-svn: 182928
2013-05-30 13:19:42 +00:00
Justin Holewinski
099d52887f [NVPTX] Fix case where a sext load of an i1 type may produce an
ld.u1 instead of an ld.u8.

llvm-svn: 182924
2013-05-30 12:22:39 +00:00
Richard Sandiford
b7ab6fd782 [SystemZ] Enable unaligned accesses
The code to distinguish between unaligned and aligned addresses was
already there, so this is mostly just a switch-on-and-test process.

llvm-svn: 182920
2013-05-30 09:45:42 +00:00
Rafael Espindola
5b34d5a3c7 Change how we iterate over relocations on ELF.
For COFF and MachO, sections semantically have relocations that apply to them.
That is not the case on ELF.

In relocatable objects (.o), a section with relocations in ELF has offsets to
another section where the relocations should be applied.

In dynamic objects and executables, relocations don't have an offset, they have
a virtual address. The section sh_info may or may not point to another section,
but that is not actually used for resolving the relocations.

This patch exposes that in the ObjectFile API. It has the following advantages:

* Most (all?) clients can handle this more efficiently. They will normally walk
all relocations, so doing an effort to iterate in a particular order doesn't
save time.

* llvm-readobj now prints relocations in the same way the native readelf does.

* probably most important, relocations that don't point to any section are now
visible. This is the case of relocations in the rela.dyn section. See the
updated relocation-executable.test for example.

llvm-svn: 182908
2013-05-30 03:05:14 +00:00
Bill Wendling
cab3fa1f1c This testcase tests command line attributes which we don't yet support.
In fact, we're probably going to support these flags in completely different
ways. So this test is no longer valid.

llvm-svn: 182899
2013-05-30 00:32:04 +00:00
Andrew Trick
aec414c298 Order CALLSEQ_START and CALLSEQ_END nodes.
Fixes PR16146: gdb.base__call-ar-st.exp fails after
pre-RA-sched=source fixes.

Patch by Xiaoyi Guo!

This also fixes an unsupported dbg.value test case. Codegen was
previously incorrect but the test was passing by luck.

llvm-svn: 182885
2013-05-29 22:03:55 +00:00
JF Bastien
235d8c9117 Enable FastISel on ARM for Linux and NaCl
FastISel was only enabled for iOS ARM and Thumb2, this patch enables it
for ARM (not Thumb2) on Linux and NaCl.

Thumb2 support needs a bit more work, mainly around register class
restrictions.

The patch punts to SelectionDAG when doing TLS relocation on non-Darwin
targets. I will fix this and other FastISel-to-SelectionDAG failures in
a separate patch.

The patch also forces FastISel to retain frame pointers: iOS always
keeps them for backtracking (so emitted code won't change because of
this), but Linux was getting much worse code that was incorrect when
using big frames (such as test-suite's lencod). I'll also fix this in a
later patch, it will probably require a peephole so that FastISel
doesn't rematerialize frame pointers back-to-back.

The test changes are straightforward, similar to:
  http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130513/174279.html
They also add a vararg test that got dropped in that change.

I ran all of test-suite on A15 hardware with --optimize-option=-O0 and
all the tests pass.

llvm-svn: 182877
2013-05-29 20:38:10 +00:00
Tim Northover
db2d7a34b2 Teach ReMaterialization to be more cunning about subregisters
This allows rematerialization during register coalescing to handle
more cases involving operations like SUBREG_TO_REG which might need to
be rematerialized using sub-register indices.

For example, code like:
    v1(GPR64):sub_32 = MOVZ something
    v2(GPR64) = COPY v1(GPR64)
should be convertable to:
    v2(GPR64):sub_32 = MOVZ something

but previously we just gave up in places like this

llvm-svn: 182872
2013-05-29 19:32:06 +00:00
Richard Sandiford
b70371b744 [SystemZ] Two tests missing from previous commit
llvm-svn: 182847
2013-05-29 11:59:26 +00:00
Richard Sandiford
b62e20c071 [SystemZ] Immediate compare-and-branch support
This patch adds support for the CIJ and CGIJ instructions.

llvm-svn: 182846
2013-05-29 11:58:52 +00:00
Venkatraman Govindaraju
cb40ce1f29 [Sparc] Add support for leaf functions in sparc backend.
llvm-svn: 182822
2013-05-29 04:46:31 +00:00
Richard Sandiford
4b6cfd7cec [SystemZ] Register compare-and-branch support
This patch adds support for the CRJ and CGRJ instructions.  Support for
the immediate forms will be a separate patch.

The architecture has a large number of comparison instructions.  I think
it's generally better to concentrate on using the "best" comparison
instruction first and foremost, then only use something like CRJ if
CR really was the natual choice of comparison instruction.  The patch
therefore opportunistically converts separate CR and BRC instructions
into a single CRJ while emitting instructions in ISelLowering.

llvm-svn: 182764
2013-05-28 10:41:11 +00:00
Preston Gurd
8be7e42cc2 Convert sqrt functions into sqrt instructions when -ffast-math is in effect.
When -ffast-math is in effect (on Linux, at least), clang defines
__FINITE_MATH_ONLY__ > 0 when including <math.h>. This causes the
preprocessor to include <bits/math-finite.h>, which renames the sqrt functions.
For instance, "sqrt" is renamed as "__sqrt_finite". 

This patch adds the 3 new names in such a way that they will be treated
as equivalent to their respective original names.

llvm-svn: 182739
2013-05-27 15:44:35 +00:00
Rafael Espindola
bf27725489 Add a cpu to try to bring back the atom bots.
llvm-svn: 182734
2013-05-27 13:22:52 +00:00
Hal Finkel
1f5ee2fefe Prefer to duplicate PPC Altivec loads when expanding unaligned loads
When expanding unaligned Altivec loads, we use the decremented offset trick to
prevent page faults. Unfortunately, if we have a sequence of consecutive
unaligned loads, this leads to suboptimal code generation because the 'extra'
load from the first unaligned load can be combined with the base load from the
second (but only if the decremented offset trick is not used for the first).
Search up and down the chain, through loads and token factors, looking for
consecutive loads, and if one is found, don't use the offset reduction trick.
These duplicate loads are later combined to yield the desired sequence (in the
future, we might want a more-powerful chain search, but that will require some
changes to allow the combiner routines to access the AA object).

This should complete the initial implementation of the optimized unaligned
Altivec load expansion. There is some refactoring that should be done, but
that will happen when the unaligned store expansion is added.

llvm-svn: 182719
2013-05-26 18:08:30 +00:00
Andrew Trick
c92ce8a4f2 Fix PR16143: Insert DEBUG_VALUE before terminator.
llvm-svn: 182717
2013-05-26 08:58:50 +00:00
Hal Finkel
f5d061cce9 PPC: Combine duplicate (offset) lvsl Altivec intrinsics
The lvsl permutation control instruction is a function only of the alignment of
the pointer operand (relative to the 16-byte natural alignment of Altivec
vectors). As a result, multiple lvsl intrinsics where the operands differ by a
multiple of 16 can be combined.

llvm-svn: 182708
2013-05-25 04:05:05 +00:00
Andrew Trick
53ca6c9254 Track IR ordering of SelectionDAG nodes 4/4.
Unit test cases for -pre-RA-sched=source.

llvm-svn: 182706
2013-05-25 03:26:51 +00:00
Andrew Trick
34c31df32a Track IR ordering of SelectionDAG nodes 3/4.
Remove the old IR ordering mechanism and switch to new one.  Fix unit
test failures.

llvm-svn: 182704
2013-05-25 03:08:10 +00:00
Hal Finkel
b8fe2ab5cb PPC: Initial support for permutation-based unaligned Altivec loads
Altivec only directly supports aligned loads, but the loads have a strange
property: If given an unaligned address, they truncate the address to the next
lower aligned address, and load from there.  This property, along with an extra
load and some special-purpose permutation-control instructions that generate
the appropriate permutations from the original unaligned address, allow
efficient lowering of aligned loads. This code uses the trick explained in the
Apple Velocity Engine optimization overview document to prevent the needed
extra load from possibly causing a page fault if the original address happens
to be aligned.

As noted in the FIXMEs, there are several additional optimizations that can be
performed to reduce the cost of these loads even more. These will be
implemented in future commits.

llvm-svn: 182691
2013-05-24 23:00:14 +00:00
Diego Novillo
d1f091f169 Add a new function attribute 'cold' to functions.
Other than recognizing the attribute, the patch does little else.
It changes the branch probability analyzer so that edges into
blocks postdominated by a cold function are given low weight.

Added analysis and code generation tests.  Added documentation for the
new attribute.

llvm-svn: 182638
2013-05-24 12:26:52 +00:00
Tim Northover
9b6ef4d68e ARM: implement @llvm.readcyclecounter intrinsic
This implements the @llvm.readcyclecounter intrinsic as the specific
MRC instruction specified in the ARM manuals for CPUs with the Power
Management extensions.

Older CPUs had slightly different methods which may also have to be
implemented eventually, but this should cover all v7 cases.

rdar://problem/13939186

llvm-svn: 182603
2013-05-23 19:11:20 +00:00
Tom Stellard
dee18e3abb R600: Fix R600ControlFlowFinalizer not considering VTX_READ 128 bit dst reg
Patch by: Vincent Lejeune

https://bugs.freedesktop.org/show_bug.cgi?id=64877

NOTE: This is a candidate for the 3.3 branch.
llvm-svn: 182600
2013-05-23 18:26:42 +00:00
Jakob Stoklund Olesen
b4fe10613b Fix PR16110: Handle DBG_VALUE in ConnectedVNInfoEqClasses::Distribute().
Now that the LiveDebugVariables pass is running *after* register
coalescing, the ConnectedVNInfoEqClasses class needs to deal with
DBG_VALUE instructions.

This only comes up when rematerialization during coalescing causes the
remaining live range of a virtual register to separate into two
connected components.

llvm-svn: 182592
2013-05-23 17:02:23 +00:00
Nick Lewycky
f93dded11b Add missing test from r175092.
llvm-svn: 182564
2013-05-23 07:46:13 +00:00
Nadav Rotem
bfc39207bf X86: Fix a bug in EltsFromConsecutiveLoads. We can't generate new loads without chains.
llvm-svn: 182507
2013-05-22 19:28:41 +00:00
Benjamin Kramer
dced131e7e X86: When expanding PCMPGTQ to PCMPGTD we always want to compare the lower halves as unsigned.
Take #2 on fixing PR15977.

llvm-svn: 182486
2013-05-22 17:01:12 +00:00
David Majnemer
0c608d85e0 X86: Remove test instructions proceeding shift by immediate instructions
Allow LLVM to take advantage of shift instructions that set the ZF flag,
making instructions that test the destination superfluous.

llvm-svn: 182454
2013-05-22 08:13:02 +00:00
Akira Hatanaka
4da68c1676 [mips] Rename option to make it compatible with gcc.
llvm-svn: 182397
2013-05-21 17:17:59 +00:00
Akira Hatanaka
6123e22ce0 [mips] Add instruction selection patterns for blez and bgez.
llvm-svn: 182396
2013-05-21 17:13:47 +00:00
Justin Holewinski
2a53cbfbe1 [NVPTX] Add @llvm.nvvm.sqrt.f() intrinsic
llvm-svn: 182394
2013-05-21 16:51:30 +00:00
Justin Holewinski
e8d1165196 Drop @llvm.annotation and @llvm.ptr.annotation intrinsics during codegen.
The intrinsic calls are dropped, but the annotated value is propagated.

Fixes PR 15253

Original patch by Zeng Bin!

llvm-svn: 182387
2013-05-21 14:37:16 +00:00
Benjamin Kramer
6b339bee4e X86: When emulating unsigned PCMPGTQ with PCMPGTD, fix the sign bit for the smaller type.
Otherwise we'll get a mix of signed and unsigned compares.
Fixes PR15977.

llvm-svn: 182364
2013-05-21 09:58:54 +00:00
Richard Sandiford
10059d8172 [SystemZ] Tighten branch tests
After r182274, the branches in these tests must always be short.

llvm-svn: 182358
2013-05-21 08:53:17 +00:00
Benjamin Kramer
5872fe13c9 DAGCombine: Avoid an edge case where it tried to create an i0 type for (x & 0) == 0.
Fixes PR16083.

llvm-svn: 182357
2013-05-21 08:51:09 +00:00
Reed Kotler
81c5979b12 Add checks that the proper predeined stubs are being called to the test case.
These were accidentally omitted.

llvm-svn: 182347
2013-05-21 01:27:36 +00:00
Reed Kotler
2d5f41cb35 Add some additional functions to the list of helper functions for
pic calls. These need to be there so we don't try and use helper
functions when we call those.

As part of this, make sure that we properly exclude helper functions in pic
mode when indirect calls are involved.

llvm-svn: 182343
2013-05-21 00:50:30 +00:00
Akira Hatanaka
05711091c4 [mips] Add (setne $lhs, 0) instruction selection pattern.
llvm-svn: 182307
2013-05-20 18:18:07 +00:00
Akira Hatanaka
96de87d87c [mips] Trap on integer division by zero.
By default, a teq instruction is inserted after integer divide. No divide-by-zero
checks are performed if option "-mnocheck-zero-division" is used.

llvm-svn: 182306
2013-05-20 18:07:43 +00:00
Justin Holewinski
2d2a08ee5e [NVPTX] Fix mis-use of CurrentFnSym in NVPTXAsmPrinter. This was causing a symbol name error in the output PTX.
llvm-svn: 182298
2013-05-20 16:42:18 +00:00
Tom Stellard
6cdacd1792 R600: Fix rotr.ll on non-asserts builds
The -debug-only option is only available on asserts builds.

llvm-svn: 182291
2013-05-20 15:28:48 +00:00
Tom Stellard
d72698331e R600/SI: Add pattern for rotr
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 182286
2013-05-20 15:02:24 +00:00
Tom Stellard
5ca265d214 R600: Swap the legality of rotl and rotr
The hardware supports rotr and not rotl.

llvm-svn: 182285
2013-05-20 15:02:19 +00:00
Tom Stellard
1609774b15 R600/SI: Add patterns for 64-bit shift operations
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 182284
2013-05-20 15:02:12 +00:00
Richard Sandiford
cc815ef1d8 [SystemZ] Add long branch pass
Before this change, the SystemZ backend would use BRCL for all branches
and only consider shortening them to BRC when generating an object file.
E.g. a branch on equal would use the JGE alias of BRCL in assembly output,
but might be shortened to the JE alias of BRC in ELF output.  This was
a useful first step, but it had two problems:

(1) The z assembler isn't traditionally supposed to perform branch shortening
    or branch relaxation.  We followed this rule by not relaxing branches
    in assembler input, but that meant that generating assembly code and
    then assembling it would not produce the same result as going directly
    to object code; the former would give long branches everywhere, whereas
    the latter would use short branches where possible.

(2) Other useful branches, like COMPARE AND BRANCH, do not have long forms.
    We would need to do something else before supporting them.

    (Although COMPARE AND BRANCH does not change the condition codes,
    the plan is to model COMPARE AND BRANCH as a CC-clobbering instruction
    during codegen, so that we can safely lower it to a separate compare
    and long branch where necessary.  This is not a valid transformation
    for the assembler proper to make.)

This patch therefore moves branch relaxation to a pre-emit pass.
For now, calls are still shortened from BRASL to BRAS by the assembler,
although this too is not really the traditional behaviour.

The first test takes about 1.5s to run, and there are likely to be
more tests in this vein once further branch types are added.  The feeling
on IRC was that 1.5s is a bit much for a single test, so I've restricted
it to SystemZ hosts for now.

The patch exposes (and fixes) some typos in the main CodeGen/SystemZ tests.
A later patch will remove the {{g}}s from that directory.

llvm-svn: 182274
2013-05-20 14:23:08 +00:00
Justin Holewinski
d5636664a4 [NVPTX] Add GenericToNVVM IR converter to better handle idiomatic LLVM IR inputs
This converter currently only handles global variables in address space 0. For
these variables, they are promoted to address space 1 (global memory), and all
uses are updated to point to the result of a cvta.global instruction on the new
variable.

The motivation for this is address space 0 global variables are illegal since we
cannot declare variables in the generic address space.  Instead, we place the
variables in address space 1 and explicitly convert the pointer to address
space 0. This is primarily intended to help new users who expect to be able to
place global variables in the default address space.

llvm-svn: 182254
2013-05-20 12:13:32 +00:00
Justin Holewinski
fda22b94b1 [NVPTX] Fix i1 kernel parameters and global variables. ABI rules say we need to use .u8 for i1 parameters for kernels.
llvm-svn: 182253
2013-05-20 12:13:28 +00:00
Stepan Dyatkovskiy
adb91e7ed9 PR15868 fix.
Introduction:
In case when stack alignment is 8 and GPRs parameter part size is not N*8:
we add padding to GPRs part, so part's last byte must be recovered at
address K*8-1.
We need to do it, since remained (stack) part of parameter starts from
address K*8, and we need to "attach" "GPRs head" without gaps to it:

Stack:
|---- 8 bytes block ----| |---- 8 bytes block ----| |---- 8 bytes...
[ [padding] [GPRs head] ] [ ------ Tail passed via stack  ------ ...

FIX:
Note, once we added padding we need to correct *all* Arg offsets that are going
after padded one. That's why we need this fix: Arg offsets were never corrected
before this patch. See new test-cases included in patch.

We also don't need to insert padding for byval parameters that are stored in GPRs
only. We need pad only last byval parameter and only in case it outsides GPRs
and stack alignment = 8.
Though, stack area, allocated for recovered byval params, must satisfy
"Size mod 8 = 0" restriction.

This patch reduces stack usage for some cases:
We can reduce ArgRegsSaveArea since inner N*4 bytes sized byval params my be
"packed" with alignment 4 in some cases.

llvm-svn: 182237
2013-05-20 08:01:34 +00:00
Jakob Stoklund Olesen
dad0022424 Also expand 64-bit bitcasts.
llvm-svn: 182229
2013-05-20 01:01:43 +00:00
Jakob Stoklund Olesen
e033165fd4 Implement spill and fill of I64Regs.
llvm-svn: 182228
2013-05-20 00:53:25 +00:00
Jakob Stoklund Olesen
f777e6d131 Mark i64 SETCC as expand so it is turned into a SELECT_CC.
llvm-svn: 182227
2013-05-20 00:28:36 +00:00
Jakob Stoklund Olesen
50d419ac93 Don't use %g0 to materialize 0 directly.
The wired physreg doesn't work on tied operands like on MOVXCC.

Add a README note to fix this later.

llvm-svn: 182225
2013-05-19 21:47:13 +00:00
Jakob Stoklund Olesen
f4ec84c2d4 Select i64 values with %icc conditions.
llvm-svn: 182224
2013-05-19 20:38:21 +00:00
Jakob Stoklund Olesen
1948cf9ca7 Add floating point selects on %xcc predicates.
llvm-svn: 182222
2013-05-19 20:33:11 +00:00
Jakob Stoklund Olesen
c53b3587a3 Implement SPselectfcc for i64 operands.
Also clean up the arguments to all the MOVCC instructions so the
operands always are (true-val, false-val, cond-code).

llvm-svn: 182221
2013-05-19 20:20:54 +00:00
Venkatraman Govindaraju
d432ed013f [Sparc] Rearrange integer registers' allocation order so that register allocator will use I and G registers before using L and O registers.
Also, enable registers %g2-%g4 to be used in application and %g5 in 64 bit mode.

llvm-svn: 182219
2013-05-19 20:07:20 +00:00
Jakob Stoklund Olesen
702a7c68c9 Handle i64 FrameIndex nodes in SPARC v9 mode.
llvm-svn: 182216
2013-05-19 19:14:24 +00:00
Hal Finkel
d4eb9291fa Check InlineAsm clobbers in PPCCTRLoops
We don't need to reject all inline asm as using the counter register (most does
not). Only those that explicitly clobber the counter register need to prevent
the transformation.

llvm-svn: 182191
2013-05-18 09:20:39 +00:00
David Majnemer
a21386b571 X86: Bad peephole interaction between adc, MOV32r0
The peephole tries to reorder MOV32r0 instructions such that they are
before the instruction that modifies EFLAGS.

The problem is that the peephole does not consider the case where the
instruction that modifies EFLAGS also depends on the previous state of
EFLAGS.

Instead, walk backwards until we find an instruction that has a def for
EFLAGS but does not have a use.
If we find such an instruction, insert the MOV32r0 before it.
If it cannot find such an instruction, skip the optimization.

llvm-svn: 182184
2013-05-18 01:02:03 +00:00
JF Bastien
cbcaf8db77 Support unaligned load/store on more ARM targets
This patch matches GCC behavior: the code used to only allow unaligned
load/store on ARM for v6+ Darwin, it will now allow unaligned load/store
for v6+ Darwin as well as for v7+ on Linux and NaCl.

The distinction is made because v6 doesn't guarantee support (but LLVM
assumes that Apple controls hardware+kernel and therefore have
conformant v6 CPUs), whereas v7 does provide this guarantee (and
Linux/NaCl behave sanely).

The patch keeps the -arm-strict-align command line option, and adds
-arm-no-strict-align. They behave similarly to GCC's -mstrict-align and
-mnostrict-align.

I originally encountered this discrepancy in FastIsel tests which expect
unaligned load/store generation. Overall this should slightly improve
performance in most cases because of reduced I$ pressure.

llvm-svn: 182175
2013-05-17 23:49:01 +00:00
Vincent Lejeune
c8aad4509a R600: Lower int_load_input to copyFromReg instead of Register node
It solves a bug uncovered by dot4 patch where the register class of
int_load_input use was ignored.

llvm-svn: 182130
2013-05-17 16:51:06 +00:00
Vincent Lejeune
5a2e018ab6 R600: Use bottom up scheduling algorithm
llvm-svn: 182129
2013-05-17 16:50:56 +00:00
Vincent Lejeune
2bf65b1826 R600: Use depth first scheduling algorithm
It should increase PV substitution opportunities and lower gpr
usage (pending computations path are "flushed" sooner)

llvm-svn: 182128
2013-05-17 16:50:44 +00:00
Vincent Lejeune
152473c61c R600: Relax some vector constraints on Dot4.
Dot4 now uses 8 scalar operands instead of 2 vectors one which allows register
coalescer to remove some unneeded COPY.
This patch also defines some structures/functions that can be used to handle
every vector instructions (CUBE, Cayman special instructions...) in a similar
fashion.

llvm-svn: 182126
2013-05-17 16:50:32 +00:00
Vincent Lejeune
0c663b698a R600: Improve texture handling
llvm-svn: 182125
2013-05-17 16:50:20 +00:00