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1198 Commits

Author SHA1 Message Date
Devang Patel
a5cda569d3 Remove OptimizeForSize global. Use function attribute optsize. 
llvm-svn: 56937
 2008-10-01 23:18:38 +00:00
Dan Gohman
be88cf29b6 Split this test and move it into target-specific directories. 
This fixes failures on configurations that don't have one or the
other targets enabled.

llvm-svn: 56926
 2008-10-01 19:46:30 +00:00
Dan Gohman
5508abb3bf nounwind-ify this test. 
llvm-svn: 56918
 2008-10-01 15:07:14 +00:00
Bill Wendling
c807050f44 Moved this option to the front-end. 
llvm-svn: 56901
 2008-10-01 01:02:18 +00:00
Dan Gohman
d456cc01eb Use explicit target-triples to unbreak this test on non-darwin systems. 
llvm-svn: 56896
 2008-10-01 00:25:38 +00:00
Bill Wendling
618d422cdd Just don't transform this memset into "bzero" if no-builtin is specified. 
llvm-svn: 56888
 2008-09-30 22:05:33 +00:00
Bill Wendling
86f6fdc7e3 - Initialize "--no-builtin" to "false". 
- Testcase for r56885.

llvm-svn: 56886
 2008-09-30 21:40:30 +00:00
Evan Cheng
1c8ff02eeb Re-apply 56835 along with header file changes. 
llvm-svn: 56848
 2008-09-30 15:44:16 +00:00
Duncan Sands
a2c8482495 Revert commit 56835 since it breaks the build. 
"If a re-materializable instruction has a register
operand, the spiller will change the register operand's
spill weight to HUGE_VAL to avoid it being spilled.
However, if the operand is already in the queue ready
to be spilled, avoid re-materializing it".

llvm-svn: 56837
 2008-09-30 10:00:30 +00:00
Evan Cheng
4eee17f4fb If a re-materializable instruction has a register operand, the spiller will change the register operand's spill weight to HUGE_VAL to avoid it being spilled. However, if the operand is already in the queue ready to be spilled, avoid re-materializing it. 
llvm-svn: 56835
 2008-09-30 06:36:58 +00:00
Evan Cheng
b749199c34 Fix PR2835. Do not change the width of a volatile load. 
llvm-svn: 56792
 2008-09-29 17:26:18 +00:00
Evan Cheng
28d9b3a8ad Re-apply 56683 with fixes. 
llvm-svn: 56748
 2008-09-27 01:56:22 +00:00
Devang Patel
47a504c87c Implement function notes as function attributes. 
llvm-svn: 56716
 2008-09-26 23:51:19 +00:00
Evan Cheng
d63fc80c1e Implement "punpckldq %xmm0, $xmm0" as "pshufd $0x50, %xmm0, %xmm" unless optimizing for code size. 
llvm-svn: 56711
 2008-09-26 23:41:32 +00:00
Bill Wendling
7273078850 Temporarily reverting r56683. This is causing a failure during the build of llvm-gcc: 
/Volumes/Gir/devel/llvm/clean/llvm-gcc.obj/./gcc/xgcc -B/Volumes/Gir/devel/llvm/clean/llvm-gcc.obj/./gcc/ -B/Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/bin/ -B/Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/lib/ -isystem /Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/include -isystem /Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/sys-include -mmacosx-version-min=10.4 -O2  -O2 -g -O2  -DIN_GCC    -W -Wall -Wwrite-strings -Wstrict-prototypes -Wmissing-prototypes -Wold-style-definition  -isystem ./include  -fPIC -pipe -g -DHAVE_GTHR_DEFAULT -DIN_LIBGCC2 -D__GCC_FLOAT_NOT_NEEDED  -I. -I. -I../../llvm-gcc.src/gcc -I../../llvm-gcc.src/gcc/. -I../../llvm-gcc.src/gcc/../include -I./../intl -I../../llvm-gcc.src/gcc/../libcpp/include  -I../../llvm-gcc.src/gcc/../libdecnumber -I../libdecnumber -I/Volumes/Gir/devel/llvm/clean/llvm.obj/include -I/Volumes/Gir/devel/llvm/clean/llvm.src/include -fexceptions -fvisibility=hidden -DHIDE_EXPORTS -c ../../llvm-gcc.src/gcc/unwind-dw2-fde-darwin.c -o libgcc/./unwind-dw2-fde-darwin.o
Assertion failed: (TargetRegisterInfo::isVirtualRegister(regA) && TargetRegisterInfo::isVirtualRegister(regB) && "cannot update physical register live information"), function runOnMachineFunction, file /Volumes/Gir/devel/llvm/clean/llvm.src/lib/CodeGen/TwoAddressInstructionPass.cpp, line 311.
../../llvm-gcc.src/gcc/unwind-dw2.c:1527: internal compiler error: Abort trap
Please submit a full bug report,
with preprocessed source if appropriate.
See <URL:http://developer.apple.com/bugreporter> for instructions.
{standard input}:3521:non-relocatable subtraction expression, "_dwarf_reg_size_table" minus "L20$pb"
{standard input}:3521:symbol: "_dwarf_reg_size_table" can't be undefined in a subtraction expression
{standard input}:3520:non-relocatable subtraction expression, "_dwarf_reg_size_table" minus "L20$pb"
...

llvm-svn: 56703
 2008-09-26 22:10:44 +00:00
Evan Cheng
9946443460 Fix @llvm.frameaddress codegen. FP elimination optimization should be disabled when frame address is desired. Also add support for depth > 0. 
llvm-svn: 56683
 2008-09-26 19:48:35 +00:00
Evan Cheng
b4d6625c85 Avoid spilling EBP / RBP twice in the prologue. 
llvm-svn: 56675
 2008-09-26 19:14:21 +00:00
Evan Cheng
c8674dcfd0 Prefer movlhps over punpcklqdq, etc. in more cases. 
llvm-svn: 56627
 2008-09-25 23:35:16 +00:00
Evan Cheng
d190aeb62d With sse3 and when the source is a load or has multiple uses, favors movddup over shuffp*, pshufd, etc. Without sse3 or when the source is from a register, make use of movlhps 
llvm-svn: 56620
 2008-09-25 20:50:48 +00:00
Dale Johannesen
62f64ab4c8 Accept 'inreg' attribute on x86 functions as 
meaning sse_regparm (i.e. float/double values go
in XMM0 instead of ST0).  Update documentation
to reflect reality.

llvm-svn: 56619
 2008-09-25 20:47:45 +00:00
Evan Cheng
efd1f614ff Fix patterns for SSE4.1 move and sign extend instructions. Also add instructions which fold VZEXT_MOVL and VZEXT_LOAD. 
llvm-svn: 56594
 2008-09-24 23:27:55 +00:00
Dale Johannesen
4184c23365 Remove SelectionDag early allocation of registers 
for earlyclobbers.  Teach Local RA about earlyclobber,
and add some tests for it.

llvm-svn: 56592
 2008-09-24 23:13:09 +00:00
Evan Cheng
f942615847 Properly handle 'm' inline asm constraints. If a GV is being selected for the addressing mode, it requires the same logic for PIC relative addressing, etc. 
llvm-svn: 56526
 2008-09-24 00:05:32 +00:00
Evan Cheng
5bf702d20a Support x86 specific inline asm modifier 'J'. 
llvm-svn: 56483
 2008-09-22 23:57:37 +00:00
Arnold Schwaighofer
49f49e2086 Change the calling convention used when tail call optimization is enabled from CC_X86_32_TailCall to CC_X86_32_FastCC. 
llvm-svn: 56436
 2008-09-22 14:50:07 +00:00
Evan Cheng
270178bdda Fix PR2808. When regalloc runs out of register, it spill a physical register around the live interval being allocated. Do not continue to try to spill another register, just grab the physical register and move on. 
llvm-svn: 56381
 2008-09-20 01:28:05 +00:00
Evan Cheng
c01e6c2f59 Clean up the test. 
llvm-svn: 56380
 2008-09-20 01:26:27 +00:00
Evan Cheng
6a86ec1ef0 No need to print function stubs for Mac OS X 10.5 and up. Linker will handle it. 
llvm-svn: 56378
 2008-09-20 00:13:45 +00:00
Dan Gohman
f66b3277d3 Refactor X86SelectConstAddr, folding it into X86SelectAddress. This 
results in better code for globals. Also, unbreak the local CSE for
GlobalValue stub loads.

llvm-svn: 56371
 2008-09-19 22:16:54 +00:00
Evan Cheng
14493ffe78 Re-materalized definition instructions may be dead. Whack them. 
llvm-svn: 56352
 2008-09-19 17:38:47 +00:00
Dale Johannesen
99091ed94f Add a bit to mark operands of asm's that conflict 
with an earlyclobber operand elsewhere.  Propagate
this bit and the earlyclobber bit through SDISel.
Change linear-scan RA not to allocate regs in a way 
that conflicts with an earlyclobber.  See also comments.

llvm-svn: 56290
 2008-09-17 21:13:11 +00:00
Evan Cheng
d3225118a6 Unallocatable registers do not have live intervals. 
llvm-svn: 56287
 2008-09-17 18:36:25 +00:00
Bill Wendling
b2701e541c Add trampoline support to PPC. GCC simply calls the "__trampoline_setup" 
function with appropriate parameters. This allows us to support blocks on PPC.

llvm-svn: 56267
 2008-09-17 00:30:57 +00:00
Dan Gohman
faa15214e0 Teach LSR to optimize away SMAX operations for tripcounts in common 
cases.  See the comment above OptimizeSMax for the full story, and
the testcase for an example. This cancels out a pessimization
commonly attributed to indvars, and will allow us to lift some of
the artificial throttles in indvars, rather than add new ones.

llvm-svn: 56230
 2008-09-15 21:22:06 +00:00
Dan Gohman
f38d63884f Re-enable SelectionDAG CSE for calls. It matters in the case of 
libcalls, as in this testcase on ARM.

llvm-svn: 56226
 2008-09-15 19:46:03 +00:00
Bruno Cardoso Lopes
5463c59693 Added testcase for bswap allegrexel intrinsic 
llvm-svn: 56225
 2008-09-15 19:38:11 +00:00
Evan Cheng
db1693cb14 Correctly update kill infos after extending a live range and merge 2 val#'s; fix 56165 - do not mark val# copy field if the copy does not define the val#. 
llvm-svn: 56199
 2008-09-15 06:28:41 +00:00
Evan Cheng
07046dae41 On some targets, non-move instructions can become move instructions because of coalescing. e.g. 
vr2 = OR vr0, vr1
=>
vr2 = OR vr1, vr1   // after coalescing vr0 with vr1

Update the value# of the destination register with the copy instruction if that happens.

llvm-svn: 56165
 2008-09-12 18:13:14 +00:00
Arnold Schwaighofer
9cfcc68e04 Add indirect tail call (function pointer) examples. 
llvm-svn: 56127
 2008-09-11 22:24:28 +00:00
Arnold Schwaighofer
adfb111f10 When tailcallopt is enabled all fastcc calls must have an aligned argument stack size. Add a test case. 
llvm-svn: 56119
 2008-09-11 20:28:43 +00:00
Evan Cheng
5c7e3783ef Fix PR2748. Avoid coalescing physical register with virtual register which would create illegal extract_subreg. e.g. 
vr1024 = extract_subreg vr1025, 1
...
vr1024 = mov8rr AH
If vr1024 is coalesced with AH, the extract_subreg is now illegal since AH does not have a super-reg whose sub-register 1 is AH.

llvm-svn: 56118
 2008-09-11 20:07:10 +00:00
Evan Cheng
99be914c9a Fix PR2783 - coalescer bug. Missing a TargetRegisterInfo::isVirtualRegister check. 
llvm-svn: 56112
 2008-09-11 18:40:32 +00:00
Evan Cheng
b879f93ba5 Propagate subreg index when promoting a load to a copy. 
llvm-svn: 56085
 2008-09-11 01:02:12 +00:00
Evan Cheng
83c694fbe7 Fix a fastcc + sret bug. If fastcc and sret, callee doesn't need to pop the hidden struct ptr; Re-enable fastcc. 
llvm-svn: 56061
 2008-09-10 18:25:29 +00:00
Evan Cheng
ba11945234 Legalizer was missing code that expand fpow to a libcall. 
llvm-svn: 56028
 2008-09-09 23:02:14 +00:00
Evan Cheng
304fba81c9 Fix PR2757. Ignore liveinterval register allocation preference if the preference register is not in the right register class. This can happen due to sub-register coalescing. 
llvm-svn: 56006
 2008-09-09 20:22:01 +00:00
Evan Cheng
dc011a1b10 Fix a constant lowering bug. Now we can do load and store instructions with funky getelementptr embedded in the address operand. 
llvm-svn: 55975
 2008-09-09 01:26:59 +00:00
Anton Korobeynikov
afd49daa42 Reapply 55902: Add test for checking proper lowering of eh_return & unwind init intrinsics on 32bit x86 targets 
llvm-svn: 55960
 2008-09-08 21:14:36 +00:00
Anton Korobeynikov
ddf0f04445 Reapply 55903: Testcase for 64-bit lowering of eh_return & unwind_init 
llvm-svn: 55959
 2008-09-08 21:14:19 +00:00
Dan Gohman
6f360fc081 Add a target triple; apparently LLVM doesn't use 64-bit 
data directives on darwin.

llvm-svn: 55941
 2008-09-08 20:16:18 +00:00
Bill Wendling
122df59fda Remove these testcases associated with changes between r 55898 and r 55909. 
llvm-svn: 55931
 2008-09-08 18:00:39 +00:00
Bill Wendling
4cc4caab72 Reverting r55898 to r55909. One of these patches was causing an ICE during the full bootstrap on Darwin: 
/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/xgcc
-B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/
-B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/bin/
-B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/lib/
-isystem /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/include
-isystem /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/sys-include
-O2  -O2 -g -O2  -DIN_GCC    -W -Wall -Wwrite-strings
-Wstrict-prototypes -Wmissing-prototypes -Wold-style-definition
-isystem ./include  -fPIC -pipe -g -DHAVE_GTHR_DEFAULT -DIN_LIBGCC2
-D__GCC_FLOAT_NOT_NEEDED  -I. -I. -I../../llvm-gcc.src/gcc
-I../../llvm-gcc.src/gcc/. -I../../llvm-gcc.src/gcc/../include
-I./../intl -I../../llvm-gcc.src/gcc/../libcpp/include
-I../../llvm-gcc.src/gcc/../libdecnumber -I../libdecnumber
-I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.obj/include
-I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.src/include
-DSHARED -m64 -DL_negdi2 -c ../../llvm-gcc.src/gcc/libgcc2.c -o
libgcc/x86_64/_negdi2_s.o
Assertion failed: (TargetRegisterInfo::isVirtualRegister(regA) &&
TargetRegisterInfo::isVirtualRegister(regB) && "cannot update physical
register live information"), function runOnMachineFunction, file
/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.src/lib/CodeGen/TwoAddressInstructionPass.cpp,
line 311.
/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/xgcc
-B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/
-B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/bin/
-B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/lib/
-isystem /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/include
-isystem /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/sys-include
-O2  -O2 -g -O2  -DIN_GCC    -W -Wall -Wwrite-strings
-Wstrict-prototypes -Wmissing-prototypes -Wold-style-definition
-isystem ./include  -fPIC -pipe -g -DHAVE_GTHR_DEFAULT -DIN_LIBGCC2
-D__GCC_FLOAT_NOT_NEEDED  -I. -I. -I../../llvm-gcc.src/gcc
-I../../llvm-gcc.src/gcc/. -I../../llvm-gcc.src/gcc/../include
-I./../intl -I../../llvm-gcc.src/gcc/../libcpp/include
-I../../llvm-gcc.src/gcc/../libdecnumber -I../libdecnumber
-I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.obj/include
-I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.src/include
-DSHARED -m64 -DL_lshrdi3 -c ../../llvm-gcc.src/gcc/libgcc2.c -o
libgcc/x86_64/_lshrdi3_s.o
../../llvm-gcc.src/gcc/unwind-dw2.c:1527: internal compiler error: Abort trap
Please submit a full bug report,
with preprocessed source if appropriate.
See <URL:http://developer.apple.com/bugreporter> for instructions.
{standard input}:unknown:Undefined local symbol LBB21_11
{standard input}:unknown:Undefined local symbol LBB21_12
{standard input}:unknown:Undefined local symbol LBB21_13
{standard input}:unknown:Undefined local symbol LBB21_8

llvm-svn: 55928
 2008-09-08 17:59:12 +00:00
Evan Cheng
fc78ac5bbe Handle calls which produce i1 results: promote to i8 but and it with 1 to get the low bit. 
llvm-svn: 55925
 2008-09-08 17:15:42 +00:00
Dan Gohman
f2a912c2a7 Add AsmPrinter support for i128 and larger static initializer data. 
llvm-svn: 55919
 2008-09-08 16:40:13 +00:00
Anton Korobeynikov
0da56882db Testcase for 64-bit lowering of eh_return & unwind_init 
llvm-svn: 55903
 2008-09-08 14:23:16 +00:00
Anton Korobeynikov
7dc16250e7 Add test for checking proper lowering of eh_return & unwind init intrinsics on 32bit x86 targets 
llvm-svn: 55902
 2008-09-08 14:22:57 +00:00
Rafael Espindola
ce4f075afd Add testcase from bug 2770. 
llvm-svn: 55897
 2008-09-08 11:17:54 +00:00
Evan Cheng
f8d8287454 Correctly handle physical register inputs. They are not explicit input operands in the resulting machine instrs. 
llvm-svn: 55893
 2008-09-08 08:39:33 +00:00
Evan Cheng
6690ccd573 Handle x86 truncate to i8 with target hook for now. 
llvm-svn: 55877
 2008-09-07 08:47:42 +00:00
Eli Friedman
fecea4b498 Fix for PR2687: Add patterns to match sint_to_fp and fp_to_sint for <2 x 
i32>.  This is a little messy, but it works.

We should really get rid of the intrinsics, though, since they map
perfectly well to standard LLVM instructions.

llvm-svn: 55864
 2008-09-05 23:07:03 +00:00
Evan Cheng
1f4b84cad0 Fix test. 
llvm-svn: 55849
 2008-09-05 20:04:37 +00:00
Evan Cheng
10a350fa89 If SSE2 is available, x86 should pass first 3 f32/f64 arguments in XMM registers for fastcc calls. 
llvm-svn: 55840
 2008-09-05 17:24:07 +00:00
Evan Cheng
bd15e330d0 For whatever the reason, x86 CallingConv::Fast (i.e. fastcc) was not passing scalar arguments in registers. This patch defines a new fastcc CC which is slightly different from the FastCall CC. In addition to passing integer arguments in ECX and EDX, it also specify doubles are passed in 8-byte slots which are 8-byte aligned (instead of 4-byte aligned). This avoids a potential performance hazard where doubles span cacheline boundaries. 
llvm-svn: 55807
 2008-09-04 22:59:58 +00:00
Owen Anderson
cd3ee9198d Fix the ordering of operands to the store (inverted relative to LLVM IR), and fix the testcase. 
llvm-svn: 55777
 2008-09-04 16:48:33 +00:00
Owen Anderson
35485dbae3 Add a first attempt at implementing stores for X86 fast isel using target hooks. 
Dan or Evan, please review.

llvm-svn: 55764
 2008-09-04 07:08:58 +00:00
Evan Cheng
9c728a557d Load from GV stub should be locally CSE'd. 
llvm-svn: 55763
 2008-09-04 06:18:33 +00:00
Evan Cheng
53ce5fa5ce Remove code that pad number of bytes to pop for X86_FastCall CC. The code doesn't do the "aligning" for Cygwin, Mingw, and Windows. But aligning it on Darwin and Linux breaks gcc compatibility. That ruled out all the platforms we support! 
llvm-svn: 55756
 2008-09-04 01:04:15 +00:00
Evan Cheng
942d55dd92 Add X86 target hook to implement load (even from GlobalAddress). 
llvm-svn: 55693
 2008-09-03 06:44:39 +00:00
Duncan Sands
044fcaf6b4 Turn this legalize types test on. 
llvm-svn: 55605
 2008-09-01 12:00:55 +00:00
Bill Wendling
297eb080b6 Revert the "XFAIL" for the rotate_ops.ll testcase. Instead, mark ISD::ROTR 
instructions in CellSPU as "Expand" so that they won't be generated. I added a
"FIXME" so that this hack can be addressed and reverted once ISD::ROTR is
supported in the .td files.

llvm-svn: 55582
 2008-08-31 02:59:23 +00:00
Bill Wendling
5c442aafb6 CellSPU doesn't appear to support fully the "ISD::ROTR" operation. The DAG 
combiner can now generate ROTR if the backend says that it can handle it. Cell
SPU says this, but gets an error from code gen saying that it can't select
ROTR. I'm xfailing this test until this can be fixed.

llvm-svn: 55579
 2008-08-31 02:32:12 +00:00
Evan Cheng
b40b710766 Re-apply 55467 with fix. If copy is being replaced by remat'ed def, transfer the implicit defs onto the remat'ed instruction. 
llvm-svn: 55564
 2008-08-30 09:09:33 +00:00
Evan Cheng
4bc8c9652e Transform (x << (y&31)) -> (x << y). This takes advantage of the fact x86 shift instructions 2nd operand (shift count) is limited to 0 to 31 (or 63 in the x86-64 case). 
llvm-svn: 55558
 2008-08-30 02:03:58 +00:00
Dale Johannesen
0124a7db51 Testcases for ppc atomics. 
llvm-svn: 55556
 2008-08-30 00:54:31 +00:00
Evan Cheng
c1c53221c5 Swap fp comparison operands and change predicate to allow load folding (safely this time). 
llvm-svn: 55553
 2008-08-29 23:22:12 +00:00
Evan Cheng
79d2a8f97d xfail this. 
llvm-svn: 55550
 2008-08-29 22:59:13 +00:00
Chris Lattner
f24550c9d2 allow this to pass. 
llvm-svn: 55540
 2008-08-29 17:18:26 +00:00
Evan Cheng
cdd06ba3f4 Swap fp comparison operands and change predicate to allow load folding. 
llvm-svn: 55521
 2008-08-28 23:48:31 +00:00
Mon P Wang
7566974359 In lowering SELECT_CC, removed cases where we can't flip the true and false when the compare value has a NaN 
llvm-svn: 55499
 2008-08-28 21:04:05 +00:00
Dan Gohman
35a69c106a Optimize DAGCombiner's worklist processing. Previously it started 
its work by putting all nodes in the worklist, requiring a big
dynamic allocation. Now, DAGCombiner just iterates over the AllNodes
list and maintains a worklist for nodes that are newly created or
need to be revisited. This allows the worklist to stay small in most
cases, so it can be a SmallVector.

This has the side effect of making DAGCombine not miss a folding
opportunity in alloca-align-rounding.ll.

llvm-svn: 55498
 2008-08-28 21:01:56 +00:00
Dan Gohman
8f4d612996 Revert r55467; it causes regressions in UnitTests/Vector/divides, 
Benchmarks/sim/sim, and others on x86-64.

llvm-svn: 55475
 2008-08-28 17:22:54 +00:00
Evan Cheng
28b0b18082 If a copy isn't coalesced, but its src is defined by trivial computation. Re-materialize the src to replace the copy. 
llvm-svn: 55467
 2008-08-28 07:53:51 +00:00
Dale Johannesen
ae522b8463 This test crashes on non-x86 host; make SSE explicit. 
Feel free to fix a better way!

llvm-svn: 55456
 2008-08-28 01:51:09 +00:00
Dan Gohman
5e5f1c9e8f Basic FastISel support for floating-point constants. 
llvm-svn: 55401
 2008-08-27 01:09:54 +00:00
Chris Lattner
c5c00890e5 If an xmm register is referenced explicitly in an inline asm, make sure to 
assign it to a version of the xmm register with the regclass that matches its
type.  This fixes PR2715, a bug handling some crazy xpcom case in mozilla.

llvm-svn: 55358
 2008-08-26 06:19:02 +00:00
Evan Cheng
569b489cf5 Try approach to moving call address load inside of callseq_start. Now it's done during the preprocess of x86 isel. callseq_start's chain is changed to load's chain node; while load's chain is the last of callseq_start or the loads or copytoreg nodes inserted to move arguments to the right spot. 
llvm-svn: 55338
 2008-08-25 21:27:18 +00:00
Owen Anderson
27491bbf2c Add support for fast isel of (integer) immediate materialization pattens, and use them to support 
bitcast of constants in fast isel.

llvm-svn: 55325
 2008-08-25 20:20:32 +00:00
Dale Johannesen
6431c39237 Adjust grep's for new code sequence. 
llvm-svn: 55320
 2008-08-25 18:53:58 +00:00
Evan Cheng
2b9f879a99 Fix asm printing of MOVSDto64mr and MOV64toSDrm. 
llvm-svn: 55300
 2008-08-25 04:11:42 +00:00
Bill Wendling
05e1910595 Fix this test. Don't null out the file, just XFAIL it until patch can be fixed. 
llvm-svn: 55296
 2008-08-24 21:48:46 +00:00
Bill Wendling
5728cf59fd Temporarily reverting r55292. It's causing a bootstraping failure: 
/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/xgcc ... src/libiberty/make-temp-file.c -o make-temp-file.o
Assertion failed: (Node2Index[SU->NodeNum] > Node2Index[I->Dep->NodeNum] && "Wrong topological sorting"), function InitDAGTopologicalSorting, file /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.src/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp, line 508.
../../../../llvm-gcc.src/libiberty/hashtab.c:955: internal compiler error: Abort trap
Please submit a full bug report,
with preprocessed source if appropriate.
See <URL:http://developer.apple.com/bugreporter> for instructions.
make[4]: *** [hashtab.o] Error 1
make[4]: *** Waiting for unfinished jobs....
make[3]: *** [multi-do] Error 1
make[2]: *** [all] Error 2
make[1]: *** [all-target-libiberty] Error 2
make: *** [all] Error 2

llvm-svn: 55295
 2008-08-24 21:45:30 +00:00
Evan Cheng
a600778748 Move callseq_start above the call address load to allow load to be folded into the call node. 
llvm-svn: 55292
 2008-08-24 19:19:55 +00:00
Anton Korobeynikov
496a2865db Testcase for 64bit maskmovq 
llvm-svn: 55239
 2008-08-23 15:53:47 +00:00
Dale Johannesen
a8dbf73ffd Test all currently supported atomic builtins on x86-{32,64}. 
These just test that they go through the BE.

llvm-svn: 55208
 2008-08-22 22:39:21 +00:00
Dan Gohman
a398d11527 Factor out the predicate check code from DAGISelEmitter.cpp 
and use it in FastISelEmitter.cpp, and make FastISel
subtarget aware. Among other things, this lets it work
properly on x86 targets that don't have SSE, where it
successfully selects x87 instructions.

llvm-svn: 55156
 2008-08-22 00:20:26 +00:00
Bill Wendling
8ff0d8f829 Testcase for PR2585. 
llvm-svn: 55151
 2008-08-21 23:04:49 +00:00
Dan Gohman
4562b2bcfe Add -mattr=sse2 so this test doesn't fail on non-x86 hosts. 
llvm-svn: 55145
 2008-08-21 22:34:25 +00:00
Dale Johannesen
6fe9da3acc Make x86 and sse2 explicit for non-x86 hosts. 
llvm-svn: 55141
 2008-08-21 21:26:06 +00:00
Evan Cheng
ef2509b3ba Fix a number of byval / memcpy / memset related codegen issues. 
1. x86-64 byval alignment should be max of 8 and alignment of type. Previously the code was not doing what the commit message was saying.
2. Do not use byte repeat move and store operations. These are slow.

llvm-svn: 55139
 2008-08-21 21:00:15 +00:00
Dan Gohman
42fa2945d3 getelementptr doesn't work on x86-64 yet, because it 
has MOV64ri32 and no plain MOV64ri.

llvm-svn: 55126
 2008-08-21 17:28:42 +00:00