RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-25 20:23:11 +01:00
Code Issues Projects Releases Wiki Activity
79,067 Commits 4 Branches 5 Tags 704 MiB
dbc281bcbe
Commit Graph

79067 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Akira Hatanaka
1af9c41014 Revert part of r146995 that was accidentally commmitted. 
llvm-svn: 146996
 2011-12-20 22:09:36 +00:00
Akira Hatanaka
9c5e4d3b90 32-to-64-bit sign extension pattern. 
llvm-svn: 146995
 2011-12-20 22:06:20 +00:00
Akira Hatanaka
dba6358adc Add a pattern for matching zero-store with 64-bit address. The pattern is enabled 
only when the target ABI is N64. 

llvm-svn: 146992
 2011-12-20 21:50:49 +00:00
Jim Grosbach
8978194025 ARM assembly parsing and encoding for VST2 single-element, double spaced. 
llvm-svn: 146990
 2011-12-20 20:46:29 +00:00
Lang Hames
843255f890 Fix assert condition. 
llvm-svn: 146987
 2011-12-20 20:23:40 +00:00
Jakub Staszak
6f3beda2b4 Add some constantness to BranchProbabilityInfo and BlockFrequnencyInfo. 
llvm-svn: 146986
 2011-12-20 20:03:10 +00:00
Jim Grosbach
3f48367a1b ARM enable a few more tests. 
llvm-svn: 146985
 2011-12-20 20:03:00 +00:00
Devang Patel
a57e0b8f49 Add support to add named metadata operand. 
Patch by Andrew Wilkins!

llvm-svn: 146984
 2011-12-20 19:29:36 +00:00
Jim Grosbach
8156a5dcee ARM assembly parsing and encoding for VLD2 single-element, double spaced. 
llvm-svn: 146983
 2011-12-20 19:21:26 +00:00
Evan Cheng
46b085721a ARM target code clean up. Check for iOS, not Darwin where it makes sense. 
llvm-svn: 146981
 2011-12-20 18:26:50 +00:00
Jason W Kim
139dd49440 First steps in ARM AsmParser support for .eabi_attribute and .arch 
(Both used for Linux gnueabi)
No behavioral change yet (no tests need so far)

llvm-svn: 146977
 2011-12-20 17:38:12 +00:00
Elena Demikhovsky
b37883fe87 This is the second fix related to VZEXT_MOVL node. 
The failure that I see in the current version is:

LLVM ERROR: Cannot select: 0x18b8f70: v4i64 = X86ISD::VZEXT_MOVL 0x18beee0 [ID=14]
  0x18beee0: v4i64 = insert_subvector 0x18b8c70, 0x18b9170, 0x18b9570 [ID=13]
    0x18b8c70: v4i64 = insert_subvector 0x18b9870, 0x18bf4e0, 0x18b9970 [ID=12]
      0x18b9870: v4i64 = undef [ID=4]
      0x18bf4e0: v2i64 = bitcast 0x18bf3e0 [ID=10]
        0x18bf3e0: v4i32 = BUILD_VECTOR 0x18b9770, 0x18b9770, 0x18b9770, 0x18b9770 [ID=8]
          0x18b9770: i32 = TargetConstant<0> [ID=6]
          0x18b9770: i32 = TargetConstant<0> [ID=6]
          0x18b9770: i32 = TargetConstant<0> [ID=6]
          0x18b9770: i32 = TargetConstant<0> [ID=6]
      0x18b9970: i32 = Constant<0> [ID=3]
    0x18b9170: v2i64 = undef [ORD=1] [ID=1]
    0x18b9570: i32 = Constant<2> [ID=5]

llvm-svn: 146975
 2011-12-20 13:34:28 +00:00
Chandler Carruth
7564e8371a Begin teaching the X86 target how to efficiently codegen patterns that 
use the zero-undefined variants of CTTZ and CTLZ. These are just simple
patterns for now, there is more to be done to make real world code using
these constructs be optimized and codegen'ed properly on X86.

The existing tests are spiffed up to check that we no longer generate
unnecessary cmov instructions, and that we generate the very important
'xor' to transform bsr which counts the index of the most significant
one bit to the number of leading (most significant) zero bits. Also they
now check that when the variant with defined zero result is used, the
cmov is still produced.

llvm-svn: 146974
 2011-12-20 11:19:37 +00:00
Manuel Klimek
94bfd4f3fc Fixes a potential compilation error. 
Pulling the template implementation into the header to guarantee
that it's visible to all possible instantiations.

llvm-svn: 146973
 2011-12-20 11:04:23 +00:00
Manuel Klimek
9661304f32 Pulls the implementation of skip() into JSONParser. 
This is the first step towards migrating more of the parser
implementation into the parser class.

llvm-svn: 146971
 2011-12-20 10:42:52 +00:00
Manuel Klimek
8c643f1ae2 Fixing option for JSON benchmark broken since the change to size_t. 
llvm-svn: 146970
 2011-12-20 10:34:29 +00:00
Manuel Klimek
e08a021292 Addressing style issues in JSON parser. 
llvm-svn: 146968
 2011-12-20 09:26:26 +00:00
Chandler Carruth
1663697160 Fix up the CMake build for the new files added in r146960, they're 
likely to stay either way that discussion ends up resolving itself.

llvm-svn: 146966
 2011-12-20 08:42:11 +00:00
David Blaikie
0c4ffec904 Revert pragma clang suppressions that confuse GCC. (I'll worry about how to suppress/fix these problems properly when we figure out how to keep LLVM -Wweak-vtables clean) 
llvm-svn: 146965
 2011-12-20 08:22:49 +00:00
Nadav Rotem
682f1c2187 Add a few lines to the release notes: 
1. pointer-vector
2. type legalizer changes and vector-select
3. X86 ISA changes.

llvm-svn: 146964
 2011-12-20 08:02:50 +00:00
David Blaikie
576aba04f1 Unweaken vtables as per http://llvm.org/docs/CodingStandards.html#ll_virtual_anch 
llvm-svn: 146960
 2011-12-20 02:50:00 +00:00
Andrew Trick
a1c4f73f87 Unit test for r146950: LSR postinc expansion, PR11571. 
llvm-svn: 146951
 2011-12-20 01:43:20 +00:00
Andrew Trick
a2555fd695 LSR: Fix another corner case in expansion of postinc users. 
Fixes PR11571: Instruction does not dominate all uses

llvm-svn: 146950
 2011-12-20 01:42:24 +00:00
Bob Wilson
8439df9506 Mark ARM eh_sjlj_dispatchsetup as clobbering all registers. Radar 10567930. 
We used to rely on the *eh_sjlj_setjmp instructions to mark that a function
with setjmp/longjmp exception handling clobbers all the registers.  But with
the recent reorganization of ARM EH, those eh_sjlj_setjmp instructions are
expanded away earlier, before PEI can see them to determine what registers to
save and restore.  Mark the dispatchsetup instruction in the same way, since
that instruction cannot be expanded early.  This also more accurately reflects
when the registers are clobbered.

llvm-svn: 146949
 2011-12-20 01:29:27 +00:00
Chris Lattner
f60c5dadf8 fix typo 
llvm-svn: 146940
 2011-12-20 01:11:37 +00:00
Dan Gohman
80dc86c550 Add a line to ReleaseNotes for half float. 
llvm-svn: 146939
 2011-12-20 01:10:56 +00:00
Jim Grosbach
3f5493c136 ARM assembly shifts by zero should be plain 'mov' instructions. 
"mov r1, r2, lsl #0" should assemble as "mov r1, r2" even though it's
not strictly legal UAL syntax. It's a common extension and the friendly
thing to do.

rdar://10604663

llvm-svn: 146937
 2011-12-20 00:59:38 +00:00
Chris Lattner
c1d9c0a2a3 Now that PR11464 is fixed, reapply the patch to fix PR11464, 
merging types by name when we can.  We still don't guarantee type name linkage
but we do it when obviously the right thing to do.  This makes LTO type names 
easier to read, for example.

llvm-svn: 146932
 2011-12-20 00:12:26 +00:00
Chris Lattner
998998b3e7 fix PR11464 by preventing the linker from mapping two different struct types from the source module onto the same opaque destination type. An opaque type can only be resolved to one thing or another after all. 
llvm-svn: 146929
 2011-12-20 00:03:52 +00:00
Chris Lattner
151b0ec955 add a method to improve compatibility with SmallVector. 
llvm-svn: 146928
 2011-12-20 00:03:41 +00:00
Dan Gohman
7940e4e81d Add basic generic CodeGen support for half. 
llvm-svn: 146927
 2011-12-20 00:02:33 +00:00
Jim Grosbach
b1b83d2f58 ARM NEON assembly aliases for VMOV<-->VMVN for i32 immediates. 
e.g., "vmov.i32 d4, #-118" can be assembled as "vmvn.i32 d4, #117"

rdar://10603913

llvm-svn: 146925
 2011-12-19 23:51:07 +00:00
Evan Cheng
9362ee62bc Move tests to FileCheck. 
llvm-svn: 146923
 2011-12-19 23:26:44 +00:00
Jim Grosbach
343f270350 ARM assembly parsing and encoding support for LDRD(label). 
rdar://9932658

llvm-svn: 146921
 2011-12-19 23:06:24 +00:00
Evan Cheng
4c77fb5375 Add a if-conversion optimization that allows 'true' side of a diamond to be 
unpredicated. That is, turn
 subeq  r0, r1, #1
 addne  r0, r1, #1                                                                                                                                                                                                     
into
 sub    r0, r1, #1
 addne  r0, r1, #1

For targets where conditional instructions are always executed, this may be
beneficial. It may remove pseudo anti-dependency in out-of-order execution
CPUs. e.g.
 op    r1, ...
 str   r1, [r10]        ; end-of-life of r1 as div result
 cmp   r0, #65
 movne r1, #44  ; raw dependency on previous r1
 moveq r1, #12

If movne is unpredicated, then
 op    r1, ...
 str   r1, [r10]
 cmp   r0, #65
 mov   r1, #44  ; r1 written unconditionally
 moveq r1, #12

Both mov and moveq are no longer depdendent on the first instruction. This gives
the out-of-order execution engine more freedom to reorder them.

This has passed entire LLVM test suite. But it has not been enabled for any ARM
variant pending more performance evaluation.

rdar://8951196

llvm-svn: 146914
 2011-12-19 22:01:30 +00:00
Eli Friedman
53dbd7d97f Add "using" to silence warnings. 
llvm-svn: 146913
 2011-12-19 21:53:12 +00:00
Akira Hatanaka
7ef923c1f0 Add a test case for r146900. 
llvm-svn: 146901
 2011-12-19 20:24:28 +00:00
Akira Hatanaka
e54da3bfa2 Add patterns for matching immediates whose lower 16-bit is cleared. These 
patterns emit a single LUi instruction instead of a pair of LUi and ORi.

llvm-svn: 146900
 2011-12-19 20:21:18 +00:00
Eli Friedman
602ab7a677 Attempt to fix PR11607 by shuffling around which class defines which methods. 
llvm-svn: 146897
 2011-12-19 20:06:03 +00:00
Akira Hatanaka
5ac6df52af Tidy up. Simplify logic. No functional change intended. 
llvm-svn: 146896
 2011-12-19 19:52:25 +00:00
Jim Grosbach
797a88284c ARM NEON two-operand aliases for VPADD. 
rdar://10602276

llvm-svn: 146895
 2011-12-19 19:51:03 +00:00
Akira Hatanaka
804863071f Remove definitions of double word shift plus 32 instructions. Assembler or 
direct-object emitter should emit the appropriate shift instruction depending
on the shift amount.

llvm-svn: 146893
 2011-12-19 19:44:09 +00:00
Jim Grosbach
f9910809c5 ARM VFP pre-UAL mnemonic aliases for fmul[sd]. 
llvm-svn: 146892
 2011-12-19 19:43:50 +00:00
Akira Hatanaka
ea1f905123 Remove unused predicate. 
llvm-svn: 146889
 2011-12-19 19:32:20 +00:00
Akira Hatanaka
b7ebcb2ded Remove the restriction on the first operand of the add node in SelectAddr. 
This change reduces the number of instructions generated.

For example, 
(load (add (sub $n0, $n1), (MipsLo got(s))))

results in the following sequence of instructions:
1. sub $n2, $n0, $n1
2. lw got(s)($n2)

Previously, three instructions were needed.
1. sub $n2, $n0, $n1
2. addiu $n3, $n2, got(s)
3. lw 0($n3)

llvm-svn: 146888
 2011-12-19 19:28:37 +00:00
Jim Grosbach
6e9471925b ARM VFP pre-UAL mnemonic aliases for fcpy[sd] and fdiv[sd]. 
llvm-svn: 146887
 2011-12-19 19:02:41 +00:00
Jim Grosbach
520db82971 ARM NEON implied destination aliases for VMAX/VMIN. 
llvm-svn: 146885
 2011-12-19 18:57:38 +00:00
Jim Grosbach
f4ca84a7ab ARM NEON relax parse time diagnostics for alignment specifiers. 
There's more variation that we need to handle. Error checking will need
to be on operand predicates.

llvm-svn: 146884
 2011-12-19 18:31:43 +00:00
Jim Grosbach
2a0ced60a5 Tidy up. 
llvm-svn: 146882
 2011-12-19 18:11:17 +00:00
Jakob Stoklund Olesen
7b1b08eb77 Remove a register class that can just as well be synthesized. 
Add the new TableGen register class synthesizer feature to the release
notes.

llvm-svn: 146875
 2011-12-19 16:53:40 +00:00