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Commit Graph

594 Commits

Author SHA1 Message Date
Chris Lattner
6a2abe8591 Convert XO XS and XFX forms to use isPPC64
llvm-svn: 21346
2005-04-19 04:40:07 +00:00
Chris Lattner
3cfa7a24cb Turn PPC64 and VMX into classes that can be added to instructions instead of
bits that must be passed up the inheritance hierarchy.  Convert MForm and AForm
instructions over

llvm-svn: 21345
2005-04-19 04:32:54 +00:00
Nate Begeman
3b1c0df702 Next round of PPC CR optimizations. For the following code:
int %bar(float %a, float %b, float %c, float %d) {
entry:
    %tmp.1 = setlt float %a, %d
    %tmp.2 = setlt float %b, %d
    %or = or bool %tmp.1, %tmp.2
    %tmp.3 = setgt float %c, %d
    %tmp.4 = or bool %or, %tmp.3
    %tmp.5 = and bool %tmp.4, true
    %retval = cast bool %tmp.5 to int
    ret int %retval
}

We now emit:

_bar:
.LBB_bar_0:     ; entry
        fcmpu cr0, f1, f4
        fcmpu cr1, f2, f4
        cror 0, 0, 4
        fcmpu cr1, f3, f4
        cror 28, 0, 5
        mfcr r2
        rlwinm r3, r2, 29, 31, 31
        blr

Instead of:

_bar:
.LBB_bar_0:     ; entry
        fcmpu cr7, f1, f4
        mfcr r2
        rlwinm r2, r2, 29, 31, 31
        fcmpu cr7, f2, f4
        mfcr r3
        rlwinm r3, r3, 29, 31, 31
        or r2, r2, r3
        fcmpu cr7, f3, f4
        mfcr r3
        rlwinm r3, r3, 30, 31, 31
        or r3, r2, r3
        blr

llvm-svn: 21321
2005-04-18 07:48:09 +00:00
Nate Begeman
85cd65b389 Change codegen for setcc to read the bit directly out of the condition
register.  Added support in the .td file for the g5-specific variant
  of cr -> gpr moves that executes faster, but we currently don't
  generate it.

llvm-svn: 21314
2005-04-18 02:43:24 +00:00
Chris Lattner
a1fd64a073 Handle ExternalSymbol operands in the PPC JIT
llvm-svn: 21312
2005-04-18 00:46:10 +00:00
Nate Begeman
ecb5b5c028 Make pattern isel default for ppc
Add new ppc beta option related to using condition registers
Make pattern isel control flag (-enable-pattern-isel) global and tristate
  0 == off
  1 == on
  2 == target default

llvm-svn: 21309
2005-04-15 22:12:16 +00:00
Nate Begeman
604895b03c Implement multi-way branches through logical ops on condition registers.
This can generate considerably shorter code, reducing the size of crafty
by almost 1%.  Also fix the printing of mcrf.  The code is currently
disabled until it gets a bit more testing, but should work as-is.

llvm-svn: 21298
2005-04-14 09:45:08 +00:00
Nate Begeman
b707ec16b4 Add the necessary support to codegen condition register logical ops with
register allocated condition registers.  Make sure that the printed
  output is gas compatible.

llvm-svn: 21295
2005-04-14 03:20:38 +00:00
Nate Begeman
99a9840b56 Start allocating condition registers. Almost all explicit uses of CR0 are
now gone.  Next step is to get rid of the remaining ones and then start
allocating bools to CRs where appropriate.

llvm-svn: 21294
2005-04-13 23:15:44 +00:00
Nate Begeman
ae49d52006 Implement the fold shift X, zext(Y) -> shift X, Y at the target level,
where it is safe to do so.

llvm-svn: 21293
2005-04-13 22:14:14 +00:00
Nate Begeman
20b3399465 Disbale the broken fold of shift + sz[ext] for now
Move the transform for select (a < 0) ? b : 0 into the dag from ppc isel
Enable the dag to fold and (setcc, 1) -> setcc for targets where setcc
  always produces zero or one.

llvm-svn: 21291
2005-04-13 21:23:31 +00:00
Chris Lattner
8489ac991d remove one more occurance of this that snuck in
llvm-svn: 21271
2005-04-13 02:46:17 +00:00
Chris Lattner
26c7c9150a Elimate handling of ZERO_EXTEND_INREG. This causes the PPC backend to emit
andi instructions instead of rlwinm instructions for zero extend, but they
seem like they would take the same time.

llvm-svn: 21268
2005-04-13 02:40:26 +00:00
Nate Begeman
a56527ea5f Fold shift by size larger than type size to undef
Make llvm undef values generate ISD::UNDEF nodes

llvm-svn: 21261
2005-04-12 23:12:17 +00:00
Nate Begeman
79c8b8fd1c Implement setcc op, -1 sequences
Remove dead setcc op, 0 sequences
Coming later: generalization of op, imm

llvm-svn: 21260
2005-04-12 21:22:28 +00:00
Nate Begeman
f96b42f1b6 Initial support for allocation condition registers
llvm-svn: 21246
2005-04-12 07:04:16 +00:00
Nate Begeman
a154deaaff Implement bitfield clears
Implement divide by negative power of two

llvm-svn: 21240
2005-04-12 00:10:02 +00:00
Nate Begeman
f31b58f145 Update PPC readme. Remove things that are done or aren't ppc specific
llvm-svn: 21232
2005-04-11 20:48:57 +00:00
Chris Lattner
ee715b2abc ORo sets CR0
llvm-svn: 21227
2005-04-11 15:03:48 +00:00
Chris Lattner
7d11f40ee2 Revert the previous patch, which I didn't mean to check in.
llvm-svn: 21226
2005-04-11 15:03:41 +00:00
Chris Lattner
d925c74452 Fix a minor bug (ORo didn't mark that it set CR0).
Refactor how . instructions are handled.  In particular, instead of passing
the RC flag all the way up the inheritance hierarchy, just make a new tblgen
class 'DOT' which can be added to an instruction definition.

For example, instead of this:

-def AND  : XForm_6<31,  28, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
-let Defs = [CR0] in
-def ANDo : XForm_6<31,  28, 1, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
-                   "and. $rA, $rS, $rB">;

We now have this:

+def AND  : XForm_6<31,  28, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
                    "and $rA, $rS, $rB">;

llvm-svn: 21225
2005-04-11 15:01:39 +00:00
Nate Begeman
783fe2108e Add recording variants of ISD::AND and ISD::OR. This kills almost 1000
(1.5%) instructions in 186.crafty

llvm-svn: 21222
2005-04-11 06:34:10 +00:00
Nate Begeman
34aa7ec9cb Fix another fixme: factor out the constant fp generation code.
llvm-svn: 21207
2005-04-10 06:06:10 +00:00
Nate Begeman
b6c9b326e3 Fix 64 bit argument loading that straddles the args in regs / args on stack
boundary.

llvm-svn: 21206
2005-04-10 05:53:14 +00:00
Nate Begeman
0a43e95718 Remove unnecessary Implicit Defs. Since r0 is not in allocation, we do not
have to inform the register allocator it might be stepped on.

llvm-svn: 21202
2005-04-10 03:59:42 +00:00
Nate Begeman
f5cedbc812 Make sure that BRCOND branches can be converted into long branches too.
llvm-svn: 21198
2005-04-10 01:48:29 +00:00
Nate Begeman
ab8e705a52 Don't hand ISD::CALL nodes off to SelectExprFP. This fixes siod.
llvm-svn: 21197
2005-04-10 01:14:13 +00:00
Chris Lattner
c1bacbff9d rename getPPCOpcodeForSetCCNumber -> getPPCOpcodeForSetCCOpode to be more
correct.  Remove the EmitComparison retvalue, as it is always the first arg.

Fix a place where we incorrectly passed in the setcc opcode instead of the
setcc number, causing us to miscompile crafty.  Crafty now works!

llvm-svn: 21195
2005-04-10 01:03:31 +00:00
Nate Begeman
a2374d39df fix ISD::BRCONDTWOWAY codegen to not deference the end() iterator
llvm-svn: 21193
2005-04-09 23:35:05 +00:00
Chris Lattner
17c60891c1 Fix CodeGen/Generic/2005-05-09-GlobalInPHI.ll, which was reduced from 254.gap.
This caused the "use before a def" assertion on some programs.

With this patch, 254.gap now passes with the PPC backend.

llvm-svn: 21191
2005-04-09 22:05:17 +00:00
Chris Lattner
b630949c2e do not set the root to null if an argument is dead
llvm-svn: 21188
2005-04-09 21:23:24 +00:00
Nate Begeman
dda6155d19 Add rlwnm instruction for variable rotate
Generate rotate left/right immediate
Generate code for brcondtwoway
Use new livein/liveout functionality

llvm-svn: 21187
2005-04-09 20:09:12 +00:00
Chris Lattner
72b1964108 Fix a crash on 173.applu by asking for a constant bigger than 32-bits.
llvm-svn: 21185
2005-04-09 19:47:21 +00:00
Chris Lattner
c97f9f403f Switch this instruction selector over to using liveins and liveouts, eliminating
implicit defs on entry to the function.  yaay :)

llvm-svn: 21184
2005-04-09 16:32:30 +00:00
Nate Begeman
98bcb13bfa Optimize FSEL a bit for fneg arguments. This fixes the recently added test
case so that we emit

_test_fneg_sel:
.LBB_test_fneg_sel_0:   ;
        fsel f1, f1, f3, f2
        blr

instead of:

_test_fneg_sel:
.LBB_test_fneg_sel_0:   ;
        fneg f0, f1
        fneg f0, f0
        fsel f1, f0, f3, f2
        blr

llvm-svn: 21177
2005-04-09 09:33:07 +00:00
Chris Lattner
c80baf5567 This target does not yet support ISD::BRCONDTWOWAY
llvm-svn: 21163
2005-04-09 03:22:30 +00:00
Nate Begeman
99fb6814bd 64b: Expand S/UREM
32b: No longer pattern match fneg(fsub(fmul)) as fnmsub
     Pattern match fsub a, mul(b, c) as fnmsub
     Pattern match fadd a, mul(b, c) as fmadd
Those changes speed up hydro2d by 2.5%, distray by 6%, and scimark by 8%

llvm-svn: 21161
2005-04-09 03:05:51 +00:00
Nate Begeman
95e1b860a1 Fix 64b shifts
llvm-svn: 21159
2005-04-08 23:45:01 +00:00
Nate Begeman
3fca499b8d Match Mac OS X 64 bit calling conventions
llvm-svn: 21157
2005-04-08 21:26:05 +00:00
Nate Begeman
6875356db1 Optimized code sequences for setcc reg, 0
Optimized code sequence for (a < 0) ? b : 0

llvm-svn: 21150
2005-04-07 20:30:01 +00:00
Chris Lattner
352dd3e579 PowerPC zero extends setcc results
llvm-svn: 21147
2005-04-07 19:41:49 +00:00
Nate Begeman
b890f32ac9 Pattern match bitfield insert, which helps shift long by immediate, among
other things.

llvm-svn: 21127
2005-04-06 23:51:40 +00:00
Nate Begeman
6c5e4c3bb1 Fix some shift bugs
llvm-svn: 21126
2005-04-06 22:42:08 +00:00
Nate Begeman
98251d6a1c Fixed version of optimized integer divide is now fixed. Calculate the
quotient, not the remainder.  Also, make sure to remove the old div operand
from the ExprMap and let SelectExpr insert the new one.

llvm-svn: 21111
2005-04-06 06:44:57 +00:00
Nate Begeman
aee0f81849 Turn off the div -> mul optimization until it works correctly 100% of the
time.

llvm-svn: 21105
2005-04-06 03:36:33 +00:00
Nate Begeman
b44597771c Add support for MULHS and MULHU nodes
Have LegalizeDAG handle SREM and UREM for us
Codegen SDIV and UDIV by constant as a multiply by magic constant instead
of integer divide, which is very slow.

llvm-svn: 21104
2005-04-06 00:25:27 +00:00
Nate Begeman
82ff41c342 Behold, rlwinm with certain immediate arguments is printed as the much more
readable slwi or srwi (shift left/right word immediate).

llvm-svn: 21099
2005-04-05 18:19:50 +00:00
Nate Begeman
581553fd21 Fix cut & paste errors (32->64), and codegen float->int more optimally.
llvm-svn: 21098
2005-04-05 17:32:30 +00:00
Nate Begeman
152dbbe856 Remove 64 bit simple ISel, it never worked correctly
Add initial (buggy) implementation of 64 bit pattern ISel

llvm-svn: 21096
2005-04-05 08:51:15 +00:00
Nate Begeman
a18a26f47c Back out the previous change to SelectBranchCC, since there are cases it
could miscompile.  A correct solution will be found in the near future.

llvm-svn: 21095
2005-04-05 04:32:16 +00:00
Nate Begeman
358dee806e Rename canUseAsImmediateForOpcode to getImmediateForOpcode to better
indicate that it is not a boolean function.
Properly emit the pseudo instruction for conditional branch, so that we
  can fix up conditional branches whose displacements are too large.
Reserve the right amount of opcode space for said pseudo instructions.

llvm-svn: 21094
2005-04-05 04:22:58 +00:00
Nate Begeman
ede4abc899 Implement SDIV by power of 2 as srawi/addze rather than load imm, divw
llvm-svn: 21091
2005-04-05 00:15:08 +00:00
Nate Begeman
00002553ba Pattern match fp mul-add, mul-sub, neg-mul-add, and neg-mul-sub
llvm-svn: 21090
2005-04-04 23:40:36 +00:00
Nate Begeman
682fd51f9c Add support for multiply-add, multiply-sub, and their negated versions
llvm-svn: 21089
2005-04-04 23:01:51 +00:00
Nate Begeman
d9af5c4fc5 Make sure that arg regs used by the call instruction are marked as such, so
that regalloc doesn't cleverly reuse early arg regs loading later arg regs.
This fixes almost all outstanding failures in the pattern isel.

llvm-svn: 21086
2005-04-04 22:17:48 +00:00
Nate Begeman
ce13bceb2a Remove unnecessary register copy now that regalloc is fixed
llvm-svn: 21085
2005-04-04 21:48:13 +00:00
Nate Begeman
bde3612ce3 i1 loads should also be from the low byte of the argument word.
llvm-svn: 21077
2005-04-04 09:09:00 +00:00
Nate Begeman
77427b1e77 Fix i64 return, fix CopyFromReg
llvm-svn: 21076
2005-04-04 06:52:38 +00:00
Nate Begeman
b2e5a962ff Full varargs support. All of UnitTests now passes
llvm-svn: 21070
2005-04-03 23:11:17 +00:00
Nate Begeman
1a5aaf6009 Pass the correct value for the chain to the store
llvm-svn: 21066
2005-04-03 22:22:56 +00:00
Nate Begeman
82d17d0e70 Fix SHL_PARTS
Start implementation of integer varargs

llvm-svn: 21065
2005-04-03 22:13:27 +00:00
Nate Begeman
127bd62534 Keeping up with the Joneses.
Implement not, nor, nand, and eqv

llvm-svn: 21060
2005-04-03 11:20:20 +00:00
Nate Begeman
402c04ff16 Set shift amount to Extend
Implement ISD::FABS and ISD::FNEG nodes
Implement SHL_PARTS, SRL_PARTS, and SRA_PARTS
Generate PowerPC 'fneg', 'fabs', and 'fnabs' instructions

llvm-svn: 21018
2005-04-02 05:59:34 +00:00
Chris Lattner
a5d4718875 This target doesn't support fabs/fneg yet.
llvm-svn: 21010
2005-04-02 05:03:24 +00:00
Nate Begeman
8d60ca616f Fix i64 returns
Generate PowerPC 'subfic' instruction when appropriate

llvm-svn: 20995
2005-04-02 00:42:16 +00:00
Nate Begeman
4034852ba9 Add ISD::UNDEF node
Teach the SelectionDAG code how to expand and promote it
Have PPC32 LowerCallTo generate ISD::UNDEF for int arg regs used up by fp
  arguments, but not shadowing their value.  This allows us to do the right
  thing with both fixed and vararg floating point arguments.

llvm-svn: 20988
2005-04-01 22:34:39 +00:00
Nate Begeman
244b36582a Fix Olden/bh, CR0 was being set in the wrong order
LowerCallTo and ISD::CALL are going to need to be modified, regs are being
set in the wrong order.

llvm-svn: 20981
2005-04-01 08:57:43 +00:00
Nate Begeman
f3ead25b68 Also apply Chris's fix to FP select and SETCC
llvm-svn: 20979
2005-04-01 07:21:30 +00:00
Chris Lattner
0cd0036523 Move the selection of the arms of the select operation up to the conditional
part to make sure we get the side effects and to avoid confusing the CFG.

llvm-svn: 20977
2005-04-01 07:10:02 +00:00
Nate Begeman
e82a2d7373 Fix stores to global addresses
Fix calls with no arguments

llvm-svn: 20975
2005-04-01 05:57:17 +00:00
Nate Begeman
9d224ae29b Support indexed loads and stores. This drops Shootout/matrix time from
18.8 to 14.8 seconds.  The Pattern ISel is now often faster than the
Simple ISel, esp. on memory intensive code.

llvm-svn: 20973
2005-04-01 04:45:11 +00:00
Nate Begeman
af7c6366d7 Implement FP_TO_SINT and FP_TO_UINT
llvm-svn: 20972
2005-04-01 02:59:27 +00:00
Nate Begeman
552f6f5f4e Add support for adding 0.0 and -0.0 to the constant pool, since we lie and
say that we support them, for the purposes of generating fsel instructions.

llvm-svn: 20970
2005-04-01 01:08:07 +00:00
Nate Begeman
18b3394f4d Factor out common code, support FP comparison in folded SetCC
llvm-svn: 20969
2005-04-01 00:32:34 +00:00
Nate Begeman
fc89059914 fsel generation for f32 and f64 select
generate compare immediate for integer compare with constant
fold setcc into branch
fold setcc into select

Code generation quality for Shootout is now on par with the Simple ISel

llvm-svn: 20968
2005-03-31 23:55:40 +00:00
Nate Begeman
17ff2b3a87 Pass the correct values to the chain argument for node construction during
LowerCallTo.
Handle ISD::ADD in SelectAddr, allowing us to have nonzero immediates for
loads and stores, amazing!

llvm-svn: 20946
2005-03-31 02:05:53 +00:00
Nate Begeman
de4aac1374 Rewrite LowerCallTo and Select(ISD::CALL) to properly handle float varargs
Tell the SelectionDAG ISel to expand SEXTLOAD of i1 and i8, rather than
  complicate the code in ISD::SEXTLOAD to do it by hand
Combine the FP and Int ISD::LOAD codegen
Generate better code for constant pool loads

As a result, all of Shootout, and likely many other programs are now
working.

llvm-svn: 20945
2005-03-31 00:15:26 +00:00
Nate Begeman
9c5480beeb Fix calls whose arguments fit entirely in registers to not break the Chain.
Implement SINT_TO_FP and UINT_TO_FP
Remove some dead code from the simple ISel

llvm-svn: 20944
2005-03-30 19:38:35 +00:00
Nate Begeman
c877844625 Fix frame index code to generate legal PowerPC instructions. About half of
Shootout now works.

llvm-svn: 20940
2005-03-30 02:23:08 +00:00
Nate Begeman
ec87399dac Fix external symbol printing in the AsmPrinter. Tell the ISel that we
don't support things like memcpy directly.  This allows a handful of the
Shootout programs to work, yay!

llvm-svn: 20939
2005-03-30 01:45:43 +00:00
Nate Begeman
8eddad3985 Fix BranchCC (it's still dumb), and implement FP select (also dumb)
llvm-svn: 20935
2005-03-29 22:48:55 +00:00
Nate Begeman
43b127ca0a Implement integer select and i1 sign extend
llvm-svn: 20934
2005-03-29 22:24:51 +00:00
Nate Begeman
d5d90ec76b Implement SetCC, fix ZERO_EXTEND_INREG
llvm-svn: 20933
2005-03-29 21:54:38 +00:00
Chris Lattner
3759d20b0f fix a warning in the optimized build
llvm-svn: 20920
2005-03-29 15:13:27 +00:00
Nate Begeman
62e458272f Implement div, rem, and frameindex
llvm-svn: 20907
2005-03-29 00:03:27 +00:00
Nate Begeman
734a61f057 Pattern ISel: fix argument loading for i64s (thanks chris)
Simple  ISel: fix i64 subtract

llvm-svn: 20903
2005-03-28 23:08:54 +00:00
Nate Begeman
32d1caae6d Remove fake instruction 'subc' (mnemonic for subfc).
More pattern isel updates

llvm-svn: 20902
2005-03-28 22:28:37 +00:00
Nate Begeman
2ab66f55b6 Implement proper loads and zero-extends of all types
llvm-svn: 20897
2005-03-28 19:36:43 +00:00
Nate Begeman
6b0fbf811f Fix that pesky floats in integer regs problem by assigning the f32 type to
the correct register class.  Also remove the loading of float data into int
regs part of varargs; it will need to be implemented differently later.

llvm-svn: 20857
2005-03-26 08:25:22 +00:00
Nate Begeman
31d175d1e5 Get closer to having varargs working. There's still something strange
going on with copies between floating point and integer register files
being generated.  Once that is solved, varargs will be done.

llvm-svn: 20856
2005-03-26 07:46:36 +00:00
Nate Begeman
69742e6ea1 Make 64bit args and float args work correct with calls. Thanks to Chris
for explaining EXTRACT_ELEMENT to me.

llvm-svn: 20847
2005-03-26 02:17:46 +00:00
Nate Begeman
d3b5925b38 Next round of pattern isel changes, mostly dealing with calls.
llvm-svn: 20841
2005-03-26 01:28:53 +00:00
Nate Begeman
4106e81966 Correct a documention link
llvm-svn: 20840
2005-03-26 01:28:05 +00:00
Nate Begeman
ba1cd37734 Support global addresses and fix call returns. Varargs still aren't
handled correctly for floating point arguments, or more than 8 arguemnts.
This does however, allow hello world to run.

llvm-svn: 20832
2005-03-25 08:34:25 +00:00
Nate Begeman
6b11098886 Implement next round of Pattern ISel fixes
1. void returns
2. multiplies
3. calls

llvm-svn: 20822
2005-03-24 23:35:30 +00:00
Nate Begeman
613e54d5f0 Fix an incorrect argument being passed to BuildMI for indirect calls.
llvm-svn: 20821
2005-03-24 23:34:38 +00:00
Nate Begeman
4584ca0554 Commit Gabor Greif's patch to use iterators in lowering intrinsics.
llvm-svn: 20816
2005-03-24 20:07:16 +00:00
Chris Lattner
ad07b1bc54 eliminate dead variables, patch contributed by Gabor Greif!
llvm-svn: 20812
2005-03-24 17:32:20 +00:00
Nate Begeman
833c1d0994 Implement more of the PPC32 Pattern ISel:
1) dynamic stack alloc
2) loads
3) shifts
4) subtract
5) immediate form of add, and, or, xor
6) change flag from -pattern-isel to -enable-ppc-pattern-isel

Remove dead arguments from getGlobalBaseReg in the simple ISel

llvm-svn: 20810
2005-03-24 06:28:42 +00:00
Chris Lattner
a42c4a0874 Fix silly "no newline at end of file" warning
llvm-svn: 20809
2005-03-24 06:16:18 +00:00