Chris Lattner
512b1d6c2a
Fix encodings
...
llvm-svn: 18164
2004-11-23 19:23:18 +00:00
Chris Lattner
cb15c858c2
Enumerate CR registers
...
llvm-svn: 18162
2004-11-23 18:59:59 +00:00
Chris Lattner
4cad3e8fbc
Initial implementation of exiting CompilationCallback
...
This should save all argument registers on entry and restore on exit, despite
that, simple things seem to work!!!
llvm-svn: 18161
2004-11-23 18:49:46 +00:00
Chris Lattner
141a71cf32
This method is dead
...
llvm-svn: 18160
2004-11-23 18:47:55 +00:00
Chris Lattner
9554912215
Remove this method.
...
llvm-svn: 18159
2004-11-23 18:47:42 +00:00
Chris Lattner
e8e62c5431
Squelch a bogus warning.
...
llvm-svn: 18156
2004-11-23 15:56:38 +00:00
Nate Begeman
f096183b46
Don't return value from void function. This is only temporary anyway while
...
the JIT is made to work!
llvm-svn: 18155
2004-11-23 10:04:49 +00:00
Chris Lattner
b8eb5dabd7
Fix a minor bug
...
llvm-svn: 18153
2004-11-23 06:56:31 +00:00
Chris Lattner
30c5ade43e
Be really paranoid about not breaking stuff yet
...
llvm-svn: 18152
2004-11-23 06:56:18 +00:00
Chris Lattner
8bb3fbffa3
Implement the first hunk of CompilationCallback. The pieces missing are the
...
ones noted, which require funny PPC specific inline assembly.
If some angel felt the desire to help me, I think this is that last bit missing
for JIT support (however, generic code emitter might night work right with
the constant pool yet).
llvm-svn: 18151
2004-11-23 06:55:05 +00:00
Chris Lattner
ec9138be44
Implement the stub needed to get into compilation callback.
...
llvm-svn: 18147
2004-11-23 06:27:02 +00:00
Chris Lattner
5ac6f7a36d
Simplify code a bit
...
llvm-svn: 18146
2004-11-23 06:05:44 +00:00
Chris Lattner
37a72a9ef2
Initial implementation of the JIT interfaces. Relocation is done and stubs
...
for external functions work. CompilationCallback has not been written, and
stubs for internal functions are not generated yet. This means you can call
printf and exit, and use global variables, but cannot call functions local to
a module yet.
llvm-svn: 18145
2004-11-23 06:02:06 +00:00
Chris Lattner
2f47d181d8
Emit relocations for the global variable using instructions. This gets us
...
LA, LOADHiAddr, CALLpcrel, and MovePCtoLR working, though the constant pool
probably is not right.
llvm-svn: 18144
2004-11-23 05:59:53 +00:00
Chris Lattner
17d87ca91f
Implement all of the methods
...
llvm-svn: 18142
2004-11-23 05:57:57 +00:00
Chris Lattner
068ade1373
Initial checkin of the 32-bit PPC relocation types
...
llvm-svn: 18141
2004-11-23 05:57:38 +00:00
Chris Lattner
e74f5f8a4e
Move JITInfo from PPCTM to PPC32TM
...
llvm-svn: 18140
2004-11-23 05:56:40 +00:00
Chris Lattner
8e3800acc9
Do not provide the non-specialized PowerPCJITInfo object, it is pretty useless.
...
Instead, let derived classes provide specialized ones.
llvm-svn: 18139
2004-11-23 05:55:38 +00:00
Chris Lattner
1b163867c6
LA is really addi. Be consistent with operand ordering to avoid confusing the code emitter
...
llvm-svn: 18138
2004-11-23 05:54:25 +00:00
Chris Lattner
3e3ba3b1cf
Remove some dead code
...
llvm-svn: 18136
2004-11-22 23:07:22 +00:00
Chris Lattner
5b68bdb2ce
Comment out a couple of unused instructions.
...
llvm-svn: 18135
2004-11-22 23:07:01 +00:00
Chris Lattner
a020fc1650
Disable this.
...
llvm-svn: 18130
2004-11-22 21:51:40 +00:00
Chris Lattner
bab8204396
This chunk of code needs to be rewritten
...
llvm-svn: 18127
2004-11-22 21:45:54 +00:00
Nate Begeman
7ec36ad70f
Fix Shootout-C++/wc, which was broken by my recent changes to emit fewer
...
reg-reg copies. The necessary conditions for this bug are a GEP that is
used outside the basic block in which it is defined, whose components
other than the pointer are all constant zero, and where the use is
selected before the definition (backwards branch to successsor block).
llvm-svn: 18084
2004-11-21 05:14:06 +00:00
Chris Lattner
3e3645938e
ignore generated files.
...
llvm-svn: 18072
2004-11-21 00:00:54 +00:00
Chris Lattner
3ff7bafe17
Remove this method, it's not clear how it could be implemented indep of 32 or 64-bit mode
...
llvm-svn: 18038
2004-11-20 04:17:17 +00:00
Chris Lattner
e3461cf0bc
getJITStubForFunction is optional and unimplemented, just remove it.
...
llvm-svn: 18036
2004-11-20 04:14:44 +00:00
Nate Begeman
83cded0ecb
Eliminate another 6k register copies that the register allocator would just
...
coalesce out of hbd. Speeds up compilation by 2% (0.6s)
llvm-svn: 17987
2004-11-19 08:01:16 +00:00
Nate Begeman
de1fd6a162
Generate fewer reg-reg copies for the register allocator to deal with.
...
This eliminates over 2000 in hbd alone.
llvm-svn: 17973
2004-11-19 02:06:40 +00:00
Nate Begeman
567d30174a
Eliminate another common source of moves that the register allocator
...
shouldn't be forced to coalesce for us: folded GEP operations. This too
fires thousands of times across the testsuite.
llvm-svn: 17947
2004-11-18 07:22:46 +00:00
Nate Begeman
3e1aaef2b5
When accessing the base register for global variables, use the register
...
directly rather than making a copy for the register allocator to coalesce.
This kills thousands of live intervals across the testsuite.
llvm-svn: 17946
2004-11-18 06:51:29 +00:00
Nate Begeman
7e254235e2
Clean up and fix cast codegen by removing cases that are handled elsewhere,
...
and properly emitting signed short to unsigned int. This fixes the last
regression vs. the CBE, MultiSource/Applications/hbd.
llvm-svn: 17942
2004-11-18 04:56:53 +00:00
Chris Lattner
c13149e03e
Simplify namespaces
...
llvm-svn: 17870
2004-11-16 04:47:33 +00:00
Misha Brukman
757502af07
Add BCTR and LWZU instruction opcodes
...
llvm-svn: 17851
2004-11-15 21:20:09 +00:00
Misha Brukman
0d900050be
Handle GhostLinkage (should not ever reach the assembly printing stage!)
...
llvm-svn: 17749
2004-11-14 21:03:30 +00:00
Misha Brukman
c98cd22aae
Fix build on Linux/PowerPC64 using SuSE GCC (#undef PPC)
...
llvm-svn: 17744
2004-11-14 20:34:01 +00:00
Nate Begeman
398bd2b9f6
Allow hbd to be bugpointable on darwin by fixing common and linkonce codegen
...
llvm-svn: 17637
2004-11-09 04:01:18 +00:00
Nate Begeman
a0c15f3ffd
Put int the getReg cast optimization from x86 so that we generate fewer
...
move instructions for the register allocator to coalesce.
llvm-svn: 17608
2004-11-08 02:25:40 +00:00
Nate Begeman
a7541b19fc
Disable bogus cast elimination when the cast is used by a setcc instruction.
...
llvm-svn: 17583
2004-11-07 20:23:42 +00:00
Nate Begeman
bc8bc24d28
Thanks to sabre for pointing out that we were incorrectly codegen'ing
...
int test(int x) { return 32768 - x; }
Fixed by teaching the function that checks a constant's validity to be used
as an immediate argument about subtract-from instructions.
llvm-svn: 17476
2004-11-04 19:43:18 +00:00
Reid Spencer
d3f7233495
Change Library Names Not To Conflict With Others When Installed
...
llvm-svn: 17286
2004-10-27 23:18:45 +00:00
Nate Begeman
46c3a8875f
Remove file that is no longer used, and move include of MRegisterInfo.h
...
from PowerPCFrameInfo.h to PowerPCAsmPrinter.cpp where it is actually
needed.
llvm-svn: 17244
2004-10-26 06:02:38 +00:00
Nate Begeman
7c3c97af10
Eliminate usage of MRegisterInfo::getRegClass(physreg)
...
llvm-svn: 17240
2004-10-26 05:40:45 +00:00
Nate Begeman
ae98298003
Update to-do list
...
llvm-svn: 17235
2004-10-26 04:10:53 +00:00
Nate Begeman
113f516f6b
Fix treecc. Also fix a latent bug in emitBinaryConstOperation that would
...
allow and const, 0 to be incorrectly codegen'd into a rlwinm instruction.
llvm-svn: 17234
2004-10-26 03:48:25 +00:00
Chris Lattner
9c356da87d
Disable the JIT until it can sorta kinda work.
...
llvm-svn: 17230
2004-10-25 20:53:41 +00:00
Nate Begeman
4b5ed899fd
Implement more complete and correct codegen for bitfield inserts, as tested
...
by the recently committed rlwimi.ll test file. Also commit initial code
for bitfield extract, although it is turned off until fully debugged.
llvm-svn: 17207
2004-10-24 10:33:30 +00:00
Misha Brukman
f8bd6fc901
* Correctly handle the MovePCtoLR pseudo-instr with a bl to next instr
...
* Stop the confusion of using rv and Addr for global addresses: just use rv
llvm-svn: 17195
2004-10-23 23:47:34 +00:00
Misha Brukman
58d9e43fa1
Add BA, BL, and BLA opcodes
...
llvm-svn: 17193
2004-10-23 20:29:24 +00:00
Misha Brukman
0342392149
* Do not emit IMPLICIT_DEF pseudo-instructions
...
* Convert register numbers from their opcode value to the real value, e.g.
PPC::R1 => 1 and PPC::F1 => 1
* Add correct handling of loading of global values which are PC-relative --
implement ha16() and lo16()
llvm-svn: 17190
2004-10-23 18:28:01 +00:00
Misha Brukman
bd6a01c3ef
DForm_1, particularly used by store instructions, needs the immediate operand to
...
be listed second as that is how the instructions are usually created (and is the
correct asm syntax) so that it's assembled correctly from its constituents
llvm-svn: 17183
2004-10-23 06:08:38 +00:00
Misha Brukman
e4ae05e099
Fix the SPR field for MTLR, MFLR, MTCTR, and MFCTR instructions.
...
The decimal value given in the manual (8 or 9) really needs to be multiplied by
a factor of 32 because of the group of 5 zero bits after the register code.
llvm-svn: 17182
2004-10-23 06:05:49 +00:00
Misha Brukman
5cea06807d
The value of the XO field for MFLR and MFCTR is 339, not 399
...
llvm-svn: 17181
2004-10-23 05:38:55 +00:00
Misha Brukman
39d23c81d4
Remove extraneous blank line
...
llvm-svn: 17180
2004-10-23 04:59:22 +00:00
Misha Brukman
c660c6c514
Align function arguments in function headers
...
llvm-svn: 17178
2004-10-23 04:58:32 +00:00
Nate Begeman
91ef127999
Kill casts from integer types to unsigned byte, when the cast was only used
...
as the shift amount operand to a shift instruction. This was causing us to
emit unnecessary clear operations for code such as:
int foo(int x) { return 1 << x; }
llvm-svn: 17175
2004-10-23 00:50:23 +00:00
Reid Spencer
019621a1ea
Adjust to changes in Makefile.rules
...
llvm-svn: 17167
2004-10-22 21:02:08 +00:00
Reid Spencer
e48ba34fd4
We won't use automake
...
llvm-svn: 17155
2004-10-22 03:35:04 +00:00
Misha Brukman
66a092f3df
Remove debug code emitter from the JIT
...
llvm-svn: 17151
2004-10-21 03:07:38 +00:00
Alkis Evlogimenos
67449982b8
Make this compile.
...
llvm-svn: 17150
2004-10-21 02:44:16 +00:00
Misha Brukman
9514a75e36
* Added basic support for JITing functions, basic blocks, instruction encoding,
...
including registers, constants, and partial support for global addresses
* The JIT is disabled by default to allow building llvm-gcc, which wants to test
running programs during configure
llvm-svn: 17149
2004-10-21 01:42:02 +00:00
Nate Begeman
d7cbf1d28e
Don't clear or sign extend bool->int. This fires a few dozen times on the test suite
...
llvm-svn: 17147
2004-10-20 21:55:41 +00:00
Reid Spencer
ce514b1c2c
Initial automake generated Makefile template
...
llvm-svn: 17136
2004-10-18 23:55:41 +00:00
Nate Begeman
1c408f7319
Generate correct stubs for weak-linked symbols
...
llvm-svn: 17101
2004-10-17 23:01:34 +00:00
Reid Spencer
9a97056275
PPC32GenCodeEmitter instead of PowerPCGenCodeEmitter
...
llvm-svn: 17087
2004-10-17 14:59:38 +00:00
Nate Begeman
f9aac7846c
Implement bitfield insert by recognizing the following pattern:
...
1. optional shift left
2. and x, immX
3. and y, immY
4. or z, x, y
==> rlwimi z, x, y, shift, mask begin, mask end
where immX == ~immY and immX is a run of set bits. This transformation
fires 32 times on voronoi, once on espresso, and probably several
dozen times on external benchmarks such as gcc.
To put this in terms of actual code generated for
struct B { unsigned a : 3; unsigned b : 2; };
void storeA (struct B *b, int v) { b->a = v;}
void storeB (struct B *b, int v) { b->b = v;}
Old:
_storeA:
rlwinm r2, r4, 0, 29, 31
lwz r4, 0(r3)
rlwinm r4, r4, 0, 0, 28
or r2, r4, r2
stw r2, 0(r3)
blr
_storeB:
rlwinm r2, r4, 3, 0, 28
rlwinm r2, r2, 0, 27, 28
lwz r4, 0(r3)
rlwinm r4, r4, 0, 29, 26
or r2, r2, r4
stw r2, 0(r3)
blr
New:
_storeA:
lwz r2, 0(r3)
rlwimi r2, r4, 0, 29, 31
stw r2, 0(r3)
blr
_storeB:
lwz r2, 0(r3)
rlwimi r2, r4, 3, 27, 28
stw r2, 0(r3)
blr
llvm-svn: 17078
2004-10-17 05:19:20 +00:00
Nate Begeman
d4c970aa3d
Finally fix one of the oldest FIXMEs in the PowerPC backend: correctly
...
flag rotate left word immediate then mask insert (rlwimi) as a two-address
instruction, and update the ISel usage of the instruction accordingly.
This will allow us to properly schedule rlwimi, and use it to efficiently
codegen bitfield operations.
llvm-svn: 17068
2004-10-16 20:43:38 +00:00
Chris Lattner
3662abfd5a
ADd support for undef and unreachable
...
llvm-svn: 17050
2004-10-16 18:13:47 +00:00
Nate Begeman
d8183bd297
Better codegen of binary integer ops with 32 bit immediate operands.
...
This transformation fires a few dozen times across the testsuite.
For example, int test2(int X) { return X ^ 0x0FF00FF0; }
Old:
_test2:
lis r2, 4080
ori r2, r2, 4080
xor r3, r3, r2
blr
New:
_test2:
xoris r3, r3, 4080
xori r3, r3, 4080
blr
llvm-svn: 17004
2004-10-15 00:50:19 +00:00
Misha Brukman
66261f021d
* Claim to support machine code emission - return false from
...
addPassesToEmitMachineCode()
* Add support for registers and constants in getMachineOpValue()
This enables running "int main() { ret 0 }" via the PowerPC JIT.
llvm-svn: 16983
2004-10-14 06:39:56 +00:00
Misha Brukman
cb4130c28c
* Include the real (generated) version of getBinaryCodeForInstr()
...
* Add implementation of getMachineOpValue() for generated code emitter
* Convert assert()s in unimplemented functions to abort()s so that non-debug
builds fail predictably
* Add file header comments
llvm-svn: 16981
2004-10-14 06:07:25 +00:00
Misha Brukman
11d1764f74
* Make a PPC32-specific code emitter because we have separate classes for 32-
...
and 64-bit code emitters that cannot share code unless we use virtual
functions
* Identify components being built by tablegen with more detail by assigning them
to PowerPC, PPC32, or PPC64 more specifically; also avoids seeing 'building
PowerPC XYZ' messages twice, where one is for PPC32 and one for PPC64
llvm-svn: 16980
2004-10-14 06:04:56 +00:00
Misha Brukman
5e8bfd0675
There is only one field in an instruction, and that is `Inst', the final view of
...
the instruction binary format, all others are simply operands and should not
have the `field' label
llvm-svn: 16978
2004-10-14 05:55:37 +00:00
Misha Brukman
47c2236ae9
PowerPC instruction definitions use LittleEndian-style encoding [0..31]
...
llvm-svn: 16977
2004-10-14 05:54:38 +00:00
Reid Spencer
e6418ec30f
Update to reflect changes in Makefile rules.
...
llvm-svn: 16950
2004-10-13 11:46:52 +00:00
Reid Spencer
1b7459b29d
Initial version of automake Makefile.am file.
...
llvm-svn: 16893
2004-10-10 22:20:40 +00:00
Chris Lattner
6ff0fd4837
bling bling!
...
llvm-svn: 16873
2004-10-10 16:26:13 +00:00
Nate Begeman
dfefd2f3fc
Implement logical and with an immediate that consists of a contiguous block
...
of one or more 1 bits (may wrap from least significant bit to most
significant bit) as the rlwinm rather than andi., andis., or some longer
instructons sequence.
int andn4(int z) { return z & -4; }
int clearhi(int z) { return z & 0x0000FFFF; }
int clearlo(int z) { return z & 0xFFFF0000; }
int clearmid(int z) { return z & 0x00FFFF00; }
int clearwrap(int z) { return z & 0xFF0000FF; }
_andn4:
rlwinm r3, r3, 0, 0, 29
blr
_clearhi:
rlwinm r3, r3, 0, 16, 31
blr
_clearlo:
rlwinm r3, r3, 0, 0, 15
blr
_clearmid:
rlwinm r3, r3, 0, 8, 23
blr
_clearwrap:
rlwinm r3, r3, 0, 24, 7
blr
llvm-svn: 16832
2004-10-08 02:49:24 +00:00
Nate Begeman
370b1b7a9a
Several fixes and enhancements to the PPC32 backend.
...
1. Fix an illegal argument to getClassB when deciding whether or not to
sign extend a byte load.
2. Initial addition of isLoad and isStore flags to the instruction .td file
for eventual use in a scheduler.
3. Rewrite of how constants are handled in emitSimpleBinaryOperation so
that we can emit the PowerPC shifted immediate instructions far more
often. This allows us to emit the following code:
int foo(int x) { return x | 0x00F0000; }
_foo:
.LBB_foo_0: ; entry
; IMPLICIT_DEF
oris r3, r3, 15
blr
llvm-svn: 16826
2004-10-07 22:30:03 +00:00
Nate Begeman
76d2a77998
Add ori reg, reg, 0 as a move instruction. This can be generated from
...
loading a 32bit constant into a register whose low halfword is all zeroes.
We now omit the ori after the lis for the following C code:
int bar(int y) { return y * 0x00F0000; }
_bar:
.LBB_bar_0: ; entry
; IMPLICIT_DEF
lis r2, 15
mullw r3, r3, r2
blr
llvm-svn: 16825
2004-10-07 22:26:12 +00:00
Nate Begeman
f60feea650
Remove unnecessary header include
...
llvm-svn: 16824
2004-10-07 22:24:32 +00:00
Chris Lattner
38fbf09104
Correct some typeos
...
llvm-svn: 16770
2004-10-06 16:28:24 +00:00
Nate Begeman
79d42a185e
Turning on fsel code gen now that we can do so would be good.
...
llvm-svn: 16765
2004-10-06 11:03:30 +00:00
Nate Begeman
7b4fe83ba8
Implement floating point select for lt, gt, le, ge using the powerpc fsel
...
instruction.
Now, rather than emitting the following loop out of bisect:
.LBB_main_19: ; no_exit.0.i
rlwinm r3, r2, 3, 0, 28
lfdx f1, r3, r27
addis r3, r30, ha16(.CPI_main_1-"L00000$pb")
lfd f2, lo16(.CPI_main_1-"L00000$pb")(r3)
fsub f2, f2, f1
addis r3, r30, ha16(.CPI_main_1-"L00000$pb")
lfd f4, lo16(.CPI_main_1-"L00000$pb")(r3)
fcmpu cr0, f1, f4
bge .LBB_main_64 ; no_exit.0.i
.LBB_main_63: ; no_exit.0.i
b .LBB_main_65 ; no_exit.0.i
.LBB_main_64: ; no_exit.0.i
fmr f2, f1
.LBB_main_65: ; no_exit.0.i
addi r3, r2, 1
rlwinm r3, r3, 3, 0, 28
lfdx f1, r3, r27
addis r3, r30, ha16(.CPI_main_1-"L00000$pb")
lfd f4, lo16(.CPI_main_1-"L00000$pb")(r3)
fsub f4, f4, f1
addis r3, r30, ha16(.CPI_main_1-"L00000$pb")
lfd f5, lo16(.CPI_main_1-"L00000$pb")(r3)
fcmpu cr0, f1, f5
bge .LBB_main_67 ; no_exit.0.i
.LBB_main_66: ; no_exit.0.i
b .LBB_main_68 ; no_exit.0.i
.LBB_main_67: ; no_exit.0.i
fmr f4, f1
.LBB_main_68: ; no_exit.0.i
fadd f1, f2, f4
addis r3, r30, ha16(.CPI_main_2-"L00000$pb")
lfd f2, lo16(.CPI_main_2-"L00000$pb")(r3)
fmul f1, f1, f2
rlwinm r3, r2, 3, 0, 28
lfdx f2, r3, r28
fadd f4, f2, f1
fcmpu cr0, f4, f0
bgt .LBB_main_70 ; no_exit.0.i
.LBB_main_69: ; no_exit.0.i
b .LBB_main_71 ; no_exit.0.i
.LBB_main_70: ; no_exit.0.i
fmr f0, f4
.LBB_main_71: ; no_exit.0.i
fsub f1, f2, f1
addi r2, r2, -1
fcmpu cr0, f1, f3
blt .LBB_main_73 ; no_exit.0.i
.LBB_main_72: ; no_exit.0.i
b .LBB_main_74 ; no_exit.0.i
.LBB_main_73: ; no_exit.0.i
fmr f3, f1
.LBB_main_74: ; no_exit.0.i
cmpwi cr0, r2, -1
fmr f16, f0
fmr f17, f3
bgt .LBB_main_19 ; no_exit.0.i
We emit this instead:
.LBB_main_19: ; no_exit.0.i
rlwinm r3, r2, 3, 0, 28
lfdx f1, r3, r27
addis r3, r30, ha16(.CPI_main_1-"L00000$pb")
lfd f2, lo16(.CPI_main_1-"L00000$pb")(r3)
fsub f2, f2, f1
fsel f1, f1, f1, f2
addi r3, r2, 1
rlwinm r3, r3, 3, 0, 28
lfdx f2, r3, r27
addis r3, r30, ha16(.CPI_main_1-"L00000$pb")
lfd f4, lo16(.CPI_main_1-"L00000$pb")(r3)
fsub f4, f4, f2
fsel f2, f2, f2, f4
fadd f1, f1, f2
addis r3, r30, ha16(.CPI_main_2-"L00000$pb")
lfd f2, lo16(.CPI_main_2-"L00000$pb")(r3)
fmul f1, f1, f2
rlwinm r3, r2, 3, 0, 28
lfdx f2, r3, r28
fadd f4, f2, f1
fsub f5, f0, f4
fsel f0, f5, f0, f4
fsub f1, f2, f1
addi r2, r2, -1
fsub f2, f1, f3
fsel f3, f2, f3, f1
cmpwi cr0, r2, -1
fmr f16, f0
fmr f17, f3
bgt .LBB_main_19 ; no_exit.0.i
llvm-svn: 16764
2004-10-06 09:53:04 +00:00
Nate Begeman
65376f660e
Generate better code by being far less clever when it comes to the select instruction. Don't create overlapping register lifetimes
...
llvm-svn: 16580
2004-09-29 05:00:31 +00:00
Nate Begeman
a8b079e16a
improve Type::BoolTy codegen by eliminating unnecessary clears and sign extends
...
llvm-svn: 16578
2004-09-29 03:45:33 +00:00
Nate Begeman
dc50ea0d82
To go along with sabre's improved InstCombining, improve recognition of
...
integers that we can use as immediate values in instructions.
Example from yacr2:
- lis r10, -1
- ori r10, r10, 65535
- add r28, r28, r10
+ addi r28, r28, -1
addi r7, r7, 1
addi r9, r9, 1
b .LBB_main_9 ; loopentry.1.i214
llvm-svn: 16566
2004-09-29 02:35:05 +00:00
Nate Begeman
921a44443d
Correct some BuildMI arguments for the upcoming simple scheduler
...
llvm-svn: 16519
2004-09-27 05:08:17 +00:00
Nate Begeman
75f0d35dc6
Fix the last of the major PPC GEP folding deficiencies. This will allow
...
the ISel to use indexed and non-zero immediate offsets for GEPs that have
more than one use. This is common for instruction sequences such as a load
followed by a modify and store to the same address.
llvm-svn: 16493
2004-09-23 05:31:33 +00:00
Nate Begeman
61d1797c03
add optimized code sequences for setcc x, 0
...
llvm-svn: 16478
2004-09-22 04:40:25 +00:00
Misha Brukman
bd9f406b0b
s/ISel/PPC64ISel/ to have unique class names for debugging via gdb because the
...
C++ front-end in gcc does not mangle classes in anonymous namespaces correctly.
llvm-svn: 16471
2004-09-21 18:22:33 +00:00
Misha Brukman
6ad6dd2ab9
s/ISel/PPC32ISel/ to have unique class names for debugging via gdb because the
...
C++ front-end in gcc does not mangle classes in anonymous namespaces correctly.
llvm-svn: 16470
2004-09-21 18:22:19 +00:00
Chris Lattner
aee36bb527
Revamp the Register class, and allow the use of the RegisterGroup class to
...
specify aliases directly in register definitions.
Patch contributed by Jason Eckhardt!
llvm-svn: 16330
2004-09-14 04:17:02 +00:00
Nate Begeman
ce6d62eac7
Add 64 bit divide instructions, and use them
...
llvm-svn: 16198
2004-09-06 18:46:59 +00:00
Misha Brukman
8e6e187922
* Change PPC32AsmPrinter => PowerPCAsmPrinter since it is now shared between
...
Darwin and AIX and is not 32- or 64-bit specific
* Bring back PowerPC.td as a result, to make it use the `PowerPC' class name
* Adjust Makefile accordingly
llvm-svn: 16174
2004-09-05 02:42:44 +00:00
Misha Brukman
f55a7b3afa
Renamed PPC32AsmPrinter.cpp => PowerPCAsmPrinter.cpp as the Darwin and AIX asm
...
printers are now unified into one file.
llvm-svn: 16173
2004-09-05 02:27:37 +00:00
Nate Begeman
56a134d07a
Include MathExtras.h to fix build breakage, thanks to Vladimir
...
llvm-svn: 16164
2004-09-04 14:51:26 +00:00
Nate Begeman
e816600b3e
All PPC instructions are now auto-printed
...
32 and 64 bit AsmWriters unified
Darwin and AIX specific features of AsmWriter split out
llvm-svn: 16163
2004-09-04 05:00:00 +00:00
Nate Begeman
3bad485eec
Convert remaining X-Form and Pseudo instructions over to asm writer
...
llvm-svn: 16142
2004-09-02 08:13:00 +00:00
Reid Spencer
c4abcbefb1
Changes For Bug 352
...
Move include/Config and include/Support into include/llvm/Config,
include/llvm/ADT and include/llvm/Support. From here on out, all LLVM
public header files must be under include/llvm/.
llvm-svn: 16137
2004-09-01 22:55:40 +00:00
Nate Begeman
220175aa4d
convert M and MD form instructions to generated asm writer
...
llvm-svn: 16121
2004-08-31 02:28:08 +00:00
Nate Begeman
e58512a61c
Move yet more instructions over to being printed by the generated asm writer
...
llvm-svn: 16112
2004-08-30 02:28:06 +00:00
Nate Begeman
7792aa1f8b
Convert A-Form instructions to auto-generated asm writer
...
llvm-svn: 16107
2004-08-29 22:45:13 +00:00
Nate Begeman
68e2dd66af
Improvements to int->float cast code for PPC-64
...
llvm-svn: 16105
2004-08-29 22:02:43 +00:00
Nate Begeman
923af3763d
Implement the following missing functionality in the PPC backend:
...
cast fp->bool
cast ulong->fp
algebraic right shift long by non-constant value
These changes tested across most of the test suite. Fixes Regression/casts
llvm-svn: 16081
2004-08-29 08:19:32 +00:00
Nate Begeman
c0e42be976
Register sizes are in bits, not bytes
...
llvm-svn: 16070
2004-08-27 04:28:10 +00:00
Nate Begeman
0069f07741
Kill a majority of unnecessary sign extensions for byte loads
...
llvm-svn: 15991
2004-08-22 08:10:15 +00:00
Nate Begeman
72ec463dc7
Don't hard code the offset of the saved R31 in functions with frame pointers
...
llvm-svn: 15990
2004-08-22 08:09:17 +00:00
Nate Begeman
e6aace2ecb
Back out branchless SetCC code. While it helped a lot in some cases, it
...
hurt a lot in others. Instead, improve branching version of SetCC and
Select instructions. The old code will be in CVS should we ever need to
dig it up again.
llvm-svn: 15979
2004-08-21 20:42:14 +00:00
Chris Lattner
15593f74c1
Switch from bytes to bits for alignment.
...
Also, change GPRC for PPC32 to align on 32-bit boundary instead of 64-bit
llvm-svn: 15975
2004-08-21 20:14:40 +00:00
Chris Lattner
db3e26f50a
Reduce uses of getRegClass
...
llvm-svn: 15968
2004-08-21 19:51:17 +00:00
Chris Lattner
23a0219a11
Fix warning
...
llvm-svn: 15964
2004-08-21 19:11:03 +00:00
Nate Begeman
dd700ce5e4
Move XForm instructions over to the auto-generated asm writer
...
llvm-svn: 15962
2004-08-21 05:56:39 +00:00
Nate Begeman
6c4bd28dc1
remove some things from the todo list.
...
llvm-svn: 15956
2004-08-20 18:46:54 +00:00
Chris Lattner
cd2b92c36e
Do not register ppc64 yet, as it breaks the SparcV9 backend
...
llvm-svn: 15955
2004-08-20 18:09:18 +00:00
Nate Begeman
2f68d05d47
Implement code to convert SetCC into straight line code where appropriate. Add necessary instructions for this transformation to the .td file.
...
llvm-svn: 15952
2004-08-20 09:56:22 +00:00
Misha Brukman
8bfcf0d2e9
Fix opcodes being printed in caps (the more general fix may be `AsmWriter')
...
llvm-svn: 15932
2004-08-19 21:56:12 +00:00
Misha Brukman
1bdac3b68d
Stack space for argument passing is 32 regardless of 32- vs. 64-bit arch.
...
Thanks to Nate Begeman for pointing this out.
llvm-svn: 15930
2004-08-19 21:51:19 +00:00
Misha Brukman
70f027b623
LR needs to be saved at 16-byte offset on a 64-bit arch
...
llvm-svn: 15929
2004-08-19 21:36:14 +00:00
Misha Brukman
2c3423694a
On 64-bit PowerPC, pointers are 8 bytes, so parameter area offset is 48, not 24
...
llvm-svn: 15928
2004-08-19 21:34:05 +00:00
Misha Brukman
21df6f6757
This PHI has 4 additional operands, not 2.
...
llvm-svn: 15926
2004-08-19 21:00:12 +00:00
Misha Brukman
e438dc224e
Use the appropriate 64-bit register description file.
...
llvm-svn: 15922
2004-08-19 19:36:57 +00:00
Misha Brukman
ffaa056155
Fix more remaining 32-bit vestiges of PowerPC
...
llvm-svn: 15919
2004-08-19 18:49:58 +00:00
Misha Brukman
409030d6b4
Fix another vestige of the 32-bit PowerPC backend.
...
llvm-svn: 15918
2004-08-19 16:50:30 +00:00
Misha Brukman
9ec6a58d15
Correct character prepended to global symbols ('.'), use Mangler consistently
...
llvm-svn: 15917
2004-08-19 16:33:56 +00:00
Misha Brukman
b2f68d6752
* Eliminate global base register, r2 is used for that on AIX/PowerPC
...
* Fix bug from 32-bit PowerPC days of 2-register long split
llvm-svn: 15916
2004-08-19 16:29:25 +00:00
Misha Brukman
7a0735b46b
Wrap long lines.
...
llvm-svn: 15915
2004-08-19 16:28:30 +00:00
Nate Begeman
0975cdde75
Convert casts that will have no effect into move instructions.
...
llvm-svn: 15914
2004-08-19 08:07:50 +00:00
Nate Begeman
81c97654da
Clean up floating point instruction selection.
...
Change int->float cast code to put conversion constants in constant pool.
Shorten code sequence for constant pool fp loads.
Remove LOADLoDirect/LOADLoIndirect psuedo instructions and tweak asmwriter
llvm-svn: 15913
2004-08-19 05:20:54 +00:00
Chris Lattner
8c5096d223
Rename var
...
llvm-svn: 15897
2004-08-18 02:22:55 +00:00
Misha Brukman
631bd1c155
This file is no longer used.
...
llvm-svn: 15893
2004-08-17 20:23:33 +00:00
Chris Lattner
8b5695de66
Start using alignment output routines from AsmPrinter.
...
Changes to make this more similar to the X86 asmprinter
Fix overalignment of globals.
llvm-svn: 15891
2004-08-17 19:26:03 +00:00
Chris Lattner
7ab985b9a2
Print comments with ;
...
llvm-svn: 15881
2004-08-17 16:27:26 +00:00
Nate Begeman
ca0ea7b9ba
Re-fix hiding the Frame Pointer from the register allocator in functions
...
that have a frame pointer. This change fixes Burg. In addition, make
the necessary changes to floating point code gen and constant loading after
Chris Lattner's fixes to the asm writer. These changes fix MallocBench/gs
llvm-svn: 15873
2004-08-17 07:17:44 +00:00
Chris Lattner
2e24f55588
Use the emitGlobalConstant defined in AsmPrinter
...
llvm-svn: 15869
2004-08-17 06:37:12 +00:00
Chris Lattner
3bc964c8fb
New, more general, interface.
...
llvm-svn: 15866
2004-08-17 06:07:43 +00:00
Misha Brukman
4434e4ce05
Rewrite targets/rules to generate files for just PowerPC or PPC{32,64}
...
llvm-svn: 15862
2004-08-17 05:11:54 +00:00
Misha Brukman
35826543f8
Register classes are target-dependent
...
llvm-svn: 15861
2004-08-17 05:10:31 +00:00
Misha Brukman
47fc7a5955
#include <map> is not necessary here
...
llvm-svn: 15860
2004-08-17 05:09:39 +00:00
Misha Brukman
c358f5b8ef
`PowerPC' is no longer a real target
...
llvm-svn: 15859
2004-08-17 05:09:10 +00:00
Misha Brukman
a73414f1da
Move variables and methods which need PPC{32,64}* distinction to subclasses
...
llvm-svn: 15858
2004-08-17 05:08:44 +00:00
Misha Brukman
17c41c8bed
No need for an `is64bit' flag
...
llvm-svn: 15857
2004-08-17 05:06:47 +00:00
Misha Brukman
471143bc94
PowerPCInstrInfo and PowerPCRegisterInfo have gone away; they are replaced
...
by 32- and 64-bit customized files, named appropriately.
llvm-svn: 15856
2004-08-17 05:05:00 +00:00
Misha Brukman
d5acc2ec78
Consistently name passed with 32 or 64 in their name
...
llvm-svn: 15855
2004-08-17 05:02:58 +00:00
Misha Brukman
52079a6264
PowerPCRegisterInfo no longer takes a bool to differentiate 32 vs 64 bits
...
llvm-svn: 15854
2004-08-17 05:02:18 +00:00
Misha Brukman
5e14dba4fa
The PowerPCInstrInfo class has gone away.
...
llvm-svn: 15853
2004-08-17 05:00:46 +00:00
Misha Brukman
daf998c35f
PowerPCInstrInfo has gone away, PPC32 and PPC64 share opcodes.
...
llvm-svn: 15852
2004-08-17 04:58:50 +00:00
Misha Brukman
38fe66d9d2
PowerPC 32-/64-bit split: Part II, 64-bit customizations on PowerPC
...
llvm-svn: 15851
2004-08-17 04:57:37 +00:00
Misha Brukman
6ce030bf87
PowerPC 32-/64-bit split: Part I, PPC32* bit files, adapted from former PowerPC*
...
llvm-svn: 15850
2004-08-17 04:55:41 +00:00
Chris Lattner
e4eb00de15
Print float constants as 4 byte values.
...
Also, fix endianness problems when cross compiling from little-endian host.
llvm-svn: 15847
2004-08-17 02:48:44 +00:00
Chris Lattner
e3af4ad9b9
Make sure to put an _ prefix on all identifiers!
...
Also, add some (currently disabled) code to print float's as 32-bits.
llvm-svn: 15846
2004-08-17 02:29:00 +00:00
Chris Lattner
b8bb516d6f
More changes to make PPC32 and X86 more similar
...
llvm-svn: 15842
2004-08-16 23:38:36 +00:00
Chris Lattner
f2c9e87003
Minor changes to make the diff be nothing against the X86 version
...
llvm-svn: 15841
2004-08-16 23:30:16 +00:00
Chris Lattner
7fbc0c79e7
Finegrainify namespacification
...
Start using the AsmPrinter base class to factor out a bunch of code
llvm-svn: 15840
2004-08-16 23:25:21 +00:00
Chris Lattner
8448b91e53
There is no need for a cast here
...
llvm-svn: 15810
2004-08-16 05:09:58 +00:00
Nate Begeman
fcb98faaad
Update the current state of the world
...
llvm-svn: 15809
2004-08-16 05:06:43 +00:00
Nate Begeman
c7259a2ff0
Fix typo of the word 'implicit' I made resolving a CVS conflict. Whoops!
...
llvm-svn: 15808
2004-08-16 02:12:49 +00:00
Nate Begeman
00a1951fb1
Fix frame pointer handling:
...
Reserve R0 in store/load from stack slot for building >32k offsets from SP
or FP. This also requires we use R11 rather than R0 for holding the LR
value we want to save or restore. Also, tell the register allocator not
to use R31 (our FP) in functions that have a frame pointer. These changes
fix Burg.
llvm-svn: 15807
2004-08-16 01:52:12 +00:00
Nate Begeman
8cb25bf089
Fix mismatched adjust down/up of SP in functions that contain variable
...
sized allocas.
llvm-svn: 15806
2004-08-16 01:50:22 +00:00
Chris Lattner
b5f94a18e0
Insertion methods now return void instead of #instrs inserted. Also, use
...
more powerful forms of BuildMI to concisify the code
llvm-svn: 15782
2004-08-15 22:15:56 +00:00
Chris Lattner
e58190f5f6
These methods no longer take a TargetRegisterClass* operand.
...
llvm-svn: 15774
2004-08-15 21:56:44 +00:00
Alkis Evlogimenos
dbe432aee7
Make this compile on gc 3.4.1 (static_cast to non-const type was not
...
allowed).
llvm-svn: 15766
2004-08-15 09:18:55 +00:00
Nate Begeman
e24434f765
Add future optimization opportunity
...
llvm-svn: 15760
2004-08-15 06:43:10 +00:00
Nate Begeman
2751f754b5
Fix float to int codepath by always allocating 8 bytes for the target of a double store; optimize cmplwi generation.
...
llvm-svn: 15759
2004-08-15 06:42:28 +00:00
Chris Lattner
caa4f4a263
Zimm16 is now dead. Its entry is not removed from the enum, to avoid having
...
to renumber everything. Similar elimination should be applied to other
operand enum values that are only used to format printing in the .s file.
llvm-svn: 15755
2004-08-15 05:48:47 +00:00
Chris Lattner
6ddb5d6c76
Convert all of the DForm_6* operations, which makes all of the Zimm16 users
...
dead.
llvm-svn: 15754
2004-08-15 05:46:14 +00:00
Chris Lattner
cf6878b6c9
Reenable the CCRC
...
llvm-svn: 15752
2004-08-15 05:31:15 +00:00
Chris Lattner
41839ea5cd
Convert the DForm_4 over to the asmprintergen
...
llvm-svn: 15751
2004-08-15 05:20:16 +00:00
Nate Begeman
9705f413b7
Remove dead code
...
llvm-svn: 15750
2004-08-15 00:31:02 +00:00
Chris Lattner
e19e10e800
Print mflr using the asmwriter generator
...
llvm-svn: 15749
2004-08-14 23:27:29 +00:00
Nate Begeman
224deaa061
Replace PowerPCPEI.cpp with target independant PrologEpilogInserter
...
llvm-svn: 15746
2004-08-14 22:16:36 +00:00
Nate Begeman
826fbd0de1
Add support for frame pointers, and large offsets from stack and frame pointers. Adopt elimination of MachineFunction& arg from eliminateFrameIndex.
...
llvm-svn: 15745
2004-08-14 22:13:58 +00:00
Nate Begeman
557f61c4d6
Add indexed forms of load doubleword and load word algebraic for 64 bit targets
...
llvm-svn: 15743
2004-08-14 22:12:20 +00:00
Nate Begeman
03781a00e8
Fix handling of FP constants with single precision, and loading of internal linkage function addresses
...
llvm-svn: 15742
2004-08-14 22:11:38 +00:00
Nate Begeman
52fb57411b
Add initial support for using the generated asm writer. Also, fix FP constant printing to always print 8 byte intializers. Move printing of LinkOnce stubs.
...
llvm-svn: 15741
2004-08-14 22:09:10 +00:00
Nate Begeman
56b50cb7e8
Add generation of asm writer from tablegen files to Makefile
...
llvm-svn: 15740
2004-08-14 22:06:38 +00:00
Nate Begeman
7024c8a1a4
Remove an unneeded header and forward declaration
...
llvm-svn: 15722
2004-08-13 09:33:17 +00:00
Nate Begeman
101112a2f4
Fix siod by switching BoolTy to byte rather than int until CFE changes for
...
Darwin. Also, change asm printer to output proper stubs for external
functions whose address is passed as an argument to aid in bugpointing.
llvm-svn: 15721
2004-08-13 09:32:01 +00:00
Nate Begeman
6cf8366e11
Fix 177.mesa compilation, don't use floating point regs for base addresses!
...
llvm-svn: 15720
2004-08-13 04:45:14 +00:00
Nate Begeman
9f8ad2f245
Fix llc crasher compiling siod by giving BuildMI the correct number of arguments
...
llvm-svn: 15719
2004-08-13 03:56:49 +00:00
Nate Begeman
6a9f2fd2c1
Longs are in one register on PowerPC 64; use appropriate instructions to operate on them.
...
llvm-svn: 15711
2004-08-13 02:20:47 +00:00
Nate Begeman
48359fbcd0
Add some more 64 bit instructions we need for the PowerPC-64 ISel to the tablegen files
...
llvm-svn: 15710
2004-08-13 02:19:26 +00:00
Misha Brukman
f2c87f4794
Disable PPC64 backend by default because LLC cannot choose automatically between
...
SparcV9 and PowerPC64 without target triples, since they are both 64-bit
big-endian targets.
llvm-svn: 15688
2004-08-12 17:16:43 +00:00
Misha Brukman
bf93b04c17
* Correct 64-bit version: blr 1 (not 0)
...
* BuildMI() can build 0-param instructions (e.g., NOP)
llvm-svn: 15681
2004-08-12 03:30:03 +00:00
Misha Brukman
e281f3a2ac
* Print out full names for non-GPR or -FPR registers
...
* BuildMI() really *does* handle 0 params!
llvm-svn: 15680
2004-08-12 03:28:47 +00:00
Misha Brukman
2851d39ec4
* Pointers are 8 bytes, hence cLong type on 64-bit PPC
...
* Fix loading of GlobalValues
llvm-svn: 15678
2004-08-12 02:53:01 +00:00
Misha Brukman
8bcb04dd35
Eliminate special-casing 14-bit immediate load/store opcodes
...
llvm-svn: 15677
2004-08-12 02:51:38 +00:00
Misha Brukman
1149a822a2
Correctly print out ASCII literal strings on AIX
...
llvm-svn: 15674
2004-08-12 01:01:13 +00:00
Misha Brukman
d9b3a360fc
Mark R2 as available for allocation on Darwin/PPC32, but not AIX/PPC64
...
llvm-svn: 15673
2004-08-12 00:10:01 +00:00
Misha Brukman
14bf47d0d9
* Move AIX into the llvm namespace to be accessed from RegisterInfo
...
* Mark InstrInfo with 32 vs. 64 bit flag
* Enable the 64-bit isel and asm printer
llvm-svn: 15672
2004-08-11 23:47:08 +00:00
Misha Brukman
c24851b980
Set the is64bit flag and propagate it to PowerPCRegisterInfo
...
llvm-svn: 15671
2004-08-11 23:45:43 +00:00
Misha Brukman
42e53e4d94
* Set the is64bit boolean flag in PowerPCRegisterInfo
...
* Doubles are 8 bytes in 64-bit PowerPC, and use the general register class
* Use double-word loads and stores for restoring from/saving to stack
* Do not allocate R2 if compiling for AIX
llvm-svn: 15670
2004-08-11 23:44:55 +00:00
Misha Brukman
fc82624aab
64-bit instruction selector and AIX-specific 64-bit asm printer
...
llvm-svn: 15669
2004-08-11 23:42:15 +00:00
Misha Brukman
0b67e02e9c
Fix names of 64-bit CMP*D* opcodes, add LWA and STD* opcodes
...
llvm-svn: 15668
2004-08-11 23:33:34 +00:00
Misha Brukman
08b8a09113
Add support for 64-bit CMPDI, CMPLDI, and CMPLD opcodes
...
llvm-svn: 15667
2004-08-11 20:56:14 +00:00
Misha Brukman
7325a6c790
Add doubleword load/store (64-bit only).
...
llvm-svn: 15665
2004-08-11 15:54:36 +00:00
Misha Brukman
1f4fb14301
Hyphenate ##-bit and remove first-person from comments.
...
llvm-svn: 15663
2004-08-11 13:35:44 +00:00
Nate Begeman
6120e8f04f
Clean up 32/64bit and Darwin/AIX split. Next steps: 64 bit ISel, AIX asm printer.
...
llvm-svn: 15662
2004-08-11 07:40:04 +00:00
Chris Lattner
2903154b98
Fix a case where constantexprs could leak into the PPC isel.
...
llvm-svn: 15661
2004-08-11 07:34:50 +00:00
Nate Begeman
c07b78eaa2
Fix 255.vortex by using getClassB instead of getClass
...
llvm-svn: 15648
2004-08-11 03:30:55 +00:00
Misha Brukman
694c9ff1a6
Breaking up the PowerPC target into 32- and 64-bit subparts, Part III: the rest.
...
llvm-svn: 15636
2004-08-11 00:11:25 +00:00
Misha Brukman
47c87a8808
Breaking up the PowerPC target into 32- and 64-bit subparts: Part II: 64-bit.
...
llvm-svn: 15635
2004-08-11 00:10:41 +00:00
Misha Brukman
6713996576
Breaking up the PowerPC target into 32- and 64-bit subparts, Part I: 32-bit.
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llvm-svn: 15634
2004-08-11 00:09:42 +00:00
Misha Brukman
3f79fbe93f
Renamed PPC32 (namespace for regs, opcodes) to PPC to include 64-bit targets
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llvm-svn: 15631
2004-08-10 22:47:03 +00:00
Misha Brukman
aa0e45b8d8
* Fix file header to use tablegen emacs mode instead of c++
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* Wrap long line to 80 cols
llvm-svn: 15630
2004-08-10 21:24:44 +00:00
Nate Begeman
b74ee41754
Fix casts of float to unsigned long
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Replace STDX (store 64 bit int indexed) with STFDX (store double indexed)
Fix latent bug in indexed load generation
Generate indexed loads and stores in many more cases
llvm-svn: 15626
2004-08-10 20:42:36 +00:00
Misha Brukman
861d6cdcb1
DForm 5/6 extended mneumonics take 3 arguments.
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llvm-svn: 15620
2004-08-10 19:03:31 +00:00
Misha Brukman
fe7a08a933
Fix DForm_4: format is `op r, r, i'
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llvm-svn: 15613
2004-08-10 18:07:55 +00:00
Misha Brukman
d345cd9090
Stub definition of the PowerPC CodeEmitter class; this isn't functional (yet).
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llvm-svn: 15600
2004-08-09 23:03:59 +00:00
Misha Brukman
3da9167cc4
CodePrinter -> AsmPrinter
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llvm-svn: 15599
2004-08-09 22:27:45 +00:00
Misha Brukman
65afbbca70
Remove ClassPrefix variable as it's no longer used.
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llvm-svn: 15586
2004-08-09 19:13:29 +00:00
Misha Brukman
1547d8e8d0
Define a ClassPrefix for PowerPC.
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llvm-svn: 15580
2004-08-09 17:46:26 +00:00
Misha Brukman
eb8758cc0c
Generate a code emitter for PowerPC as well, this will be used in the JIT.
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llvm-svn: 15578
2004-08-09 17:24:32 +00:00
Misha Brukman
ba013330a8
Use instruction formats as defined in the PowerPC ISA manual
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llvm-svn: 15577
2004-08-09 17:24:04 +00:00
Reid Spencer
8bf21cd984
Fix stack size processing now that the return address isn't an implied
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push onto the top of the stack like x86, which uses the local area
offset. This will allow the removal of PowerPCPEI.cpp soon.
llvm-svn: 15573
2004-08-09 01:24:32 +00:00
Chris Lattner
bbf11b1e1d
Changes commited for Nate Begeman:
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Use a PowerPC specific prolog epilog inserter to control where spilled
callee save regs are placed on the stack.
Get rid of implicit return address stack slot, save return address reg
(LR) in appropriate slot
Improve code generated for functions that don't have calls or access
globals
Note from Chris: PowerPCPEI will eventually be eliminated, once the
functionality is merged into CodeGen/PrologEpilogInserter.cpp
llvm-svn: 15536
2004-08-06 06:58:50 +00:00
John Criswell
451362550e
Added Louis Gerbarg. Louis is given credit in the CREDITS.TXT file, so I
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assume Louis also holds copyright.
llvm-svn: 15534
2004-08-05 23:46:27 +00:00
John Criswell
45cf7f6a0f
Add additional copyright notice for the PowerPC backend.
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Thanks Nate!
llvm-svn: 15531
2004-08-05 20:36:00 +00:00
Misha Brukman
4a2823d1ae
Simplify makefile by combining all TableGen dependencies into one variable
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llvm-svn: 15527
2004-08-05 18:34:15 +00:00
Misha Brukman
3014727a37
Align dependencies so they don't hurt the eyes to look at them
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llvm-svn: 15504
2004-08-04 21:37:41 +00:00
Misha Brukman
b296dd721c
Remove unused instruction classes
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llvm-svn: 15501
2004-08-04 21:18:57 +00:00
Misha Brukman
ef93ca23ba
Make tablegen targets depend on PowerPCInstrFormats.td as well
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llvm-svn: 15500
2004-08-04 21:18:36 +00:00
Chris Lattner
1ce22d3d43
getValues does not exist
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llvm-svn: 15495
2004-08-04 17:29:14 +00:00
Misha Brukman
07f8b33325
Remove unused opcodes.
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llvm-svn: 15447
2004-08-03 20:23:44 +00:00
Misha Brukman
10a585beaf
* Use simpler instruction templates to define instructions
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* Fix several extended opcodes
llvm-svn: 15423
2004-08-02 21:58:52 +00:00
Misha Brukman
e7ad7b2f2a
Replace patterns 0, 4, and 5 with simpler heirarchical definitions that use the
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official PowerPC instruction format lingo: X- and D-form.
llvm-svn: 15422
2004-08-02 21:56:35 +00:00
Misha Brukman
f2119a5b6f
Separate instruction formats from instruction definitions.
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llvm-svn: 15414
2004-08-02 16:54:54 +00:00
Misha Brukman
8209358fca
* Conditional save/restore of LR disabled as it's not quite correct
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* sumarray2d fixed: large fixed-size alloca
* make is now compileable
* Re-organized tests to fit them under proper headings
Patch by Nate Begeman.
llvm-svn: 15347
2004-07-30 15:53:09 +00:00
Misha Brukman
f0c6eaca10
Do not mark LR as callee-save: not quite correctly done. Patch: Nate Begeman.
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llvm-svn: 15346
2004-07-30 15:51:51 +00:00
Misha Brukman
27ced926da
* Temporarily suspend LR save/restore optimization as it is not quite correct
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* Implement large fixed-size allocas Entire patch by Nate Begeman.
llvm-svn: 15345
2004-07-30 15:50:45 +00:00
Chris Lattner
6bea23ff54
Minor corrections
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llvm-svn: 15309
2004-07-28 20:18:53 +00:00
Misha Brukman
8e19054114
Add notes on bug involving casting ulong -> double, thanks to Nate Begeman.
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llvm-svn: 15307
2004-07-28 19:16:10 +00:00
Misha Brukman
a8bcaec663
Simplify loading (un)signed constants to registers, patch by Nate Begeman.
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llvm-svn: 15306
2004-07-28 19:13:49 +00:00
Misha Brukman
b699e3d825
Remove an extra 8 byte distance penalty. Patch by Nate Begeman.
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llvm-svn: 15305
2004-07-28 19:13:07 +00:00
Misha Brukman
6e134ad499
Find longs by type, not by their primitive size being 64. Patch by Nate Begeman.
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llvm-svn: 15304
2004-07-28 19:12:24 +00:00
Misha Brukman
8c293deaad
LI can only take signed values, so values > 32767 can only be loaded with ORI
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llvm-svn: 15299
2004-07-28 00:56:04 +00:00
Misha Brukman
ac63bc04f8
Reorganize tests to place them in proper directories.
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llvm-svn: 15298
2004-07-28 00:55:12 +00:00
Misha Brukman
8fc18d7d1c
UnitTests 2003-05-26-Shorts and 2003-07-09-LoadShorts have been fixed;
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2003-05-22-VarSizeArray is broken.
llvm-svn: 15297
2004-07-28 00:01:41 +00:00
Misha Brukman
1b4bc02316
Fix printing of immediate operands by looking at their operand types in
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the TargetInstrInfo. This fixes UnitTests 2003-05-26-Shorts and
2003-07-09-LoadShorts.
llvm-svn: 15296
2004-07-28 00:00:48 +00:00
Misha Brukman
148ad01de1
Renamed files:
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* PowerPCReg.td => PowerPCRegisterinfo.td
* PowerPCInstrs.td => PowerPCInstrInfo.td
llvm-svn: 15295
2004-07-27 23:29:16 +00:00
Misha Brukman
b779843f6b
Branch selection support implemented by Nate Begeman for long branches.
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llvm-svn: 15288
2004-07-27 18:43:04 +00:00
Misha Brukman
b07f569386
Correctly print out long branches, assert on finding pseudo instr COND_BRANCH
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Patch by Nate Begeman.
llvm-svn: 15286
2004-07-27 18:40:39 +00:00
Misha Brukman
ef0cbd830c
Run the branch selection pass right before the asm printer.
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Patch by Nate Begeman.
llvm-svn: 15285
2004-07-27 18:39:34 +00:00
Misha Brukman
0f26a3309f
Remove empty unused method processFunctionBeforeFrameFinalized()
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llvm-svn: 15284
2004-07-27 18:38:40 +00:00
Misha Brukman
8c047d4fad
Add COND_BRANCH pseudo instruction, patch by Nate Begeman.
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llvm-svn: 15283
2004-07-27 18:35:54 +00:00
Misha Brukman
d7d501d518
Build COND_BRANCHes which may become long or short, decided by a later pass.
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Patch by Nate Begeman.
llvm-svn: 15282
2004-07-27 18:35:23 +00:00
Misha Brukman
8e2f8de3c3
Moved definition of invertPPCBranchOpcode() into PowerPCInstrInfo class.
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Patch by Nate Begeman.
llvm-svn: 15281
2004-07-27 18:34:11 +00:00
Misha Brukman
0fe1f5d880
Add PowerPCBranchSelector to discover which are `long' branches.
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Contributed by Nate Begeman.
llvm-svn: 15280
2004-07-27 18:33:06 +00:00
Misha Brukman
c22bbdd36d
Fixed saving/restoring LR unconditionally, only done as necessary.
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llvm-svn: 15275
2004-07-27 17:17:48 +00:00
Misha Brukman
adb86dba29
Save and restore LR just like any other register and ONLY if we actually modify
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it (due to calls or globals access). We now compile `void empty(){}' to `blr'.
llvm-svn: 15274
2004-07-27 17:17:18 +00:00