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5858 Commits

Author SHA1 Message Date
Nate Begeman
d22dd0f92b Disable LSR at -fast 
llvm-svn: 29467
 2006-08-02 05:29:40 +00:00
Rafael Espindola
719336441f start comments with # 
move the constant pool to .text
correctly print loads of labels
mark R0, R1, R2 and R3 as caller save

llvm-svn: 29451
 2006-08-01 18:53:10 +00:00
Rafael Espindola
f11277971f implement LowerConstantPool and LowerGlobalAddress 
llvm-svn: 29433
 2006-08-01 12:58:43 +00:00
Evan Cheng
29d6f9d252 Factor topological order code to SelectionDAG. Clean up. 
llvm-svn: 29430
 2006-08-01 08:17:22 +00:00
Chris Lattner
26ff12f7f5 Fix PR850 and CodeGen/X86/2006-07-31-SingleRegClass.ll. 
The CFE refers to all single-register constraints (like "A") by their 16-bit
name, even though the 8 or 32-bit version of the register may be needed.
The X86 backend should realize what is going on and redecode the name back
to its proper form.

llvm-svn: 29420
 2006-07-31 23:26:50 +00:00
Rafael Espindola
0ea0399411 handle GlobalValue::InternalLinkage in doFinalization 
llvm-svn: 29417
 2006-07-31 20:38:13 +00:00
Evan Cheng
92eb9a1639 Remove a duplicate pattern. 
llvm-svn: 29414
 2006-07-31 18:43:10 +00:00
Evan Cheng
7e30f4efe7 Remove a duplicate pattern/ 
llvm-svn: 29413
 2006-07-31 18:42:49 +00:00
Chris Lattner
8cb78a0d45 Make functions with an "asm" name propagate that asm name into the cbe.c file. 
This fixes link errors on programs with these on targets with prefixes.

llvm-svn: 29390
 2006-07-28 20:58:47 +00:00
Chris Lattner
51e1b75fba Fix some ppc64 issues with vector code. 
llvm-svn: 29384
 2006-07-28 16:45:47 +00:00
Evan Cheng
e4c19806cd Can't spell. 
llvm-svn: 29383
 2006-07-28 06:33:41 +00:00
Evan Cheng
8ea5ac0abd Some clean up. 
llvm-svn: 29382
 2006-07-28 06:05:06 +00:00
Evan Cheng
5f0e94c299 Rename IsFoldableBy to CanBeFoldedleBy 
llvm-svn: 29376
 2006-07-28 01:03:48 +00:00
Evan Cheng
c43a75b7d4 Node selected into address mode cannot be folded. 
llvm-svn: 29374
 2006-07-28 00:49:31 +00:00
Evan Cheng
3b5f1c6248 Remove InFlightSet hack. No longer needed. 
llvm-svn: 29373
 2006-07-28 00:47:19 +00:00
Evan Cheng
8920047e85 Another duh. Determine topological order before any target node is added. 
llvm-svn: 29371
 2006-07-28 00:10:59 +00:00
Evan Cheng
9d43eb616a Brain cramp.. 
llvm-svn: 29370
 2006-07-27 23:35:40 +00:00
Evan Cheng
24b41a766b Allocating too large an array for ReachibilityMatrix. 
llvm-svn: 29367
 2006-07-27 22:35:40 +00:00
Evan Cheng
17ccdcc415 Calculate the portion of reachbility matrix on demand. 
llvm-svn: 29366
 2006-07-27 22:10:00 +00:00
Evan Cheng
6a126e3adb isNonImmUse is replaced by IsFoldableBy 
llvm-svn: 29365
 2006-07-27 21:19:10 +00:00
Evan Cheng
4ceeac4159 Resolve BB references with relocation. 
llvm-svn: 29351
 2006-07-27 18:21:10 +00:00
Evan Cheng
f363ae6ebd synchronizeICache removeed from TargetJITInfo. 
llvm-svn: 29348
 2006-07-27 17:33:48 +00:00
Evan Cheng
dbcca8f422 Use reachbility information to determine whether a node can be folded into another during isel. 
llvm-svn: 29346
 2006-07-27 16:44:36 +00:00
Rafael Espindola
c0ede90402 emit global constants 
llvm-svn: 29344
 2006-07-27 11:38:51 +00:00
Evan Cheng
e869883c2d Remove NodeDepth 
llvm-svn: 29338
 2006-07-27 06:40:15 +00:00
Chris Lattner
92a0b69813 Add some advice 
llvm-svn: 29324
 2006-07-27 04:24:14 +00:00
Jim Laskey
046abcdbec Use the predicate. 
llvm-svn: 29322
 2006-07-27 02:05:13 +00:00
Nate Begeman
3d5f5b4e8b Support jump tables when in PIC relocation model 
llvm-svn: 29318
 2006-07-27 01:13:04 +00:00
Jim Laskey
f35dd1a670 Prevent creation of MachineDebugInfo for intel unless it is darwin. RC842. 
llvm-svn: 29317
 2006-07-27 01:12:23 +00:00
Evan Cheng
27c53dc36e New entry. 
llvm-svn: 29310
 2006-07-26 21:49:52 +00:00
Chris Lattner
b4165c39d7 Rename RelocModel::PIC to PIC_, to avoid conflicts with -DPIC. 
llvm-svn: 29307
 2006-07-26 21:12:04 +00:00
Evan Cheng
beeb4e5c8c - Refactor the code that resolve basic block references to a TargetJITInfo 
method.
- Added synchronizeICache() to TargetJITInfo. It is called after each block
  of code is emitted to flush the icache. This ensures correct execution
  on targets that have separate dcache and icache.
- Added PPC / Mac OS X specific code to do icache flushing.

llvm-svn: 29276
 2006-07-25 20:40:54 +00:00
Evan Cheng
692215be9c Can't commute shufps. The high / low parts elements come from different vectors. 
llvm-svn: 29275
 2006-07-25 20:25:40 +00:00
Rafael Espindola
2919d4ce24 implement function calling of functions with up to 4 arguments 
llvm-svn: 29274
 2006-07-25 20:17:20 +00:00
Evan Cheng
56e0c65937 Done. 
llvm-svn: 29262
 2006-07-21 23:07:23 +00:00
Rafael Espindola
9ea0bc742c implemented sub 
correctly update the stack pointer in the prologue and epilogue

llvm-svn: 29244
 2006-07-21 12:26:16 +00:00
Evan Cheng
ed1c019899 This opt is now handled in DAG combine. 
llvm-svn: 29243
 2006-07-21 08:26:46 +00:00
Evan Cheng
56434b7578 A splat of a vector constant of all zero or all one is the vector constant. 
llvm-svn: 29234
 2006-07-20 23:09:47 +00:00
Evan Cheng
a634c2b838 Missing a space. 
llvm-svn: 29233
 2006-07-20 22:52:28 +00:00
Evan Cheng
100096b2bb Clean up. 
llvm-svn: 29228
 2006-07-20 21:37:39 +00:00
Evan Cheng
6e440c39da New entry. 
llvm-svn: 29215
 2006-07-19 21:29:30 +00:00
Jim Laskey
5d139b794a Do once flag never set to true. 
llvm-svn: 29214
 2006-07-19 19:33:08 +00:00
Jim Laskey
88d7595eb3 Tidy up a few things. 
llvm-svn: 29213
 2006-07-19 19:32:06 +00:00
Jim Laskey
d31b3778d8 Reduce size of routine. Shrinks .o by 37%. 
llvm-svn: 29210
 2006-07-19 17:53:32 +00:00
Chris Lattner
0f4e4b1bcb bswapped load/store instructions are only availble in indexed addressing form. 
As such, use xoaddr (indexed only), not xaddr for address selection.

This fixes CodeGen/PowerPC/2006-07-19-stwbrx-crash.ll, a crash compiling lencod.

llvm-svn: 29208
 2006-07-19 17:15:36 +00:00
Jim Laskey
227b585c6e Bug#834 ICE (crash in code generator?) when building PCH . 
Missing Darwin check in Intel ATT ASM printer.

llvm-svn: 29204
 2006-07-19 11:54:50 +00:00
Evan Cheng
793f3d97ff Misc. new entry. 
llvm-svn: 29202
 2006-07-19 06:06:24 +00:00
Evan Cheng
a2eaed93a0 INC / DEC instructions have shorter code size than ADD32ri8, etc. 
llvm-svn: 29194
 2006-07-19 00:27:29 +00:00
Evan Cheng
abd650f034 Add code size to target instruction use it as the 3rd isel sorting tie-breaker. 
llvm-svn: 29193
 2006-07-19 00:24:41 +00:00
Rafael Espindola
ad256854c0 initial prologue and epilogue implementation. Need to define add and sub before finishing it :-) 
llvm-svn: 29175
 2006-07-18 17:00:30 +00:00
Chris Lattner
5985b77fae Make the implicit def instructions look like other instrs. 
llvm-svn: 29174
 2006-07-18 16:33:26 +00:00
Rafael Espindola
40073f5767 skeleton of a lowerCall implementation for ARM 
llvm-svn: 29159
 2006-07-16 01:02:57 +00:00
Chris Lattner
f022962081 Remove what little AIX support we have. It has never been tested and isn't 
complete.

llvm-svn: 29156
 2006-07-15 01:24:23 +00:00
Chris Lattner
0f2560a313 Add an out-of-line virtual method for X86DwarfWriter to give it a home. 
llvm-svn: 29153
 2006-07-14 23:05:05 +00:00
Chris Lattner
ff8ee5486f Add missing PPC64 extload/truncstores 
llvm-svn: 29140
 2006-07-14 04:42:02 +00:00
Chris Lattner
9aafd2b441 Add a note 
llvm-svn: 29139
 2006-07-14 04:07:29 +00:00
Chris Lattner
5c489bce2c Another fix in the rotate encodings, needed when the first two operands are not 
the same.

llvm-svn: 29136
 2006-07-13 21:52:41 +00:00
Chris Lattner
753e4f5984 Print negative immediates as negative values instead of large constants 
when using the immshifted addressing mode.

llvm-svn: 29130
 2006-07-12 23:24:02 +00:00
Chris Lattner
726ca018c0 Fix encoding of rotates, such as rldicl 
llvm-svn: 29128
 2006-07-12 22:08:13 +00:00
Chris Lattner
024af03a3c Implement PPC64 relocations types 
llvm-svn: 29125
 2006-07-12 21:23:20 +00:00
Chris Lattner
c9be3277e7 An overaggressive #ifdef allows a function to fall off the bottom of the 
function instead of returning a value.  This sometimes allowed the ppc32 jit
to be used in 64-bit mode.

llvm-svn: 29123
 2006-07-12 20:42:10 +00:00
Chris Lattner
d0202bbed3 Add information preventing several register class constraints from working. 
This implements PR828 and CodeGen/X86/2006-07-12-InlineAsmQConstraint.ll

llvm-svn: 29118
 2006-07-12 16:59:49 +00:00
Chris Lattner
fd9cbcab4a The PPC64 JIT needs register numbers to encode instructions. 
llvm-svn: 29114
 2006-07-11 20:53:55 +00:00
Evan Cheng
db529debec Emit inc / dec of registers as one byte instruction. 
llvm-svn: 29110
 2006-07-11 19:49:49 +00:00
Jim Laskey
d19ba2cf6c It was pointed out that DEBUG() is only available with -debug. 
llvm-svn: 29106
 2006-07-11 18:25:13 +00:00
Jim Laskey
4c0d841280 Ensure that dump calls that are associated with asserts are removed from 
non-debug build.

llvm-svn: 29105
 2006-07-11 17:58:07 +00:00
Rafael Espindola
fdfaee67f5 add the memri memory operand 
this makes it possible for ldr instructions with non-zero immediate

llvm-svn: 29103
 2006-07-11 11:36:48 +00:00
Chris Lattner
b75fe307e1 Implement the inline asm 'A' constraint. This implements PR825 and 
CodeGen/X86/2006-07-10-InlineAsmAConstraint.ll

llvm-svn: 29101
 2006-07-11 02:54:03 +00:00
Chris Lattner
2db97248f8 In 64-bit mode, 64-bit GPRs are callee saved, not 32-bit ones. 
llvm-svn: 29096
 2006-07-11 00:48:23 +00:00
Evan Cheng
7c11ad2f8d New entry. 
llvm-svn: 29091
 2006-07-10 21:42:16 +00:00
Evan Cheng
b5e6a4a74d Fixed stack objects do not specify alignments, but their offsets are known. 
Use that information when doing the transformation to merge multiple loads
into a 128-bit load.

llvm-svn: 29090
 2006-07-10 21:37:44 +00:00
Chris Lattner
abaaddc214 Implement Regression/CodeGen/PowerPC/bswap-load-store.ll by folding bswaps 
into i16/i32 load/stores.

llvm-svn: 29089
 2006-07-10 20:56:58 +00:00
Chris Lattner
18c77b92a9 Mark internal function static 
llvm-svn: 29085
 2006-07-10 19:53:12 +00:00
Rafael Espindola
071c83dff0 create the raddr addressing mode that matches any register and the frame index 
use raddr for the ldr instruction. This removes a dummy mov from the assembly output
remove SelectFrameIndex
remove isLoadFromStackSlot
remove isStoreToStackSlot

llvm-svn: 29079
 2006-07-10 01:41:35 +00:00
Evan Cheng
d460c903b1 Fix a typo that causes 2006-07-07-ComputeMaskedBits.ll to fail. 
llvm-svn: 29072
 2006-07-07 21:37:21 +00:00
Evan Cheng
1d48a494a2 X86 target specific DAG combine: turn build_vector (load x), (load x+4), 
(load x+8), (load x+12), <0, 1, 2, 3> to a single 128-bit load (aligned and
unaligned).

e.g.

__m128 test(float a, float b, float c, float d) {
  return _mm_set_ps(d, c, b, a);
}

_test:
        movups 4(%esp), %xmm0
        ret

llvm-svn: 29042
 2006-07-07 08:33:52 +00:00
Chris Lattner
da960e218f Undisable ppc64 jit 
llvm-svn: 29011
 2006-07-06 17:10:42 +00:00
Evan Cheng
a6c9288186 Added option -code-model to set code model (only used in 64-bit) mode. Valid 
values include small, kernel, medium, large, and default.

llvm-svn: 29009
 2006-07-06 01:53:36 +00:00
Evan Cheng
801ea78096 Reorg. No functionality change. 
llvm-svn: 28999
 2006-07-05 22:17:51 +00:00
Evan Cheng
d75aed0d60 Fix JIT on non MacOS X i386 systems. 
llvm-svn: 28992
 2006-07-05 07:09:13 +00:00
Andrew Lenharth
9ea557b06b These are already implemented 
llvm-svn: 28990
 2006-07-03 18:00:29 +00:00
Andrew Lenharth
98f5e9c45a 0 offsets for memory operands 
llvm-svn: 28989
 2006-07-03 17:57:34 +00:00
Evan Cheng
0df13a4f2a Should just use xorps to clear XMM registers for all data types. pxor is also one byte longer. 
llvm-svn: 28984
 2006-06-29 18:04:54 +00:00
Evan Cheng
5a7af4f99f Let X86CompilationCallback pass previous frame and return address to X86CompilationCallback2. Remove alloca hack. 
llvm-svn: 28982
 2006-06-29 01:48:36 +00:00
Evan Cheng
1d5fa40da3 Add shift and rotate by 1 instructions / patterns. 
llvm-svn: 28980
 2006-06-29 00:36:51 +00:00
Evan Cheng
803891eaa8 Always use xorps to clear XMM registers. 
llvm-svn: 28979
 2006-06-29 00:34:23 +00:00
Evan Cheng
1b53896495 Move .literal4 and .literal8 support into AsmPrinter.cpp 
llvm-svn: 28978
 2006-06-29 00:33:06 +00:00
Chris Lattner
adc7078c98 Hide x86 symbols 
llvm-svn: 28976
 2006-06-28 23:27:49 +00:00
Chris Lattner
496bd3fbf6 Use hidden visibility to make symbols in an anonymous namespace get 
dropped.  This shrinks libllvmgcc.dylib another 67K

llvm-svn: 28975
 2006-06-28 23:17:24 +00:00
Chris Lattner
26f1985fdc shrink libllvmgcc.dylib another 25K 
llvm-svn: 28971
 2006-06-28 22:00:36 +00:00
Evan Cheng
36d3fccf4b Doh. 
llvm-svn: 28963
 2006-06-28 17:56:43 +00:00
Evan Cheng
e123f47232 Oops. Need to keep CP index. 
llvm-svn: 28958
 2006-06-28 07:55:24 +00:00
Evan Cheng
3963b5ee02 Darwin puts float and double literal constants into literal4 and literal8 sections. 
llvm-svn: 28957
 2006-06-28 07:35:41 +00:00
Andrew Lenharth
ae9cbe3545 this case isn't handled 
llvm-svn: 28948
 2006-06-27 23:19:14 +00:00
Rafael Espindola
f11f34a3d6 handle the "mov reg1, reg2" case in isMoveInstr 
llvm-svn: 28945
 2006-06-27 21:52:45 +00:00
Chris Lattner
852423b469 Don't match 64-bit bitfield inserts into rlwimi's. todo add rldimi. :) 
llvm-svn: 28944
 2006-06-27 21:08:52 +00:00
Chris Lattner
d7b1f61e72 Fix ppc64 jump tables 
llvm-svn: 28941
 2006-06-27 20:46:17 +00:00
Evan Cheng
a37a2f781e Remove dead code. 
llvm-svn: 28938
 2006-06-27 20:34:14 +00:00
Chris Lattner
01965c2fd8 Print stubs for external globals right. 
llvm-svn: 28936
 2006-06-27 20:20:53 +00:00
Chris Lattner
2c3f67f6a7 Implement 64-bit select, bswap, etc. 
llvm-svn: 28935
 2006-06-27 20:14:52 +00:00
Chris Lattner
86c7ca4fd4 Add a pattern for i64 sra. Print 8-byte units with a space between the .quad 
and the data

llvm-svn: 28934
 2006-06-27 20:07:26 +00:00
Chris Lattner
3422f47382 Fix rewriting frame offsets with ixaddr instructions, which implicitly shift 
the offset two bits to the left.

llvm-svn: 28933
 2006-06-27 18:55:49 +00:00
Chris Lattner
8569f4042d PPC doesn't have bit converts to/from i64 
llvm-svn: 28932
 2006-06-27 18:40:08 +00:00
Chris Lattner
da08df5d8a Add 64-bit MTCTR so that indirect calls work. 
llvm-svn: 28931
 2006-06-27 18:36:44 +00:00
Chris Lattner
20959f59cd Fix an incorrect store pattern. This fixes em3d. 
llvm-svn: 28930
 2006-06-27 18:22:50 +00:00
Chris Lattner
26f2bd4d4b Implement 64-bit undef, sub, shl/shr, srem/urem 
llvm-svn: 28929
 2006-06-27 18:18:41 +00:00
Chris Lattner
b4a636f966 Use i32 for shift amounts instead of i64. This gets bisort working. 
llvm-svn: 28927
 2006-06-27 17:34:57 +00:00
Chris Lattner
01182783c4 Add zextload from i32 -> i64, with this, perimeter works. 
llvm-svn: 28926
 2006-06-27 17:30:08 +00:00
Chris Lattner
10e71f60df Print darwin stub stuff correctly in 64-bit mode. With this, treeadd works in 
ppc64 mode!

llvm-svn: 28923
 2006-06-27 01:02:25 +00:00
Chris Lattner
a572f110b4 Fix variable shadowing issue 
llvm-svn: 28922
 2006-06-27 00:10:13 +00:00
Chris Lattner
494f476ca7 Implement a bunch of 64-bit cleanliness work. With this, treeadd builds (but 
doesn't work right).

llvm-svn: 28921
 2006-06-27 00:04:13 +00:00
Chris Lattner
c8a47e0bb0 Rearrange compares, add ADDI8, add sext from 32-to-64 bit register 
llvm-svn: 28920
 2006-06-26 23:53:10 +00:00
Chris Lattner
cbd4d14b24 Improve PPC64 calling convention support 
llvm-svn: 28919
 2006-06-26 22:48:35 +00:00
Chris Lattner
5d0654b832 Remove two more definitions 
llvm-svn: 28918
 2006-06-26 22:47:37 +00:00
Chris Lattner
209c2db6b9 remove two unused instructions. 
llvm-svn: 28917
 2006-06-26 22:44:13 +00:00
Evan Cheng
db5c7909f5 Simplify X86CompilationCallback: always align to 16-byte boundary; don't save EAX/EDX if unnecessary. 
llvm-svn: 28910
 2006-06-24 08:36:10 +00:00
Jim Laskey
a8284f65e1 Add and sort "sections" in debug lines. This always stepping through 
code in sections other than ".text", including weak sections like ctors and
dtors.

llvm-svn: 28909
 2006-06-23 12:51:53 +00:00
Evan Cheng
d8090f4666 Eliminate unneeded parameter. 
llvm-svn: 28907
 2006-06-22 00:02:55 +00:00
Evan Cheng
420ea2c264 variable_ops instructions such as call can have any number of operands. 
llvm-svn: 28906
 2006-06-21 23:37:07 +00:00
Andrew Lenharth
e75c2ec042 Add memory operand and int regs 
llvm-svn: 28896
 2006-06-21 15:42:36 +00:00
Andrew Lenharth
f794ded743 inline asm, at least for floats 
llvm-svn: 28895
 2006-06-21 13:37:27 +00:00
Andrew Lenharth
78e0cc794f fix argument problem 
llvm-svn: 28893
 2006-06-21 01:00:43 +00:00
Chris Lattner
5fa6e47534 Correct returns of 64-bit values, though they seemed to work before... 
llvm-svn: 28892
 2006-06-21 00:34:03 +00:00
Chris Lattner
10d22c274e Make these predicates correct in 64-bit mode too. 
llvm-svn: 28890
 2006-06-20 23:21:20 +00:00
Chris Lattner
75e6449a0f Rename OR4 -> OR. Move some PPC64-specific stuff to the 64-bit file 
llvm-svn: 28889
 2006-06-20 23:18:58 +00:00
Chris Lattner
2e1d3158f1 remove unused flag 
llvm-svn: 28888
 2006-06-20 23:15:07 +00:00
Chris Lattner
c74ef80a95 add some logical ops 
llvm-svn: 28887
 2006-06-20 23:11:59 +00:00
Chris Lattner
19df1fcd72 remove some unused patterns 
llvm-svn: 28886
 2006-06-20 23:11:36 +00:00
Chris Lattner
40a0a6c400 Add some more immediate patterns. This allows us to compile: 
void test6() {
  Y = 0xABCD0123BCDE4567;
}

into:

_test6:
        lis r2, -21555
        lis r3, ha16(_Y)
        ori r2, r2, 291
        rldicr r2, r2, 32, 31
        oris r2, r2, 48350
        ori r2, r2, 17767
        std r2, lo16(_Y)(r3)
        blr

llvm-svn: 28885
 2006-06-20 23:03:01 +00:00
Chris Lattner
690b03fb44 Instead of li/xoris use li/oris. Note that this doesn't work if bit 15 is 
set, so disable the pattern in that case.

llvm-svn: 28884
 2006-06-20 22:38:59 +00:00
Chris Lattner
eede1e2c00 Add some 64-bit logical ops. 
Split imm16Shifted into a sext/zext form for 64-bit support.
Add some patterns for immediate formation.  For example, we now compile this:

static unsigned long long Y;
void test3() {
  Y = 0xF0F00F00;
}

into:

_test3:
        li r2, 3840
        lis r3, ha16(_Y)
        xoris r2, r2, 61680
        std r2, lo16(_Y)(r3)
        blr

GCC produces:

_test3:
        li r0,0
        lis r2,ha16(_Y)
        ori r0,r0,61680
        sldi r0,r0,16
        ori r0,r0,3840
        std r0,lo16(_Y)(r2)
        blr

llvm-svn: 28883
 2006-06-20 22:34:10 +00:00
Evan Cheng
b0bb6dd981 __i386__, __i386, etc. are not defined for x86-64. Use __x86_64__. 
llvm-svn: 28881
 2006-06-20 22:11:12 +00:00
Chris Lattner
4ff5f3d852 64-bit bugfix: 0xFFFF0000 cannot be formed with a single lis. 
llvm-svn: 28880
 2006-06-20 21:39:30 +00:00
Chris Lattner
c97820b17c Add some patterns for globals, so we can now compile this: 
static unsigned long long X, Y;
void test1() {
  X = Y;
}

into:

_test1:
        lis r2, ha16(_Y)
        lis r3, ha16(_X)
        ld r2, lo16(_Y)(r2)
        std r2, lo16(_X)(r3)
        blr

llvm-svn: 28879
 2006-06-20 21:23:06 +00:00
Chris Lattner
3ae4156dd7 Remove some now-unneeded casts from instruction patterns. With the casts 
removed, tblgen produces identical output to with them in.

llvm-svn: 28867
 2006-06-20 00:39:56 +00:00
Chris Lattner
19339e7a96 Add some patterns for ppc64 
llvm-svn: 28866
 2006-06-20 00:38:36 +00:00
Chris Lattner
2e64872117 Remove some ugly now-redundant casts. 
llvm-svn: 28864
 2006-06-20 00:25:29 +00:00
Chris Lattner
fbea064e90 Fix some mismatched type constraints 
llvm-svn: 28862
 2006-06-20 00:12:37 +00:00
Evan Cheng
98d508af83 Minor clean up. 
llvm-svn: 28860
 2006-06-19 19:25:30 +00:00
Rafael Espindola
14a59f5b6e initial implementation of ARMRegisterInfo::eliminateFrameIndex 
fixes test/Regression/CodeGen/ARM/ret_arg5.ll

llvm-svn: 28854
 2006-06-18 00:08:07 +00:00
Evan Cheng
e3b8db6dda A new entry. 
llvm-svn: 28848
 2006-06-17 00:45:49 +00:00
Chris Lattner
d817b32a8e Implement the getPointerRegClass method, which is required for the ptr_rc 
magic to work.

llvm-svn: 28847
 2006-06-17 00:01:04 +00:00
Evan Cheng
78e6cefad9 Later models likely to have Yonah like attributes. 
llvm-svn: 28843
 2006-06-16 21:58:49 +00:00
Chris Lattner
89a0d10812 Upgrade some load/store instructions to use the proper addressing mode stuff. 
llvm-svn: 28841
 2006-06-16 21:29:41 +00:00
Chris Lattner
163da7cdcb In 64-bit mode, addr mode operands use G8RC instead of GPRC. 
llvm-svn: 28840
 2006-06-16 21:29:03 +00:00
Chris Lattner
81845946ff fix some assumptions that pointers can only be 32-bits. With this, we can 
now compile:

static unsigned long X;
void test1() {
  X = 0;
}

into:

_test1:
        lis r2, ha16(_X)
        li r3, 0
        stw r3, lo16(_X)(r2)
        blr

Totally amazing :)

llvm-svn: 28839
 2006-06-16 21:01:35 +00:00
Chris Lattner
cb294464e7 Split 64-bit instructions out into a separate .td file 
llvm-svn: 28838
 2006-06-16 20:22:01 +00:00
Chris Lattner
59947dda25 Force 64-bit register availability in 64-bit mode. For real. 
llvm-svn: 28837
 2006-06-16 20:05:06 +00:00
Chris Lattner
126464b577 Remove the -darwin and -aix llc options, inferring darwinism and aixism from 
the target triple & subtarget info.  woo.

llvm-svn: 28835
 2006-06-16 18:50:48 +00:00
Chris Lattner
6a9ec7e80e Don't pass target name into TargetData anymore, it is never used or needed. 
Remove explicit casts to std::string now that there is no overload resolution
issues in the TargetData ctors.

llvm-svn: 28830
 2006-06-16 18:22:52 +00:00
Chris Lattner
9fcdb0d7e5 Remove ctor with each piece specifyable (which causes overload ambiguities), 
add a new init method.

llvm-svn: 28828
 2006-06-16 18:11:26 +00:00
Chris Lattner
19680a4928 Document the subtarget features better, make sure that 64-bit mode, 64-bit 
support, and 64-bit register use are all consistent with each other.

Add a new "IsPPC" feature, to distinguish ppc32 vs ppc64 targets, use this
to configure TargetData differently.  This not makes ppc64 blow up on lots
of stuff :)

llvm-svn: 28825
 2006-06-16 17:50:12 +00:00
Chris Lattner
fa884ac11b Rename some subtarget features. A CPU now can *have* 64-bit instructions, 
can in 32-bit mode we can choose to optionally *use* 64-bit registers.

llvm-svn: 28824
 2006-06-16 17:34:12 +00:00
Chris Lattner
aeb5a015cd First baby step towards ppc64 support. This adds a new -march=ppc64 backend 
that is currently just like ppc32 :)

llvm-svn: 28813
 2006-06-16 01:37:27 +00:00
Chris Lattner
4c7ba81f59 Add a note that Nate noticed. 
llvm-svn: 28808
 2006-06-15 21:33:31 +00:00
Jim Laskey
849c76e55c 1. Support standard dwarf format (was bootstrapping in Apple format.) 
2. Add vector support.

llvm-svn: 28807
 2006-06-15 20:51:43 +00:00
Evan Cheng
cc433bd065 Vector extract / insert index operand should have ptr type. 
llvm-svn: 28798
 2006-06-15 08:19:05 +00:00
Evan Cheng
32feafd76c Type of extract_element index operand should be iPTR. 
llvm-svn: 28797
 2006-06-15 08:18:06 +00:00
Evan Cheng
bc79e5f0e4 Type of vector extract / insert index operand should be iPTR. 
llvm-svn: 28796
 2006-06-15 08:14:54 +00:00
Evan Cheng
0e2235b803 X86 call instructions can take variable number of operands. Parameters of 
vector types are passed via XMM registers.

llvm-svn: 28789
 2006-06-14 22:24:55 +00:00
Chris Lattner
20c3c42c02 add a note 
llvm-svn: 28787
 2006-06-14 21:26:18 +00:00
Evan Cheng
242ebc9ab3 Add argument registers to the end of call operand list (partial fix). 
llvm-svn: 28783
 2006-06-14 18:17:40 +00:00
Jim Laskey
69d5018a05 Place dwarf headers at earliest possible point. Well behaved when skipping 
functions.

llvm-svn: 28781
 2006-06-14 11:35:03 +00:00
Andrew Lenharth
2263835c1d I am sure I had commited this workaround before. Perhaps soon I should sort it all out 
llvm-svn: 28772
 2006-06-13 20:34:47 +00:00
Andrew Lenharth
a903a21a85 It really helps to be returning to the correct place 
llvm-svn: 28769
 2006-06-13 18:27:39 +00:00
Chris Lattner
bbbcb8cceb Port some bugfixes in shift handling from SimplifyDemandedBits over to 
ComputeMaskedBits.  DemandedMasks and KnownZero/One masks should never have
bits set out of the range of the base datatype.

llvm-svn: 28768
 2006-06-13 16:52:37 +00:00
Jim Laskey
c9a71e96ae TargetLowering::ComputeMaskedBits was not clearing reciprocal bits on shifts. 
llvm-svn: 28765
 2006-06-13 13:08:58 +00:00
Evan Cheng
2a0f3b2e79 Cygwin support: use _alloca to allocate stack if > 4k. Patch by Anton Korobeynikov. 
llvm-svn: 28764
 2006-06-13 05:14:44 +00:00
Chris Lattner
6f45959365 Gaar! Don't use r11 for CR save/restore, use R0. R11 can be register 
allocated, thus live across the save/reload.  This fixes

llc-beta /MultiSource/Applications/spiff/spiff
llc-beta /MultiSource/Benchmarks/sim/sim:
llc-beta /MultiSource/Benchmarks/Ptrdist/bc/bc
llc-beta /MultiSource/Benchmarks/McCat/12-IOtest/iotest:
llc-beta /MultiSource/Benchmarks/FreeBench/fourinarow/fourinarow
llc-beta /MultiSource/Benchmarks/Fhourstones-3.1/fhourstones3.1
llc-beta /MultiSource/Benchmarks/mediabench/adpcm/rawdaudio/rawdaudio
llc-beta /MultiSource/Benchmarks/mediabench/adpcm/rawcaudio/rawcaudio
llc-beta /MultiSource/Benchmarks/mediabench/g721/g721encode/encode
llc-beta /MultiSource/Benchmarks/mediabench/jpeg/jpeg-6a/cjpeg

and probably others, with -regalloc=local.

llvm-svn: 28761
 2006-06-12 23:59:16 +00:00
Chris Lattner
93ed4373c4 Fix spilling and reloading of CR regs to reload the right values. This fixes 
Olden/power (and probably others) with -regalloc=local.

llvm-svn: 28760
 2006-06-12 21:50:57 +00:00
Andrew Lenharth
fe127f3de7 Let the alpha breakage begin. First Formals and RET. next Calls 
llvm-svn: 28753
 2006-06-12 18:09:24 +00:00
Andrew Lenharth
a2bda5b0e1 Start on my todo list 
llvm-svn: 28752
 2006-06-12 16:07:18 +00:00
Rafael Espindola
bcba226a99 lower more then 4 formal arguments. The offset is currently hard coded. 
implement SelectFrameIndex

llvm-svn: 28751
 2006-06-12 12:28:08 +00:00
Chris Lattner
7bc8eae1f0 Work around a nasty tblgen bug where it doesn't add operands for varargs 
nodes correctly.

llvm-svn: 28745
 2006-06-10 01:15:02 +00:00
Chris Lattner
b231c3d11c Fix a problem exposed by the local allocator. CALL instructions are not marked 
as using incoming argument registers, so the local allocator would clobber them
between their set and use.  To fix this, we give the call instructions a variable
number of uses in the CALL MachineInstr itself, so live variables understands
the live ranges of these register arguments.

llvm-svn: 28744
 2006-06-10 01:14:28 +00:00
Evan Cheng
9e5e585c89 Comments to appease sabre. 
llvm-svn: 28737
 2006-06-09 06:25:10 +00:00
Evan Cheng
8f46dba83d Minor compilation speed improvement. 
llvm-svn: 28736
 2006-06-09 06:24:42 +00:00
Chris Lattner
82b121e762 Add support for "m" inline asm constraints. 
llvm-svn: 28728
 2006-06-08 18:03:49 +00:00
Evan Cheng
2da9d803a4 Added X86FunctionInfo subclass of MachineFunction to record whether the 
function that is being lowered is forced to use FP. Currently this is only
true for main() / Cygwin.

llvm-svn: 28703
 2006-06-06 23:30:24 +00:00
Chris Lattner
3dbb345389 Now that PR633 is implemented, the CBE can know to emit _setjmp/_longjmp 
when available.  This speeds up hexxagon from 18.61s to 16.61s with the CBE on
PPC Mac OS (for reference, LLC is 15.48s and GCC is 23.35s).

llvm-svn: 28697
 2006-06-06 21:45:47 +00:00
Chris Lattner
bfbee64ecf Add PowerPC intrinsics to support dcbz[l] 
llvm-svn: 28696
 2006-06-06 21:29:23 +00:00
Rafael Espindola
42375303a6 add R0 to liveout 
expand "ret null" (implements test/Regression/CodeGen/ARM/ret_void.ll)
note that a Flag link is missing between the copy and the branch

llvm-svn: 28691
 2006-06-05 22:26:14 +00:00
Evan Cheng
8d9b7650f1 A few new entries. 
llvm-svn: 28683
 2006-06-04 09:08:00 +00:00
Evan Cheng
6fd191494f Be consistent with gcc. 
llvm-svn: 28682
 2006-06-04 07:24:07 +00:00
Andrew Lenharth
813c3dcf58 ignore ordered/unordered for now 
llvm-svn: 28679
 2006-06-04 00:25:51 +00:00
Evan Cheng
696779cea0 Cygwin support. Patch by Anton Korobeynikov! 
llvm-svn: 28672
 2006-06-02 22:38:37 +00:00
Evan Cheng
ddb0525a32 Use xor to clear a register. 
llvm-svn: 28667
 2006-06-02 21:20:34 +00:00
Evan Cheng
ed96100b00 Incorrect AT&T opcode. 
llvm-svn: 28666
 2006-06-02 21:09:10 +00:00
Chris Lattner
d14d882c4a Add mingw support, patch contributed by Anton 
llvm-svn: 28661
 2006-06-02 18:54:01 +00:00
Chris Lattner
1d2618c6c7 Silence -pedantic warning 
llvm-svn: 28633
 2006-06-01 17:17:06 +00:00
Chris Lattner
ac3d91f023 Silence -pedantic warning. 
llvm-svn: 28630
 2006-06-01 17:13:10 +00:00
Evan Cheng
4966cad9b5 Typos 
llvm-svn: 28617
 2006-06-01 05:53:27 +00:00
Reid Spencer
4b26f88ec9 For PR786: 
Don't warn about -pedantic errors. Add a note to the PR instead.

llvm-svn: 28616
 2006-06-01 05:49:51 +00:00
Reid Spencer
cf025eb201 For PR786: 
Turn -pedantic and -Wno-long-long compile flags on by default. In a few
places, avoid the warnings by removing these options in the local makefile.
One notable exception: lib/Target/CBackend/Writer.cpp. These warnings are
left on as a reminder to developers to clean them up.

llvm-svn: 28614
 2006-06-01 01:55:21 +00:00
Reid Spencer
94a443bb29 Use archive libraries instead of object files for VMCore, BCReader, 
BCWriter, and bzip2 libraries. Adjust the various makefiles to accommodate
these changes. This was done to speed up link times.

llvm-svn: 28610
 2006-06-01 01:30:27 +00:00
Evan Cheng
15c1f84762 Remove a warning 
llvm-svn: 28607
 2006-06-01 00:30:39 +00:00
Evan Cheng
4488266c46 Rename ASM modifier trunc8, trunc16 to subreg8, subreg16. 
llvm-svn: 28606
 2006-05-31 22:34:26 +00:00
Reid Spencer
30d5eade2a Fix casting so there's no warning on Alpha. 
llvm-svn: 28605
 2006-05-31 22:26:11 +00:00
Evan Cheng
f90443c471 Sign extender 
llvm-svn: 28603
 2006-05-31 22:05:11 +00:00
Evan Cheng
889544823a Rename instructions for consistency sake. 
llvm-svn: 28594
 2006-05-31 19:00:07 +00:00
Evan Cheng
abbbe57ba2 Select vector_shuffle v1, undef <2, 3, ?, ?> to MOVHLPS. 
llvm-svn: 28582
 2006-05-31 00:51:37 +00:00
Evan Cheng
82db95cd32 Remove dead code. 
llvm-svn: 28581
 2006-05-31 00:50:42 +00:00
Evan Cheng
8dc7251083 A new entry 
llvm-svn: 28579
 2006-05-30 23:56:31 +00:00
Evan Cheng
c024ad7f32 MAXP{D|S} and MINP{D|S} are commutable. 
llvm-svn: 28578
 2006-05-30 23:47:30 +00:00
Evan Cheng
e2397256c1 Commute shufps / shufpd. 
llvm-svn: 28577
 2006-05-30 23:34:30 +00:00
Evan Cheng
88bd79b75b Somehow I lost a condition when I was shuffling some code around. Anyway, 
only transform a shufps to pshufd when the first two operands are the same.

llvm-svn: 28575
 2006-05-30 22:13:36 +00:00
Evan Cheng
bdb6af8e7d Fix a build breaker. 
llvm-svn: 28574
 2006-05-30 21:45:53 +00:00
Evan Cheng
66bfb1dc9a Oops. PSHUFD is only available with SSE2. 
llvm-svn: 28573
 2006-05-30 21:30:59 +00:00
Chris Lattner
a5c50baaf5 Add a note 
llvm-svn: 28572
 2006-05-30 21:29:15 +00:00
Chris Lattner
31b150e334 Always reserve space for 8 spilled GPRs. GCC apparently assumes that this 
space will be available, even if the callee isn't varargs.

llvm-svn: 28571
 2006-05-30 21:21:04 +00:00
Evan Cheng
03ca651244 Allow shufps x, x, mask to be converted to pshufd x, mask to save a move. 
llvm-svn: 28565
 2006-05-30 20:26:50 +00:00
Evan Cheng
d7e0bab7f0 Remove bogus comment. 
llvm-svn: 28564
 2006-05-30 20:24:48 +00:00
Rafael Espindola
1bf57da16e Expand ret into "CopyToReg;BRIND" 
llvm-svn: 28559
 2006-05-30 17:33:19 +00:00
Evan Cheng
ced05ab1b4 Add a note about integer multiplication by constants. 
llvm-svn: 28551
 2006-05-30 07:37:37 +00:00
Evan Cheng
f7637e403f A addressing mode folding enhancement: 
Fold c2 in (x << c1) | c2 where (c2 < c1)
e.g.
int test(int x) {
  return (x << 3) + 7;
}

This can be codegen'd as:
leal 7(,%eax,8), %eax

llvm-svn: 28550
 2006-05-30 06:59:36 +00:00
Evan Cheng
1891844780 Some new entries about truncate / anyext 
llvm-svn: 28548
 2006-05-30 06:23:50 +00:00
Chris Lattner
e1552475d3 Ignore generated files 
llvm-svn: 28520
 2006-05-27 01:23:30 +00:00
Evan Cheng
de0f25081a Change RET node to include signness information of the return values. i.e. 
RET chain, value1, sign1, value2, sign2, ...

llvm-svn: 28510
 2006-05-26 23:10:12 +00:00
Evan Cheng
25db1a52d2 Vector argument must be passed in memory location aligned on 16-byte boundary. 
llvm-svn: 28505
 2006-05-26 20:37:47 +00:00
Evan Cheng
7f468901bb Mac OS X ABI document lied. The first four XMM registers are used to pass 
vector arguments, not three.

llvm-svn: 28504
 2006-05-26 19:22:06 +00:00
Evan Cheng
629df0afb2 Minor update to make the code more clear 
llvm-svn: 28499
 2006-05-26 18:39:59 +00:00
Evan Cheng
bde90b2732 Update more comments. 
llvm-svn: 28498
 2006-05-26 18:37:16 +00:00
Evan Cheng
414c909954 Fix some comments. 
llvm-svn: 28497
 2006-05-26 18:25:43 +00:00
Evan Cheng
a4b6f4749d No need to handle illegal types. 
llvm-svn: 28496
 2006-05-26 18:22:49 +00:00
Rafael Espindola
f7c5af4863 On ARM, alignment is in bits 
Add lr as a hard coded operand of bx

llvm-svn: 28494
 2006-05-26 10:56:17 +00:00
Evan Cheng
c80154a36e Remove a couple of bogus casts. 
llvm-svn: 28493
 2006-05-26 08:04:31 +00:00
Evan Cheng
77b8eaf292 Minor bug caught by Ashwin Chandra 
llvm-svn: 28491
 2006-05-26 06:22:34 +00:00
Evan Cheng
f610c3e318 Consistency 
llvm-svn: 28488
 2006-05-25 23:31:23 +00:00
Evan Cheng
fb5e64ff9e Some clean up. 
llvm-svn: 28483
 2006-05-25 22:38:31 +00:00
Chris Lattner
5e1d6724da Add support for the missing FP condition codes 
llvm-svn: 28482
 2006-05-25 22:26:02 +00:00
Evan Cheng
ee280ac5d0 Remove some dead code. 
llvm-svn: 28481
 2006-05-25 22:25:52 +00:00
Evan Cheng
564c7ac8f6 X86 / Cygwin asm / alignment fixes. 
Patch contributed by Anton Korobeynikov!

llvm-svn: 28480
 2006-05-25 21:59:08 +00:00
Evan Cheng
abb909e3bb Build breakage. 
llvm-svn: 28475
 2006-05-25 18:56:34 +00:00
Chris Lattner
cbcad040b3 Fix build failure of povray 
llvm-svn: 28473
 2006-05-25 18:06:16 +00:00
Chris Lattner
e3059fb8bd Fix Benchmarks/MallocBench/cfrac 
llvm-svn: 28471
 2006-05-25 16:54:16 +00:00
Rafael Espindola
31b98f8e04 implement initial version of ARMAsmPrinter::printOperand 
llvm-svn: 28470
 2006-05-25 12:57:06 +00:00
Rafael Espindola
90eec6b0f7 port the ARM backend to use ISD::CALL instead of LowerCallTo 
llvm-svn: 28469
 2006-05-25 11:00:18 +00:00
Evan Cheng
bb17ad5ffa Switch X86 over to a call-selection model where the lowering code creates 
the copyto/fromregs instead of making the X86ISD::CALL selection code create
them.

llvm-svn: 28463
 2006-05-25 00:59:30 +00:00
Evan Cheng
4a74dd0c51 CALL node change (arg / sign pairs instead of just arguments). 
llvm-svn: 28462
 2006-05-25 00:57:32 +00:00
Evan Cheng
09942d3f8b Assert if InflightSet is not cleared after instruction selecting a BB. 
llvm-svn: 28459
 2006-05-25 00:24:28 +00:00
Evan Cheng
b040dd86af Clear HandleMap and ReplaceMap after instruction selection. Or it may cause 
non-deterministic behavior.

llvm-svn: 28454
 2006-05-24 20:46:25 +00:00
Reid Spencer
574d4e6992 For PR786: 
Minor tweaks in public headers and a few .cpp files so that LLVM can build
successfully with -pedantic and projects using LLVM with -pedantic don't
get warnings from LLVM. There's still more -pedantic warnings to fix.

llvm-svn: 28453
 2006-05-24 19:21:13 +00:00
Reid Spencer
e39b3b9bf0 For PR786: 
Remove a spurious ;

llvm-svn: 28452
 2006-05-24 19:05:21 +00:00
Chris Lattner
f604017e47 Patches to make the LLVM sources more -pedantic clean. Patch provided 
by Anton Korobeynikov!  This is a step towards closing PR786.

llvm-svn: 28447
 2006-05-24 17:04:05 +00:00
Chris Lattner
bc3be2ff8a Fix CodeGen/Generic/vector.ll:test_div with altivec. 
llvm-svn: 28445
 2006-05-24 00:15:25 +00:00
Chris Lattner
56862bbd53 Handle SETO* like we handle SET*, restoring behavior after Evan's setcc 
change.  This fixes PowerPC/fnegsel.ll.

llvm-svn: 28443
 2006-05-24 00:06:44 +00:00
Chris Lattner
2ce3eb8210 Print struct return functions and calls as actually returning the hidden 
argument struct pointer, enabling ABI compatibility for the CBE with
platforms with strange struct-return ABIs.  This fixes 252.eon and
CoyoteBench/fftbench on Darwin/X86 among other things.

llvm-svn: 28442
 2006-05-23 23:39:48 +00:00
Chris Lattner
ac9665d682 Fix file header comment 
llvm-svn: 28441
 2006-05-23 23:20:42 +00:00
Evan Cheng
3ef176507d Better way to check for vararg. 
llvm-svn: 28440
 2006-05-23 21:08:24 +00:00
Evan Cheng
65c3f3f26b Remove PreprocessCCCArguments and PreprocessFastCCArguments now that 
FORMAL_ARGUMENTS nodes include a token operand.

llvm-svn: 28439
 2006-05-23 21:06:34 +00:00